implementation of 11 level cascaded multilevel inverter using

IPASJ International Journal of Electrical Engineering (IIJEE) Web Site: http://www.ipasj.org/IIJEE/IIJEE.htm

A Publisher for Research Motivation........ Email: [email protected] Volume 2, Issue 10, October 2014 ISSN 2321-600X

Volume 2, Issue 10, October 2014 Page 20

ABSTRACT

This paper proposes a novel of large electric drives and utility applications require advanced power electronics converter to meet the high power demands. A multilevel inverter not only achieves high power ratings, but also improves the performance of the whole system in terms of harmonics, and stresses in the bearings of a motor. Referring to the literature reviews, the cascaded multilevel inverter (CMI) with separated DC sources is clearly the most feasible topology for use as a power inverter for medium & high power applications due to their modularization and extensibility. Multicarrier based level shifting pulse width modulation identified as the most promising technique to pursue for both technical and practical reasons. The thesis examined & compared the harmonic analysis of 11-level cascaded multilevel inverter with R and RL load through simulation.

Keywords—cascaded multilevel inverter (CMI), Multicarrier based level shifting PWM.

1. INTRODUCTION Many current and future designs will incorporate the use of induction motors as the primary source for traction in electric vehicles. Designs for heavy duty trucks and many military vehicles that have large electric drives will require advanced power electronic inverters to meet the high power demands (>250 KW). Development of electric drive trains for these large vehicles will result in increased fuel efficiency, lower emissions, and likely better vehicle performance (acceleration and braking). Multilevel inverters are uniquely suited for these applications because of the high VA ratings possible with these inverters. The multilevel voltage source inverters unique structure allows them to reach high voltages and power levels without the use of transformer. They are specially suited to high voltage vehicle drives where low output voltage total harmonic distortion (THD) and electromagnetic interference (EMI) are needed. The general function of the multilevel inverter is to synthesize a desired voltage from several levels of dc voltages. For this reason, multilevel inverters can easily provide the high power required of a large EV or HEV drive. 1.1 Concept of Multilevel Inverter The concept of multilevel converters has been introduced since 1975. The term multilevel began with the three-level converter. Subsequently, several multilevel converter topologies have been developed. However, the elementary concept of a multilevel converter to achieve higher power is to use a series of power semiconductor switches with several lower voltage dc sources to perform the power conversion by synthesizing a staircase voltage waveform. Capacitors, batteries, and renewable energy voltage sources can be used as the multiple dc voltage sources. The commutation of the power switches aggregate these multiple dc sources in order to achieve high voltage at the output; however, the rated voltage of the power semiconductor switches depends only upon the rating of the dc voltage sources to which they are connected. 1.2 Types of Multilevel Inverter The general structure of the multilevel inverter is to synthesize a near sinusoidal voltage from several levels of dc voltage. As the number of levels increases, the synthesized output waveform has more steps, which produce staircase wave that approaches a desired waveform. Also, as more steps are added to the waveform, the harmonic distortion of

Implementation of 11 Level Cascaded Multilevel Inverter Using Level Shifting Pulse Width

Modulation Technique With Different Loads

K.B.Bhaskar1, Dr.T.S.Sivakumaran2, M.Devi3

1Research Scholar, Bharath University, Chennai, India

2 Professor/Dean, Department of EEE, Arunai College of Engineering, Tiruvannamalai.

3 Assistant Professor, Department of EEE, Arunai College of Engineering, Tiruvannamalai.



Volume 2, Issue 10, October 2014 1

the output wave distortion of the output wave decrease. As the number of levels increases, the voltage that can be spanned by summing multiple voltages. The multilevel inverters can be classified into three types

Diode-Clamped Multilevel Inverter Flying Capacitor Multilevel Inverter Cascaded Multilevel Inverter

2. CASCADED MULTILEVEL INVERTERS 2.1 Introduction Among various configurations of multilevel inverters, cascaded multilevel inverter is important. An eleven level multilevel inverter consists of five H-bridge cascaded in single-phase. One H-bridge consisting of 4 IGBTs as shown in fig. 2.3(a). A multilevel inverter synthesize a desired voltage from several separate dc sources (SDCS’s), which may be obtained from batteries, fuel cells, or solar cells. Each SDCS is connected to a single-phase full- bridge inverter. Each H-bridge can generate three different voltage outputs (+vdc, 0 and -vdc) by the different combinations of the four switches (s1, s2, s3 and s4). The fig. 2.3(b) shows the switching pattern of four switches in a single H-bridge. One more alternative for a multilevel inverter is the cascaded multilevel inverter or series H-bridge inverter. Since then, the CMI has been utilized in a wide range of applications. With its modularity and flexibility, the CMI shows superiority in high-power applications, especially shunt and series connected FACTS controllers. The CMI synthesizes its output nearly sinusoidal voltage waveforms by combining many isolated voltage levels. By adding more H-bridge converters, the amount of Var can simply increased without redesign the power stage, and build-in redundancy against individual H-bridge converter failure can be realized. A series of single-phase full bridges makes up a phase for the inverter.

Fig 1.1: (a) One H-bridge with 4 IGBTs (b) Switching sequence of one H- bridges inverter.

A three-phase CMI topology is essentially composed of three identical phase legs of the series-chain of H-bridge converters, which can possibly generate different output voltage waveforms and offers the potential for AC system phase-balancing. This feature is impossible in other VSC topologies utilizing a common DC link. Since this topology consists of series power conversion cells, the voltage and power level may be easily scaled. The dc link supply for each full bridge converter is provided separately, and this is typically achieved using diode rectifiers fed from isolated secondary windings of a three-phase transformer. Phase-shifted transformers can supply the cells in medium-voltage systems in order to provide high power quality. 2.2Operation of CMLI The converter topology is based on the series connection of single-phase inverters with separate dc sources. Fig. 2.3 shows the power circuit for one phase leg of a three-level cascaded inverter. The resulting phase voltage is synthesized by the addition of the voltages generated by the different cells. In a 3-level cascaded inverter each single-phase full-bridge inverter generates three voltages at the output: +Vdc, 0, -Vdc (zero, positive dc voltage, and negative dc voltage). This is made possible by connecting the capacitors sequentially to the ac side via the power switches. The resulting output ac voltage swings from -Vdc to +Vdc with three levels, -2Vdc to +2Vdc with five-level, -3Vdc to +3Vdc with seven-level inverter and -5Vdc to +5Vdc eleven-level inverter. The staircase waveform is nearly sinusoidal, even without filtering. For a three-phase system, the output voltage of the three cascaded converters can be connected in either star (Y) or delta (Δ) configurations.

3. MODULATION TECHNIQUES 3.1 Definition of Modulation Mainly the power electronic converters are operated in the “switched mode” which means the switches within the converter are always in either one of the two states - turned off (no current flows), or turned on (saturated with only a small voltage drop across the switch). Any operation in the linear region, other than for the unavoidable transition from conducting to non-conducting, incurs an undesirable loss of efficiency and an unbearable rise in switch power




dissipation. To control the flow of power in the converter, the switches alternate between these two states (i.e. on and off). This happens rapidly enough that the inductors and capacitors at the input and output nodes of the converter average or filter the switched signal. The switched component is attenuated and the desired DC or low frequency AC component is retained. This process is called Pulse Width Modulation (PWM), since the desired average value is controlled by modulating the width of the pulses.

Figure 3.1 Modulation strategies for multilevel inverter

3.2 PWM AND LEVEL SHIFTED MODULATION 3.2.1. CLASSIFICATION OF CONTROL STRATEGIES The main aim of the modulation strategy of the multilevel inverter is to synthesize the output voltage as close as possible to the sinusoidal waveform. Many modulation techniques have been developed for harmonic reduction and switching loss minimization. The modulation methods used in multilevel inverters can be classified according to switching frequency, as shown in Figure 3.2. Methods that work with high switching frequencies have many commutations for the power semiconductors in one period of the fundamental output voltage. A very popular method in industrial application is the classic carrier-based sinusoidal PWM (SPWM) that uses the phase shifting technique to reduce the harmonics in the load voltage.

Figure 3.2 Classification of Multilevel Modulation Methods

3.2.2. PWM (PULSE WIDTH MODULATION): Pulse width modulation control is the most widely used method of controlling depth of inverter, including the multilevel family. A significant amount of research has been published on the various ways of implementing PWM control. The focus here is level shifting carrier based sinusoidal PWM schemes for controlling a flying-capacitor multilevel three-phase inverter. The main aim of this investigation is to ascertain which of the large number of possible implementations of multilevel sine-triangle PWM is the optimum for a cascaded multilevel inverter, using models of a practical implementation to help simulate as accurately as possible the complete system’s performance. The aim is also to develop a balancing control scheme applicable to all forms of PWM control. Pulse width modulation (PWM) is the basis for control in power electronics. The theoretically zero rise and fall time of an ideal PWM waveform represents a preferred way of driving modern semiconductors power devices.




3.3.3.Pwm Methods Of Carrier Based Techniques: Carrier based methods are simplest for the realization, yet not always straight forward to understand. The switching state of the inverter leg is determined by comparison of the modulating signal providing information on the voltage reference, and carrier signal providing information of the switching period Multilevel inverters are aimed at higher power applications and the semiconductor switch technology has inherent operating speed limitations due to higher switching losses. Therefore, the inverter switching frequencies must be relatively low, so that it is preferable to synchronize the triangular carrier to the reference sinusoid to optimize performance. The following analysis focuses predominantly on synchronous mode operation. The carrier-based PWM methods are traditionally used in analogy implementation of modulators, where the advantage of the continuous reference can be explained in full when switching instants are determined with a certain carrier frequency, the average voltage will be as close to the reference as possible. Nowadays, the control systems are digitally implemented, and therefore the references are not continuous but sampled. The same reference remains in force for a sampling period, which is now determined as Tsw . (a) LEVEL SHIFTED PWM METHOD: Another major aim is to identify the maximum energy factor for a PWM controlled cascaded multilevel inverter. In this case, it explores the different forms of multilevel sine-triangle PWM and bench-marks their performance under ideal system conditions. There are three alternative PWM strategies with different phase relationships for the level-shifted multicarrier modulation: In-phase disposition (IPD), where all carrier waveforms are in phase. Phase opposition disposition (POD), where all carrier waveforms above zero reference are in phase and are 180

degree out of phase with those below zero. Alternate phase disposition (APOD), where every carrier waveform is in out of phase with its neighbor carrier by

180 degree. (1) In Phase Disposition (IPD): In the present work, in the carrier-based implementation the phase disposition PWM scheme is used. Figure 5.3 demonstrates the sine-triangle method for a three-level inverter. Therein, the a-phase modulation signal is compared with two (n-1 in general) triangle waveforms. The rules for the in phase disposition method, when the number of level N = 3, are The N –1 = 3-1=2 carrier waveforms are arranged so that every carrier is in phase. The converter is switched to +Vdc/ 2 when the reference is greater than both carrier waveforms. The converter is switched to zero when the reference is greater than the lower carrier waveform but less than the

upper carrier waveform. The converter is switched to - Vdc/ 2 when the reference is less than both carrier waveforms.

In the carrier-based implementation, at every instant of time the modulation signals are compared with the carrier and depending on which is greater, the switching pulses are generated.

Figure 3.3 11-level PWM schema using 10 triangular carriers disposed to carry out PD-PWM

As seen from Figure 3.3, the figure illustrates the switching pattern produced by the carrier-based PWM scheme. In the PWM scheme there are two triangles, the upper triangle ranges from 1 to 0 and the lower triangle ranges from 0 to –1. In the similar way for an N –level inverter, the (N-1) triangles are used and each has a peak-to-peak value of 2/ (N-1). Hence the upper most triangle magnitude varies from 1 to (1-2/ (N-1)), second carrier waveform from (1-4/ (N-1)), and the bottom most triangle varies from (2-2/ (N-1)) to –1 It is clear from the figure that during the positive cycle of the modulation signal, when the modulation is greater than Triangle 1 and Triangle 2, then S1ap and S2ap are turned on and also during the positive cycle S2ap is completely turned on. When S1ap and S2ap are turned on, the converter switches to the + Vdc/ 2.When S1an and S2ap are on, the converter switches to zero and hence during the positive cycle S2ap is completely turned on and S1ap and S1an will be turning on and off and hence the converter switches from + Vdc/ 2 to 0.During the negative half cycle of the modulation signal the converter switches from 0 to - Vdc/ 2. The phase voltage equations for star-connected, balanced three-phase loads expressed in terms of the existence functions and input nodal voltage V30 = Vdc/ 2 , V20 = 0 , V10 = -Vdc/ 2.




4. PROPOSED CASCADED MULTILEVEL INVERTER 4.1.Operation of Proposed CMLI The improved configuration of a cascaded multilevel inverter is proposed to reduce harmonic distortion. Each inverter level can generate three different voltage outputs, +Vdc, 0, and –Vdc by connecting the dc source to the ac output by different combinations of the four switches, S1, S2, S3, and S4. To obtain +Vdc, switches S1 and S4 are turned on, whereas –Vdc can be obtained by turning on switches S2 and S3. By turning on S1 and S2 or S3 and S4, the output voltage is 0.The ac outputs of each of the different full-bridge inverter levels are connected in series such that the synthesized voltage waveform is the sum of the inverter outputs. The number of output phase voltage levels m in a cascade inverter is defined by m = 2s+1, where s is the number of separate dc sources. An an 11-level cascaded H-bridge inverter with 5 SDCSs and 5 full bridges is shown in Figure 4.1.The phase voltage van = va1 + va2 + va3 + va4 + va5

Figure 4.1 Three phase structure of 11-level cascaded multilevel inverter

The conducting angles, θ1, θ2, ...θs, can be chosen such that the voltage total harmonic distortion is a minimum. Generally, these angles are chosen so that predominant lower frequency harmonics, 5th, 7th, 11th, and 13th, harmonics are eliminated. The inverter could be controlled to either regulate the power factor of the current drawn from the source or the bus voltage of the electrical system where the inverter was connected.

Figure 4.2 Output waveform three phase cascaded multilevel inverter.

Cascaded inverters are ideal for connecting renewable energy sources with an ac grid, because of the need for separate dc sources, which is the case in applications such as photovoltaic or fuel cells.

5 SIMULATION RESULTS 5.1single Phase 11-Level Cascaded Multilevel Inverter With Normal Pwm Method. 5.1.1 Simulation Model:




Figure 5.1 Simulation of single phase cascaded multilevel inverter

Figure 5.1 One leg 11-level cascaded multilevel inverter. Each H-bridge needs four IGBT’s. The pulse generator is given to cascaded 11-level inverter. 5.1.2 Single Phase Voltage Output Waveform.

Figure 5.2 Output waveform of single phase cascaded multilevel inverter

The cascaded 11-level inverter output signal is shown in the figure 5.2. Here the power electronics switches (IGBT) are used in both positive and negative side of the multi level inverter. 5.1.3 Switching Pattern For Single Phase CMLI

Figure 5.3 Switching pattern for one leg of 3-phase cascaded multilevel inverter

In fig 5.3, Each H-bridge unit generates a quasi-square waveform by phase shifting is positive and negative phase legs switching timings. Note that each switching device always conducts for 180, regardless of pulse width of the quasi- square waveform.




5.2 Three Phase 11 Level Cascaded Multilevel Inverter Using Pulse Generator 5.2.1Simulation Model

Figure 5.4 Simulation of three phase 11 level cascaded multilevel inverter using pulse generator.

Fig 5.4 Three leg 11 level cascaded inverter. Each H-bridge cell needs IGBT’s switches. The pulse generator is given to cascaded multilevel inverter. The 11-level inverter is connected to get the output 5.2.2 Three Phase Voltage Output Waveform.

Figure 5.5 Output voltage waveform of 3-phase 11-level cascaded multilevel inverter

The figure 5.5 shows the three phase 11 level output of cascaded multilevel inverter. Here the three phase output was phase shifted by 120 degrees. 5.2.3 Fft Analysis Of Cmli Using Pulse Generator:

Figure 5.6 FFT analysis of CMLI using pulse generator.




5.2.4 Theoritical Calculation For THD Using Pulse Generator The total harmonic distortion can be calculated using the formula

On subatituting the values of voltages and considering the value of n as 20, the equation changes to

On solving we get, THD = 46.77% 5.3 Multi-Carrier Level Shiftng Pwm 5.3.1 Switching Waveform Of Multi-Carrier Level Shiftng Pwm

Figure 5.7 Output Waveform of level shifting PWM

In fig 5.7, this waveform shows that the combination of carrier output signal and reference output signals are obtained by using level shifting PWM technique. 5.3.2 Single Phase Voltage Output Waveform using Multi-Carrier Level Shiftng Pwm.

Figure 5.8 Output voltage waveform of 11-level cascaded multilevel inverter

5.3.3 Three Phase Voltage Output Waveform using Multi-Carrier Level Shiftng Pwm:

Figure 5.9 Output voltage waveform of 3-phase 11-level cascaded multilevel inverter




5.3.4 FFT Analysis Of CMLI Using Level Shifting Multicarrier PWM Method:

Figure 5.10 FFT analysis of CMLI using pulse generator.

5.4 Three Phase 11 Level Cascaded Multilevel Inverter Using Level Shifting Multicarrier Pwm With Rl Load:

5.4.1 Three Phase Voltage Output Waveform:

Figure 5.11 Output voltage waveform of 3-phase 11-level cascaded multilevel inverter with RL load

5.4.2 FFT ANALYSIS OF CMLI WITH RL LOAD

5.12 Simulation Of Three Phase Cascaded Multilevel Inverter Using Level Shifting Pwm With Motor Load: 5.5 Three Phase 11 Level Cascaded Multilevel Inverter Using Level Shifting Multicarrier Pwm With Induction

Motor Load:




Figure 5.13 Simulation of single phase cascaded multilevel inverter using level shifting PWM

5.5.1 Output Voltage Waveform

Figure 5.14 Output voltage waveform with motor load.

5.5.2 Speed Waveform:

Figure 5.15 speed of the motor with load variations

5.5.3 Stator And Rotor Current Waveform




Figure 5.16 Stator and rotor Current of the motor with load variations

5.5.4 Torque Waveform

Figure 5.17 Torque of the motor with load variations

6.Conclusion IGBT based cascaded multilevel inverter fed induction motor modeled and simulated using the block of Simulink. It is able to maintain constant speed by maintaining constant voltage the simulation agree with the analytical prediction. The multilevel inverter fed induction motor is successfully simulated in MATLAB. The software system used in present work as obvious advantage using three phase supply. This drive can be used for variable speed applications like electrical vehicles, robotics etc., the proposed techniques was experimented using MATLAB Simulink software and result are verified. And also current, voltage, speed and torque waveform are plotted and also reduces harmonics and produce almost sinusoidal waveform.

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AUTHOR

K.B.Bhaskar received the BE degree in electrical and electronics engineering from Anna university, Chennai, Tamil Nadu, India in 2008 and ME degree in power electronics and drives from Anna university, Chennai, Tamil Nadu, India in 2011. He is currently working towards the Ph.D in Multilevel inverter in Bharath University, Chennai, India. Interested area power electronics and drives ,machine design,and intelligent control

Dr.T.S.Sivakumaran was born in Panruti,India, on December 18, 1969. He has obtained B.E (Electrical and Electronics) and M.Tech (Power Electronics) in 1998 and 2002 respectively from Annamalai University and VIT University and then Ph.D in Power Electronics & Intrumentation from Annamalai University, Chidambaram in 2009. He is currently Dean in Department of Electrical and Electronics Engineering, Arunai College of Engineering, Tiruvannamalai, India. He is presently

guiding twelve Ph.D scholars and so far guided eighty M.E students. His research papers (20) have been presented at IEEE / International Conferences in Hong Kong, India, Singapore, SriLanka, and Malaysia. He has two and eight publications respectively in national and International journals. He is currently working in the area of alternate topology for Matrix converter, Luo converters, soft switching PWM schemes and power electronics application towards power systems. His areas of interest are: modeling, simulation and implementation of intelligent control strategies for power electronic converters. He is a life member of Institution of Engineers (India), senior member of IEEE and Indian Society for Technical Education

M.Devi received the Bachelor degree in Electronics and Communication Engineering from Mailam Engineering College and Master degree in Power Electronics and Drives in Adhiparasakthi Engineering College affiliated to Anna University. She is currently Assistant Professor in Department of Electrical and Electronics Engineering, Arunai College of Engineering, Tiruvannamalai, India. Her areas of interest are: modeling, simulation and implementation of intelligent control strategies for power

electronic converters.

implementation of 11 level cascaded multilevel inverter using

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