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1 IME’s TSI Consortium on August 17, 2012 © IME-Singapore IME TSI Consortium Industry Forum 2.5D Heterogeneous Integration on Through Silicon Interposers 17 th August 2012 Institute of Microelectronics

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Page 1: IME TSI Consortium Industry Forum - Agency for Science ... TSI_consortium_Overview... · IME TSI Consortium Industry Forum ... Product Roadmap ... - Member-company inputs on project

1IME’s TSI Consortium on August 17, 2012© IME-Singapore

IME TSI ConsortiumIndustry Forum

2.5D Heterogeneous Integration on Through Silicon Interposers

17th August 2012

Institute of Microelectronics

Page 2: IME TSI Consortium Industry Forum - Agency for Science ... TSI_consortium_Overview... · IME TSI Consortium Industry Forum ... Product Roadmap ... - Member-company inputs on project

2IME’s TSI Consortium on August 17, 2012© IME-Singapore

IME Industry Forum on

2.5D Through Si Interposer (TSI) Consortium

Agenda Schedule

Registration 9:30AM

Welcome note, Overview of IME 2.5D TSI Consortium 10:00AM - 10:30AM

Industry Guest Presentations:

• Robert Patti, Tezzaron Semiconductor

• Anwar Mohammed, Huawei US R&D

10:30AM - 11:30AM

300mm Fab Tour, Lunch 11:30AM - 1:00PM

Technical Proposals for 2.5D TSI Consortium

• Electrical Design of 2.5D Functional Test Vehicle

• 300mm Fabrication flow for 2.5D TSI

• Assembly flow, Thin Wafer Handling for 2.5DTSI Vehicle

• PDK for Design Enablement of 2.5D TSI, Cost Modeling

• Thermo-mechanical issues, Thermal solution for 2.5D TSI Vehicle

1:00PM - 3:00 PM

Re-cap, Follow-up Communications 3:00PM - 3:15PM

Q&A, open discussion 3:15PM

Industry Forum Conclusion 4:00PM

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3IME’s TSI Consortium on August 17, 2012© IME-Singapore

Advanced Packaging

at IME

2.5D/3DIC

Si Photonics

Bio Electronics

Ruggedized Electronics

Green Electronics

GaN on Si Power

Electronics

Sensors Actuators and Microsystems

Miniaturized Medical Devices

• Integrated Fiber Coupling• Low-Cost MEMS-assisted

Passive/Active Packaging & Assembly

• Flip-Chip, micro-bumping & 2.5D Platform for O/E IC

• Thermal aware Packaging Innovation

• Nanowire Integration• Heterogeneous integration

(MEMs, Logic, Memory , Analog/RF, Photonics)

• Biosensor packaging• Microfluidics-integrated

biosensor array• TSV biosensor array

• Over 300oC / 30 kpsi reliability • Novel interconnection and

encapsulation materials >300oC

• MEMS sensor hermetic sealing for harsh environment

• Chip on Flexible Substrate• Biocompatible Encapsulation

for long term implantation• Flip Chip for MEMS structure

• Vacuum/Hermetic WLP with TSV

• Thin Film Encapsulation• Low Cost Solutions - MEMS-

ASIC Integration

• Low Cost, small size, high-reliable module packaging

• Reduced parasitics for higher efficiency

• Integrated thermal management solution

• 2.5D Heterogeneous integration (Logic, Memory , Analog/RF, Photonics) on TSI

• 3D multi-chip stacking

IME’s Advanced Packaging, 2.5D/3D IC Strategic Focus

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4IME’s TSI Consortium on August 17, 2012© IME-Singapore

EMWLP High Perf. Materials

Fine Pitch

Flip Chip

with Cu

Pillar

3D-TSVCu Wirebond

2.5D TSI

TSV-TSI 12” Engineering Line

Advanced Interconnect/Packaging Consortia

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5IME’s TSI Consortium on August 17, 2012© IME-Singapore

Market for Interposers Expected to be Strong

Market driven by Heterogeneous Integration: Logic-Logic, Logic + Memory, MEMS &

Sensors.

To address the growing market, a strong design, and manufacturing ecosystem is

needed.

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6IME’s TSI Consortium on August 17, 2012© IME-Singapore

SiXiS

FPGA + Memory (IME)

Requirements Data communication systems, and High Performance

MobileTablets

• Higher IO counts to support Wide Bus Architecture

• Lower Power, Higher Memory Bandwidth(access),

• Advantages from System Partitioning through

Heterogeneous Integration

FPGA + Memory + Optics I/O

(IME)

High Performance Tablets

2011

2013

2015

FPGA (Xilinx)

Data-center Infrastructure

2009

Bandwidth, Power-efficiency of Logic-Memory Systems

Driving 2.5D IC Landscape

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7IME’s TSI Consortium on August 17, 2012© IME-Singapore

PCB

Logic bare Die

3D DRAM bare

die

2.5D TSI Solves Wiring Density and Power Constraint.

Wiring Density Constraint: Solved by Tight pitch interconnects on TSI. This allows Wide I/O bus

and higher bandwidth.

DRAM Power-Bandwidth Constraint: Solved by using unbuffered LVCMOS IO Bare Die on TSI,

with Wide bus architecture.

Heterogeneous Integration: Bare dies are manufactured in their own optimized Silicon

technology.

IME’s TSI Consortium addresses Technology, Manufacturing, and Design challenges

encountered by 2.5D TSI industry ecosytem.

Logic

DRAM

PCB

DRAM

DRAM

DRAM

PKG/SUBS

PKG/SUBS

TSI

Conventional 2.5D TSI

2.5D

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8IME’s TSI Consortium on August 17, 2012© IME-Singapore

2.5D TSI Challenges: TSI Fabrication,

and 2.5D Assembly Flow

TSI Fabrication

- Large area for Heterogeneous Integration (lithography challenge)

- RDL, BEOL cost optimization, Low cost IPD,

- TSI Electrical Testing

2.5D TSI Assembly

- Chip-to-wafer Bonding.

- Temporary Bonding/Debonding (TBDB),

- Carrierless Alternative to TBDB for lower cost

TSI Cost

- Development of 2.5D TSI relative cost-model.

- Understanding of critical factors impacting TSI cost.

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9IME’s TSI Consortium on August 17, 2012© IME-Singapore

2.5D TSI Challenges: Design EDA Flow, Modeling

Thermo-Mechanical Modeling, Thermal Solution

- Warpage, Solder joint reliability Model for large area TSI, fully assembled

2.5D module

- Thermal solution for 2.5D TSI

PDK, Electrical Models, EDA Flow

- Accurate electrical models and PDK for TSI

- Open PDK for members to begin prototyping in TSI platform.

TSI Design Challenges for Heterogeneous integration

- TSI Wiring Density vs. Performance tradeoff.

- Metal Stack Optimization

- Signal, Power Integrity

- System Design on TSI (vs. PCB)

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10IME’s TSI Consortium on August 17, 2012© IME-Singapore

IME 2.5D TSI Consortium

2.5D TSI Consortium addresses technology, manufacturing,

design challenges faced by industry.

Member Companies

Product Roadmap

Technology, Design Requirements

Performance, Reliability requirements

Manufacturing Ramp Schedule

TSI Consortium Goals

TSI Technology Platform

Indepth understanding of

2.5D IC manufacturing.

Silicon Proven PDK

Design, manufacturing

flow for TSI products.

Cost optimization

Functional Vehicle

Stronger Manufacturing

Ecosystem,

IME

300mm, 200mm Fab,

Assembly

Modeling and

characterization

TSI Process integration

Package Design

Assembly process

optimization

Demonstration Vehicle

design

Reliability, FA

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11IME’s TSI Consortium on August 17, 2012© IME-Singapore

What IME 2.5D TSI Consortium Offers

Highlights

Technology Platform for Heterogeneous

Integration on 2.5D TSI

- TSI Fabrication

- 2.5D TSI Assembly flow

Design Enablement for 2.5D TSI

- PDK, EDA Flow

- Thermo-mechanical, Thermal Models

Demonstration Functional Vehicle for

Heterogeneous Integration

- Benefits of 2.5D TSI

- Optimization of overall design/manufacturing

flow

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12IME’s TSI Consortium on August 17, 2012© IME-Singapore

IME TSI Consortium Key Deliverables

• 26x44mm2 TSI die size

• Up to 52x44mm2 using double reticle

• Integrated Passive Devices (IPD)

Large area TSI to support rich Heterogeneous

Integration

• Chip to wafer bonding optimization for Heterogeneous Integration

• Address 2.5D TSI Assembly flow Challenges2.5D TSI Assembly Flow

• Early availability of PDK to consortium members (PEX/DRC/LVS etc)

• Electrical models for TSI interconnect components and IPD

• Silicon validation using Functional Vehicle.

TSI PDK on Industry Standard EDA Tools for

faster Prototyping

• MPW Capability for TSI prototyping by 2013

• Relative cost models for TSITime to Market

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13IME’s TSI Consortium on August 17, 2012© IME-Singapore

IME TSI Consortium Key Deliverables

• Carrierless alternative to thin wafer handling

• Improved Manufacturability compared to TBDB

• Lower Cost

Alternative approach to TBDB

• Wafer level and package-level thermo-mechanical models.

• Warpage prediction for large area TSI

• Solder joint reliability.

Thermo-mechanical Models

• Air cooled with heat sink on electrical module .

• Thermal Solution for FPGA + 3D DRAM 2.5D ICThermal Solution

• FPGA + 3D DRAM functional system for Tb/s applications

• Measurement of electrical performance: SI/PI, Speed, Power, Latency

• Reliability Assessment

High Performance Vehicle to demonstrate,

optimize 2.5D Integration

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14IME’s TSI Consortium on August 17, 2012© IME-Singapore

• Design Rules Manual

(DRM)

• EDA design kit

- Design rule checking

- LVS in EDA tool (inc.

spice models)

- Parasitic extraction

• Standard cells: TSV,

BEOL & FS/BS via/wires,

Inductors, Metal

Resistance, Bonds

(uBps,C4 Bps, Solder

balls)

• I/O library: To be

implemented in EDA

Design kit

Heterogeneous 2.5D

• FPGA + 3D Memory

• Cu BEOL interconnect

• Integrated Passive

Devices (IPD)

Low Cost

• RDL for front-side

interconnect.

• Reduce Organic

substrate layers to

reduce cost.

Applications, Vehicles

• TSV formation, (TSV

Via size/TSV depth

10μm/100μm)

- Si etch

- TSV liner

- Barrier/Seed PVD,

Cu ECP, CMP.

• BEOL process with

Cu Interconnects

• Integrated passives:

Resistor, Capacitor,

Inductor.

200mm/300mm

fabrication

RDL, Bumping, PKG

Assembly

• Cu pillar + SnAg

Micro-Bump (30μm

pitch)

• Multi-layer RDL

processing

• C2W & C2C bonding

• Wafer thinning

(50μm), under-filling

and Molding

• Thin wafer handling

for 12” TSV wafer

(50μm)

• Mechanical

- Stress & warpage

analysis

- Solder joint rel. & life

prediction

• Thermal

- Cooling solutions to

extract heat from the

3D

- Passive cooling

design

• Electrical

- Schematic/simulation

with 3D Full wave

solver

- Signal/Power Integrity.

DRIE CVD

PVD ECP CMP

Litho Cu + solder Micro-

bumping

Wafer level

Underfilling

Wafer molding C2W & C2C

Temporally

Bond/Debond

Backside Via

Revealing

Wafer Thinning RDL

Modeling, Simulation Process Design

Kit (PDK)

IME’s Manufacturing Capability for 2.5D ICs

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15IME’s TSI Consortium on August 17, 2012© IME-Singapore

• Process Design Kit (PDK): A key design enabler for 2.5D, 3D IC design and implementation.

3D Mem

Organic Substrate

FPGA

Metal lid + thermal interface

Through Si Interposer +TSV

PCB

IME’s TSI PDK Silicon-proven by

FPGA+3D DRAM Demonstration Vehicle

TSI Process Design Kit (PDK)

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16IME’s TSI Consortium on August 17, 2012© IME-Singapore

• TSI Reference flow allows for addressing critical design constraints early during IC integration on

TSI platform

• Optimization for reducing board/package/TSI level parasitics

• Thermo-mechanical and SI/PI analysis within TSI and Package (Co-design)

3D Memory and Logic on TSI

Physical Implementation using

IME PDK on EDA platform

TSI Package

Implementation

Electrical

(SI/PI,power,latency)

Thermo-Mechanical Effects

(Warpage, Solder-joint Reliability)

IME 2.5D

Models

TSI Warpage

Integration of Design and Manufacturing Flow for 2.5D TSI

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17IME’s TSI Consortium on August 17, 2012© IME-Singapore

Finalize project scope, TSI Technology,

Test Vehicle Specs.

Members inputs

300mm TSI Fabrication Flow

TSI Assembly Process Flow Development

Electrical

Char., PDK

development

2.5D TSI Fabrication and Assembly Flow Ready Silicon Verified PDK

Performance, Reliability Assessment

2.5D Test vehicle Fabrication, Assembly

Test Vehicle Design, Signoff

TSI Tapeout

Thermo-

mechanical,

Thermal

Models

TSI Consortium Project Flow

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18IME’s TSI Consortium on August 17, 2012© IME-Singapore

Consortium Duration: 24 months: Nov 2012 through Oct 2014

Consortium Preparation

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19IME’s TSI Consortium on August 17, 2012© IME-Singapore

Membership Structure

• Core membership is S$150,000/=

• Associate membership is S$80,000/=

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20IME’s TSI Consortium on August 17, 2012© IME-Singapore

Project Execution

Execution

- A project team will be formed with member companies

- The members in the project review meeting will direct the

consortium efforts to meet the project targets & review its progress.

- The members will have the choice to directly participate in the

experiments and contribute to the success of the project.

Communication

- Conference calls every 8 weeks (local members can attend in

person)

- Half-yearly on-site meetings at IME

- Periodic Reports and, conf. call Minutes.

- Member-company inputs on project steering a key ingredient to

project success.

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21IME’s TSI Consortium on August 17, 2012© IME-Singapore

Responsibility of IME & Consortium Members

IME

- To conduct research on the Project with the participation of the

Consortium members

- To co-ordinate activities relating to the Project, including organising the

Consortium meetings for the purpose of updating members on a regular

basis

- To report on the findings of the research work and to keep the Consortium

members informed

Consortium members

- To actively participate in the Project as and when required by the

Consortium for the purpose of carrying out and completing the Project

- To assist in contacting material suppliers as and when required by the

Consortium to carry out the Project

- To provide inputs that are required for the formulation of the Project work

scope and for the purpose of carrying out the Project

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22IME’s TSI Consortium on August 17, 2012© IME-Singapore

Feedback for Today’s Industry Forum

Before conclusion of today’s

industry forum, please

complete the hard copy of the

feedback form (provided to

you) and hand it to IME staff.

feedback

form

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23IME’s TSI Consortium on August 17, 2012© IME-Singapore

Provisional TSI Consortium Membership Reply SlipInstitute of Microelectronics

11, Science Park Road

Science Park II

Singapore 117685

Attention: Surya Bhattacharya

Tel: (65) 6770 5456

Fax: (65) 6774 5747

Email: [email protected]

2.5D Through Silicon Interposer (TSI) Consortium

Membership Reply Slip

We agree to participate in the 2.5D TSI Consortium under the name of ___________________________________ (Registered Company

Name) at a fee of

S$150,000/= for core-membership

S$80,000 for associate membership

Company :

Signed by for and on behalf of,

Signature :

Name :

Title : Date :

Our participation is conditioned on our review, acceptance, and signature of the member legal agreement. Our only obligation to this project,

if any, will be the terms and conditions contained in the member agreement which we sign.

Email :

Fax :

Tel :

Address :

• Please indicate your interest in the consortium by completing this reply slip and faxing OR sending us a scanned copy by 14th Sept 2012 (Friday).

• We will send you the official agreement for review. The aim is to formally start the project by 1st Oct 2012 (Monday).

• Your participation in this consortium will only be confirmed upon the signing of the official agreement.

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24IME’s TSI Consortium on August 17, 2012© IME-Singapore

Thank YouThank You.