imagine the future in telecommunications technology€¦ · imagine the future in...

Imagine the Future in Telecommunications Technology

D. Harame A.Joseph, D.Coolbaugh, G. Freeman1, K.Newton, S.M.Parker, R.Groves1, H.Zamat3, V.S.Marangos4, M.M.Doherty4,

O. Schreiber5,T.Tanji6, D.A.Herman1, M.Meghali2, R. Singh

IBM, 1000 River Rd., Essex Jct., VT 05452, Phone: (802) 769-9231, Email:[email protected], 2070 Rte. 52, Hopewell Junction, NY 125332IBM, Yorktown Heights, NY 105983IBM, Encinitas, California

4IBM, Lowell, Massachusetts5AMCC, 6290 Sequence Drive, San Diego, CA 92121 6AMCC, 6800 France Avenue South, Suite 305, Edina, MN 55435

Outline - Perspective

The Wired and Wireless PerspectiveRFCMOS ( definition and performance overview )SiGe BiCMOS Process ReviewSiGe BiCMOS Active DevicesSiGe BiCMOS Passive Devices and InterconnectsRF/Analog and Mixed Signal Design System ( Models and Design Automation )RF Analog Mixed Signal Application SpaceSiGe BiCMOS Product ExamplesSummary

Enterprise / Campus

Core

CustomerPremise

WAN

High-SpeedBackbone

CentralOffice

CentralOffice

LAN

Base Station

AccessSOHO / Consumer

SAN

ISP

Edge

Data Services

SAN

SONET

Ethernet

Fibre Channel

LAN

Storage Farm

Fibre Channel

CellularWireless LAN

The Broadband Network

The Evolution of the Broadband Network

Enterprise / Campus

Core

CustomerPremise

WAN

High-SpeedBackbone

CentralOffice

CentralOffice

LAN

Base Station

AccessSOHO / Consumer

SAN

ISP

Edge

Data Services

SAN

SONET 155M, 622M, 2.5G, 10G=> 40G==> 160G

LAN

Storage Farm

Fibre Channel 1, 2G => 10G

Ethernet 10/100M/1G => 10G==> 100G

Wireless LAN 1M,10M => 56 MbpsCellular 1G, 2G => 2.5G, 3G, 4G

Cellular Roadmap

1st GenerationVoice Only

2nd GenerationVoice / Messaging

wideband digitalvariable data rate

64 kbps vehicular384 kbps pedestrian2 Mbps stationary

phone with keypad

phone with screen

information appliance

200820072006

IBM

0

1

10

100

1000

10000

analog<9600 baud

digital9600-14000 baud

AMPS

TDMAGSMPDCCDMA

UWC-136W-CDMA

cdma2000 (3xRTT)

EDGEGPRS

cdma2000 (1xRTT)

2.5 GenerationVoice / Data

Digital -variable56-115 kbps 115-384 kbps

3rd GenerationVoice / Data / Media

phone with larger screen/enhanced services

US

EuropeJapanUS/Asia US

3G Evolution

3G + integration of WLAN

data

rate

(kbp

s)

Wireless SystemsPresent and future RF applications can divided into regions of data rate and mobility

Stationary: Connects over short distances- a few meters to 100 meters (eg IEEE 802.11b 2.4 GHz Wireless LAN)Walk: Connects over medium distances several 100 meters (eg 5 Ghz IEEE 802.11a Wireless LAN)Vehicle: Connects over long distances, use cellular phone protocols

Data Rate (Mb/s)0.1

4G

Station

aryW

alk

Vehicl

e

3rdGenerationMobile

Broadband RLANs:IEEE 802.11a, Hiperlan-2, MMAC

Future Very High-Speed RLANs

Mobility

Infrared (IrDA)BluetoothIEEE 802.11b

1.0 10 100 1000

Outline - RFCMOSThe Wired and Wireless PerspectiveRFCMOS ( definition and performance overview )SiGe BiCMOS Process ReviewSiGe BiCMOS Active DevicesSiGe BiCMOS Passive Devices and InterconnectsRF/Analog and Mixed Signal Design System ( Models and Design Automation )RF Analog Mixed Signal Application SpaceSiGe BiCMOS Product ExamplesSummary

RF-CMOS = Digital CMOS + Adders

0.25 µm foundry CMOS2.5 V FETs3.3 V dual ox option0 Vt FETsResistorsMOS capacitor

0.25 µm foundry RF CMOS technology

2.5 V FETs3.3 V dual ox options0 Vt FETsResistorsMOS varactorMOS and stacked MIM capsThick last metal (inductors)P- substrate

Device Level Design Kit RF Models & Layouts

Add MOS varactorAdd MIM capacitorAdd thick dielectric/metalAdd RF Layouts, Models & Device Level Design Kit

Digital CMOS

RF/Analog Adders

RF CMOS

Parameterized PCELL with call backs to model

RFCMOS Performance OverviewBuilds on low cost digital CMOS roadmapParameters that are scaling with 1/L are dramatically improving for example: fmax, fT, and Fmin

Digital scaling issues translate to RF/Analog issuesVdd not scaling = high tinv= limitations in gdsand self gain (gm/gds)

Double gate FINFET, asymmetric halos, and high K gates offer reliefNew materials introduction required by scaling may degrade 1/f noise

Layout must be optimized, especially W for multi-finger devices

Parameter Good News Bad Newsft ~ vsat / 2π L improves with 1/L Rs ultimately limitsfmax = (fT / 2)(gds (RG+RS) + 2πftRGCGD)-1/2 ~ ft (W/L) wide W limited by Rg long W

gm ~ vsat W Cox ~1/Ltinv, improves gm not scaling with L, limited by Rs < 45nm

Fmin = 1 + K*(f/fT)(gm(RG+RS))1/2 improves scaled W/L limited by Rg long W

gm/gds FINFETS, high K, asymetric halos new structures reguired

1/f Circuit innovation limiting impact

degrades with nitridi- zation and high K?

threshold matching - 33% degrade per litho generation

Outline - Process Review


Base-After Gate SiGe BiCMOS Integration Flow

Maintains CMOS structure and electrical characteristicsMajor thermal cycles prior to base depositionLow thermal-cycle HBT module

Ref: S. St Onge, BCTM 99

CMOS / Common Bipolar/Analog

Shallow Trench Isolation

FET Well ImplantsDual Gate Oxide & Gate FormationLDD Implants & AnnealsSpacer Formation

Silicide & ContactsStandard 2 to 6 Metal Layers

– Includes MIM Capacitor

Subcollector & n-EPI Deep Trench Isolation

Collector Plug Implant

Thick Metal Add-On Module

pFET S/D/G Implants nFET S/D/G Implants

HBT Module: Bipolar Window Open SiGe Epi Base Growth Extrinsic Base, Collector & Emitter Formation

Source/Drain and Emitter Anneal

Base EmitterCollector

Outline - Active Devices


Vertical scaling

Reduce transit time, increase fT

Kirk-effect extended to higher current densityVertical scaling with lateral scaling maintains constant current / device length for self-heating and current delivery

conc

entra

tion

IncreaseGe slope

Narrow Base

Increase Coll

depth

fT

Reducetransit time

Kirkeffectto highercurrent

current density

1E-4 1E-3 1E-2Ic (A)

0

50

100

150

200

250

Cut

off F

requ

ency

(GH

z)

IBM 8HP

IBM 7HP0.18 µm generation

IBM 5HP0.5 µm generation

10X current

1.75X performanceEmitter shrink

with increasing current density

SAT

CSCL

n

BCBEC

CEB

C vW

DWCRR

qIkTC

qIkT

2

2

++

+++=

γCSCLBCEECTf

τττττπ

+++==2

1

HBT lateral scalingParasitic R’s & C’s are principally in proximity to the emitter

Low RB & low CCB far from the intrinsic deviceChallenge is to minimize parasitic structures

Minimize outside elementsShrink intrinsic dimensionsFocus on overlap regions

New structures provide large leverage in parasitic reduction

Polysilicon diffused-in emitterImplanted

extrinsic base

Dielectric isolation

Patterned collector"pedestal" implant

Low resistance metal salicideE

B

C

Emitt

erEm

itter

Emitt

erEm

itter

Shrinking emitter width reduces unit area RB and increases unit area CCB

CBB

TMAX CR

ffπ8

≈

120 GHz peak fT SiGe HBT in 0.18µm SiGe BiCMOS

120GHz (peak-fT) attained at 7.5 mA/mm2S-Parameter measurements out to 100 GHzIdeal characteristics for h21, MAG, and U

0

10

20

30

40

50

60

70

80

90

100

110

120

130

1.E-04 1.E-03 1.E-02 1.E-01Collector Current (A)

fT a

nd fm

ax (G

Hz)

Ae = 0.2x6.4 um 2Vcb = 1.0V1 Lot / 3 wafs / 9 sites

fT

fmax

0

5

10

15

20

25

10 100

Frequency (GHz)

Mag

nitu

de (d

B)

h21

U

20 dB/dec

MAG

Outline - Passives and Interconnects


Menu of Passives in 0.18µm SiGe BiCMOSDiffusion, poly, and metal resistors available for designersCapacitors reliable for 5.0V operationVaractors for high tuning range and linear operation

Resistors Rs (O/Sq) TCR (ppm/C)Subcollector 8.1 1430N+ Diffusion 72 1910P+ Diffusion 105 1430P+ Polysilcon 270 50P Polysilicon 1600 -1178TaN 142 -750Capacitors Cp (fF/um2) VCC (+5/-5 ppm/V)MIM 1 <45MOS 2.6 -7500 / -1500Inductor L (nH) Max Q at 5 GHzAl - Spiral Inductor >=0.7 18Varactor Tuning Range Q @0.5 GHzCB Junction 1.64:1 90MOS Accumulation 3.1:1 300

Varactor Options

N+NOX

P+ Single Crystal Silicon

NOX

Custom Implant Varactor (1 mask adder)

C-B junction varactor

N-WELL

Accumulation Varactor

P+ Single Crystal Silicon

N+

N+N+

N+ Polysilicon

P+ Polysilicon

P+ Polysilicon

Custom ImplantN+ Subcollector

N+ Subcollector P-

P-

N

-3 -2.5 -2 -1.5 -1 -0.5 0Delta Voltage (V)

1

1.5

2

2.5

3

3.5

C /

Cm

in

MOS

Collector-Base

Custom Implant

Figures of Merit Tunability - Cmax/CminLinearityQ

MOS has the largest Tunability but has very poor linearity

CapacitorsFigures of Merit

CA=Capacitance per unit areaCBOT=parasitic capacitance to the substrate Q (FEOL a concern, process and layout innovation)

Main concernTradeoff between Capacitance and Reliabilty

FEOL CapacitorsHigher thermal cycles allow higher CA achieved than MIM Challenge is to Minimize Resistances (BiCMOS vs FET)Substrate and polysilicon layers, free vs dedicated steps

BEOL (Metal-Insulator-Metal MIM) CapacitorsDielectrics improving Oxide->Nitride->High KAluminum simple integration, Copper Damascene Integration issues

StrategyStackable Configurations

Reliabilty targets100K Power On Hours - 5V1-2 Million Square Microns Per Chip

Metal Mx+1

Top Plate

Base Plate Metal Layer Mx

Metal Mx+1

Top Plate

Middle Plate

Base Plate Metal Layer Mx

Nitride Ta2O50.01

0.1

1

10

100

ILEA

K@

3.6

V (u

A/s

q. c

m)

Dual nitride MIMTa2O5 data from Phillips Semiconductor website

ILEAK, Nitride ~< 140 x ILEAK, Ta2O5

Single MIM Dual MIM

Inductors

SPICE modelSPICE model

Silicon

Inductor Spiral

Via

Underpass

Si02

dielectricheight

(P-)

Figures of MeritQ = Power Stored/Power DissipatedL per unit area (intertwined)

Reduce parasitic spiral-to-substrate (C1,C2) and intra-spiral capacitance C3Reduce power consumption through substrate resistance, R3 ->0 or R3 ->infinityReduce parasitic resistance, R1, in the spiralE&M modeling results demonstrate the need for Thick Metal

Relevance of metal thickness for Inductors

Additional metal thicknessallows more "sidewall" for current flow, reducing effective resistance

Edge Current

More even distribution

Edge current

Expected areaof sidewallcurrent flow

4µm

2GHz Method of Moments E-M Simulation (SONNETTM) of multi-turn spiral current flow

High Q Inductors

Cross-section parallel Dual Metal Inductors

10-1 100 101 1020

5

10

15

20

25

301.1nH Spiral Inductor (Parallel Stack MA||E1)

Peak Qof 28

Last metal add on modules "Dual Metal Inductors"Last metal add on modules "Dual Metal Inductors"Option 1: Thick single last metal Option 1: Thick single last metal Option 2: dual thick last metal levelsOption 2: dual thick last metal levelsIncreased dielectric layersIncreased dielectric layers

Excellent Q values over very large frequency rangeExcellent Q values over very large frequency rangeExample: 1.1nH inductor Q >15 from 600 MHz - 9 GHzExample: 1.1nH inductor Q >15 from 600 MHz - 9 GHz

Al

Cu

Al

Al

Al

W

Silicon

1.1 nH Parallel Stack Inductor (MA - 4µm Al || E1 - 3µm Cu)25 um wire, 1.5 turns

MA 4µm

E1 3µm

D.Coolbaugh, MTT-S Int., p. 187, 2002

Outline - Models and Design Automation


Nominal Lot Characterization

Split Lot Characterization Device Physics Design Rules

Inline Electrical Data

DC + AC (+ large signal) Testsite Data-55C - 125C

Device Scaling equations

Statistical Process Description

Scalable Statistical Model across Temperature

Physical LayoutSimulator to Simulator Conversions

Requirements for RF/Analog ModelsHardware based, all devices characterized at RF frequenciesMatching, Corner and Monte Carlo Statistical capability includedMeasured across temperature (-55oC - 125oC)Extensive model to hardware comparisonsStandard-advanced model structures, multiple simulators supported

SiGe Custom Design MethodologyIBM RF/Analog Device Level Design Kit with industry standard toolsFor RF/Analog anIntegrated tool suite for interactive resimulation is a critical need (parasitic resimulations across all point tools)

IBM AMS Design Kit

Scalable HBT, FET and passive modelsRF & digital models/pcells for RF-CMOSSpiral inductors, stacked MIM, resistors, HA and MOS varactors, robust ESD structures

Frequency Domain Simulation

Agilent ADSXpedian GoldengateMentor Eldo-RF

Schematic CaptureCadence Composer

LayoutParameterized Cells (PCells)Virtuoso-XL LayoutEditor

Parasitic ExtractionCadence Coeffgen, PRE, LPE, Assura RCX & (Inductance)Sequence Columbus RF

Design VerificationLVS/DRCHierarchical Checking DIVA & AssuraMentor CalibreSynopsys Hercules

Res

imul

atio

n

GDS II

Mixed-Signal SimulationVerilog-A/MS template librariesCadence AMS DesignerAntrim AMSMentor AMS

Simulation Environment

Cadence Analog Artist

Device-level Transient Simulation

SpectreDirectSynopsys HSpiceMentor Eldo

Compact ModelsSkew File Parameters

Complex Mixed-Signal SOC Design Implementation

Different design environments require optimum tools, integrated to enable IC to be effectively designed

Design System Enablement is KEY!!!!

Floorplanning

Front End AMS HDLDesign and Simulation

Custom Design and Physical Design & Verification

Chip level Integration and Physical Verification

Selected Resimulation

SP&R (Digital) Physical Design

SP&R (Digital) Physical Design

Frequency Domain Simulation

Schematic Capture

Layout

Parasitic Extraction

Design Verification

Res

imul

atio

n

GDS II

Mixed-Signal Simulation

Simulation Environment

Device-level Transient Simulation

Compact Models

Analog and digital ware (signal Integrity Enabled)

Mixed-Signal HDL

Mixed-signal Mixed Level simulation, and custom layout

Analog and digital ware (signal Integrity Enabled)

IBM Tools (ASICs group) EDA Vendor Tools (COT)

Outline - Application Space


Bipolar advantages over MOSNoiseEarlier fT availabilityHigher voltage capabilityMore effective fT

gM ability to drive loads fT tolerancemismatchempirically fT,Bipolar = 2-3XfT,CMOS

0 50 100 150 200 250

Measured fT

0

5

10

15

20

Max

vo

ltag

e

SOI 8SF8RF6RF

SiGe 8HPSiGe 7HP

SiGe 5/6HP

SiGe 5HP

Bias-dependent limit range

Junction-limited

Gate-oxide limited

Year

6SF

7SF

8SF

9SF

1997 1998 1999 2000 2001 2002 2003 20040

50

100

150

200

250

CMOS fTBipolar fT

10Gbps

40Gbps

0.25 µm

0.18 µm 0.13 µm

0.10 µm

Dev

ice

Dev

ice

ff TT(G

Hz)

(GH

z)

0.13 µm SiGe BICMOS

0.18 µm SiGe BICMOS

0.5 µm SiGe BICMOS

25 50 75 100 1258

101214161820222426

Bipolar CML

nFET SCL

Prop

agat

ion

Del

ay (p

s)

Load (fF)

ITAIL= 3mA

0.18 µm CMOSfT =70GHz NFET

0.5 µm SiGefT=47GHz HBT

Delay ~ gM/(CIN+CLOAD)

Bipolar vs. CMOS Technology Tradeoffs

CMOS TechnologiesLower costLatest CMOS for highest speed and lowest power for large chipsFull ASIC infrastructure

BiCMOS TechnologiesCurrent driveHigh fT availabile at earlier timeSignal fidelityWidest set of passive elementsWell established modelling accuracy for analog applications

Network Product Circuits: Technology, Process, & Methodology requirements

Product Critical Issues Technology

RequirementsProcess Technology Methodology

Requirements

Transimpedance Amp (TIA)

Low NoiseHigh Transimpedance

Low NoiseHigh GainDecoupling/IsolationPassives (R, C)

SiGe BiCMOS Custom RF/analogRF package models

Postamplifier (PA) High Dynamic RangeLow NoiseLow Jitter

High GainLow JitterDecoupling/IsolationPassives (R, C)

SiGe BiCMOS orRF-CMOS < 10 Gb

Custom RF/analog

Laser Driver / Electroabsorption Modulator Driver

High Voltage Swings (high breakdown) Low Output Jitter

High BreakdownHigh-Q InductorsDecoupling/IsolationPassives (R, C)

SiGe BiCMOS Custom RF/analogRF package models

Stand-alone Ser/Des Jitter ToleranceJitter Generation

High-Q InductorsDecoupling/IsolationPassives (R, C)Logic

SiGe BiCMOS orRF - CMOS <= 10Gb (lower power)

Custom RF/AnalogCustom Logic

Integrated Ser/Des + Framer

Jitter ToleranceJitter GenerationIsolation

High-Q InductorsDecoupling/IsolationPassives (R, C)CMOS standard-cell logic

SiGe BiCMOS orRF - CMOS <= 10Gb (lower power, higher integration)

Custom RF/AnalogCustom LogicStandard cell CMOSMixed-Signal sim.

Backplane parallel bus, Switch chips, NPs

PowerJitterEase of IntegrationIsolation

Low PowerSmall AreaCMOS compatibleDominated by big D

RF-CMOSStandard CMOS

Custom RF/AnalogCustom LogicStandard cell CMOSMixed-Signal sim.

Wireless Application Space

Silicon Germanium BiCMOS and CMOS have characteristics that are matched to specific wireless applicationsAn application may be first implemented in SiGe BiCMOS and later implemented in an advanced CMOS offering

--Frequency Range----Frequency Range--

RFCMOS 9SF

RFCMOS 8SF

RFCMOS 6SF

0.25µm CMOSRF6SF

0.13µm CMOSRF8SF

0.10 µm CMOSRF9SF

SiGe-5HPSiGe 7WL SiGe-6HP0.18 µm SiGe BICMOS 7WL

0.5 µm SiGe BICMOS 5HP

0.25 µm SiGe BICMOS 6HP

CMOS Content

5-10GHz

2.5-5GHz

2.0-2.5GHz

0.9-2.0GHz < 0.9 GHz

100K - 1M+ gatesHighly

Integrated Wirless

Access SOC

Wireless MAC Solution

PlatformBluetooth

SOC

FPGABasestationTransciever

Platform

baseband processor all

protocols

20k - 100K gates10GHz 802.11,

3G UWBISM, 802.11 Integrated

GSMChipset

IF Digital Down

Converters

1K - 20K gates 3G5GHz802.11

Integrated 2.5G

Bluetooth Front end

GSM, DECT, Chipsets

GPS SOCHandset Chipsets

Negligible CMOS BasestationFront End

WCDMA 3G, UWB RF

Front End

WCDMA, GSM

Dual BandRF Front End

CDMA, GSM, DCS, PCS, Dual Band Front End

TDMA, CDMA, GSM Dual Band Front End

Outline - Product Examples


Tri-Band LNA/Image Reject Mixer

Product

Tri-band GSM Image Reject Mixer with LNA Features

900MHz, 1.8GHz and 1.9GHz operationLow power with sleep mode and single supply (3.0V) operationFully integrated differential design including LNA for improved performanceIntegrated IF phase shifter/combiner and LO quadrature generator which simplifies useFlexible design with external low sensitivity matching

CMOS compatible band select logic control

RCpoly-phasefilter

IF+

IF-

DCSLO

GSMLO

LOQuadGen.

4:1RF+

4:1

RF-

RF-

RF+

Band Control

Band sel.

Bias Control

VccLNA

VccMix

Sleep

LO LO LO LO

Frequency (MHz) 935-960 MHz (GSM)1.8-2.0GHz (DCS/PCS)

Cascade Gain 22 dB

NF 3.5 dBRF Input VSWR < 2:1

LO Input VSWR < 2:1

IIP3 -14 dBmLO Power 200mVp ECLSupply Voltage 2.7-3.3 V

Supply Current < 30 mA

Port Isolation (min) 20 dB (all ports)

Image Rejection > 30 dB

IF Frequency 400 MHzIF Load Impedance

600 Ω

Package TSSOP24Temperature -40 to +85C

0.5µm/3.3V SiGe BiCMOS GSM Power AmplifierQuad Band GMSK PA for maximum 4 slot operation (GPRS) GMSK (Gaussian Minimum Shift Key) PA serving 800MHz, 900MHz, 1800MHz and 1900MHzIntegrated bias and controlFabricated with a high breakdown SiGe BiCMOS technology optimized for PA (V.Ramachandran, GAAS 2002, Milan, Sept. 2002) Meets or exceeds all requirements including robustnessExcellent Thermal Performance (Si, min gain variation)Ability to integrate Predistortion circuits, Smart Bias etc.

-30-20

-100

1020

3040

50

1 1.5 2 2.5 3Control Voltage Vapc (V)

Pout

(dB

m)

010

2030

4050

6070

80

PAE

(%)

Pout PAE

C4 Bonded Chip

Module (Ceramic Substrate)

Parameters Measured 900 MHz

GSM Spec 900 MHz

Measured 1800 MHz

GSM Spec 1800 MHz

POUT dBm from antenna

35 34.5 32.5 31.5

PAE 60 >50 46 >45Robustness [email protected]*

50:1 10:1 10:1 >10:1

*35 dBm Pout into 50 Ω load

Ericsson Microelectronics 3.5V Quad Band GSM/GPRS power amplifier module PA 31603

Integrated VCO Results CB vs. HA Varactor

SiGe BiCMOS 5AM iVCOSiGe BiCMOS 5AM iVCOCB Varactor: 1.7:1CB Varactor: 1.7:1>8 band selection logic cores>8 band selection logic cores

SiGe BiCMOS 5DM iVCOSiGe BiCMOS 5DM iVCOHA Varactor: 3.3:1HA Varactor: 3.3:145% greater tuning range45% greater tuning range58% less VCO gain variation58% less VCO gain variation

2 band selection logic cores2 band selection logic cores50% active chip area reduction50% active chip area reduction

Example: TriQuint TQ3116 iVCOExample: TriQuint TQ3116 iVCOTwo tuning bands covering 3580-3980 Two tuning bands covering 3580-3980 MHzMHz-138 dBc/Hz phase noise-138 dBc/Hz phase noise3 x 3mm3 x 3mm22 package (85% area reduction package (85% area reduction over typical hybrid module)over typical hybrid module)

chip

Band SelectionLogic

RF

-3 -2.5 -2 -1.5 -1 -0.5 0

Delta Voltage (V)

1

1.5

2

2.5

3

3.5

C /

Cm

in

Hyperabrupt Collector-Base

Q > 100 @ 2-4 GHz

Intersil Wireless LAN Chipset>4 Million chip sets shipped

2.4 GHz (ISM Band)3 SiGe BICMOS + 1 CMOS chipsReplaces 8 chips (some GaAs) + board components

CAL ENABLE

IF DETECTOR OUTRECEIVE AGCBASEBAND RXI

BASEBAND RXQ

OFFSETCAL

I

Q

Σ

TRANSMIT IF AGCBASEBAND TXQBASEBAND TXI

IF_IN

IF_OUT

0/ 90 PLL MODULE IF 2X LO/VCO INCHARGE PUMP OUT3-WIRE INTERFACEREF IN

O

Specification HFA3726 (old)

HFA3783 SiGe

Units

Pin Count 80 48Radio Bit Rate 2 11 Mb/sReceiver Icc 70 36 mA2x Loc. Osc. Freq. 20-800 160-1200 MHzGain Control Limiter Tx and Rx

AGCRX Phase Balance +/- 4 +/- 2 degreesTx Carrier Suppression

-28 -30 dBc max

Phase detector Icc 0.8 0.1A mABaseband Coupling (DC with offset correction)

AC DC HFA3783(IF IQ Mod/Demod)

Alcatel 10Gbit/sec SONETτ 10 and 40 Gbps Circuits with IBM SiGe

First Experimental Multi Chip Reticle 18 x 18 mm²• All 10 Gbps circuits were first time right• The chips have been moved to production directly• The average circuit yield is > 90%

10 Gbps Clock and Data Recovery Multi Chip Module

8:1 MUX 13 Gbps5 V, 2.5 W2000 Tr.3 x 3 mm²Multi-chip

Reticule(18x18 mm2)10 product circuits

10 Gbit/sec Clock and Data Recovery multi chip module for SONET/SDH applications. The chip set consisted of 10 separate chips designed in IBM's 0.5µm SiGe BiCMOS process by Alcatel™ in 1996. All 10 Gbps circuits were first time right and were moved to production directly. The average circuit yield > 90%.

Modulator Driver

Courtesy AMCC

3.5V single-ended, 7V diffUp to 43 GbpsPW controlOff set adjustAmp. adjustVEE = -5.8V ... -5.2V

Modulator drivers operate at high voltage. 4.5 Volts across the Emitter Collector of a 2 V BVceo 0.18µm SiGe HBT

60 Gbps Bit Error Rate Test Set SHF Communication Technologies AG announces world's fastest Bit SHF Communication Technologies AG announces world's fastest Bit Error Rate Test SetError Rate Test Set

SHF5005A 4:1 Multiplexer and SHF5002A 1:4 DemultiplexerSHF5005A 4:1 Multiplexer and SHF5002A 1:4 Demultiplexer200 degree clock phase margin @ 50 Gbps200 degree clock phase margin @ 50 Gbpsinput sensitivity better than 60 mVinput sensitivity better than 60 mV

based on IBM SiGe7HP 4:1 mux & 1:4 demuxbased on IBM SiGe7HP 4:1 mux & 1:4 demux

Non-SiGe based BERT sets Non-SiGe based BERT sets operate at 42-43 Gbpsoperate at 42-43 Gbps

ApplicationApplication testing of optical links components using the most aggressive FEC testing of optical links components using the most aggressive FEC (Forward Error Correction) techniques (Forward Error Correction) techniques

POS/ATM SONET MapperSingle chip OC-48c SONET/SDH Mapper with integrated serializer / deserializer, integrated clock recovery (CDR), clock synthesis (CSU)

Highly integrated HBT and ASIC methodology

1.2M CMOS devices6K SiGe HBTsDie size 10.84x10.84 mm2

65 percent reduction in board real estate compared to existing solutions3.3V technology with 3.4W of typical power

IBM ASIC designed CMOSRF/Analog Custom IC design

Outline - SummaryThe Wired and Wireless PerspectiveRFCMOS ( definition and performance overview )SiGe BiCMOS Process ReviewSiGe BiCMOS Active DevicesSiGe BiCMOS Passive Devices and InterconnectsRF/Analog and Mixed Signal Design System ( Models and Design Automation )RF Analog Mixed Signal Application SpaceSiGe BiCMOS Product ExamplesSummary

SummaryToday's challenges to move data at fast rates are greater than ever

Wired networking data rates pushing technology 10Gb/s => 40 Gb/s => 160 Gb/s Wireless data transfer rates 0.1 =>100 Mb/s as 3G moves to 4G protocols

SiGe BiCMOS processBase after gate now the standard to decouple thermal cycles and achieve high fT, fMAX

Varactors, MIMs, Resistors, and thick dielectric/metal modules for inductors & TlinesSiGe HBTs continue to improve fT = 210 -> 275 GHz, fMAX = 280 GHz

Fastest circuits built to date are SiGe BiCMOS (3.9 pS RO delay) Integration capability will push SiGe BiCMOS into more and more application areas

SiGe BiCMOS products in wireless and wired applicationsWired technology: TIA, Post-Amp, Modulator driver, SerDes, & Integrated SerDes Framer Wireless building blocks and systems: LNA, PA, VCO, Synthesizer, Transmitters and Receivers, 5 GHz LAN, GSM and CDMA chipsets, 3G, & GPS

Demanding Requirements on technologyAdvanced RF Analog Technology Features (passives, thick dielectric/metal add on module)

Demanding Requirements on Design SystemRF layouts, device characterization, and advanced modelsDevice level design kits with accurate parasitic extraction in a highly integrated systemEnablement is KEY!

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