ieee’s hands on practical electronics (hope) lesson 8: transistors
TRANSCRIPT
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IEEE’sHands on Practical Electronics (HOPE)
Lesson 8: Transistors
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Last Week
• Transistors– Metal Oxide Semiconductor Field Effect Transistor
– Drain, Body, Source, Gate
– Function as an electronic switch
• NMOS– Gate voltage higher than source => current ON
– Gate voltage lower than source => current OFF
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This Week
• PMOS Transistors
• Review: NMOS Transistors
• PMOS Operation
• Lab
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PMOS
• For a PMOS, whichever terminal is biased at a higher potential (voltage) is called the source, the other is called the drain.
G
D
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B
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PMOS
• Fabrication will be discussed in a later lesson. Today, we’ll explain how PMOS transistors work.
G
D
S
B
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PMOS
• We saw this last week for NMOS.
• For a PMOS, N-type regions become P-type regions and vice versa.
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PMOS
• To turn on a PMOS, apply a voltage to the gate that is lower than the source voltage.
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PMOS
• A gate voltage higher than the source will not turn on the PMOS
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Review: NMOS Transistor
• Remember these pictures from last week?
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Review: NMOS Transistor
• With too LOW of a gate voltage, electrons cannot get through.
• No current flows.
N type N typeP type
No current
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Review: NMOS Transistor
• Apply a voltage to make the p-type material behave like n-type.
• Current flows.
N type N typeN type
Current
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Review: NMOS Transistor
• Gate voltage LOWER than source voltage
N type N typeP type
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Review: NMOS Transistor
• Gate voltage HIGHER than source voltage
N type N typeN type
Current
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PMOS Transistor
• With too HIGH a gate voltage, holes cannot get through: no current.
P type P typeN type
No current
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PMOS Transistor
• Apply a voltage to make the n-type material behave like p-type
P type P typeP type
Current
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PMOS Transistor
• Gate voltage HIGHER than source voltage
P type P typeN type
No current
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PMOS Transistor
• Gate voltage LOWER than source voltage
P type P typeP type
Current
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Summary
• You are given two different voltages (HIGH & LOW).
• Applying the two voltages to the terminals of a MOSFET and one of the two voltages to the gate, the following combinations are possible:
Type Gate Voltage
Current?
PMOS HIGH OFF
PMOS LOW ON
NMOS HIGH ON
NMOS LOW OFF
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Sample Circuit
• This is a graph of Id versus Vin
VDD
RD
+
vDS
–
iD
VDD
RD
+
vDS
–
iD
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Drain current
• This graph is an approximate graph of the drain current.
• The first portion behaves like a parabola.
• Then it flattens, and increasing the voltage does not increase the current. This is “saturation.”
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Digital Logic
• Digital Logic only concerns itself with ON or OFF
• ON can be considered to be above some value, and OFF can be considered to be below that value.
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Lab
• PMOS transistor is OFF
• Current does not flow
• LED is OFFDC
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Lab
• PMOS transistor is ON
• Current flows
• LED is ONDC
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Lab
• Be sure to connect all the wires – ask for help if you need it.
DC
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Lab
• Unplug the wire from the gate to 9V and plug that wire into ground.
• Do not just leave it “floating”!
DC
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Lab
• How does the circuit from last week compare to the circuit from this week?
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Lab
DC DC