BEHAVIOR OF MEMORY ELEMENTS

IN THE PRESENCE OF POWER SUPPLY DISTURBANCES

Hassanein Hamed Amer

Science Department American University

113 Kasr El Aini, Cairo, Egypt

Abstract

In this paper, the SPICE circuit simulator is used to simulate the behavior of two arbitrarily chosen memory elements in the

disturbances. A static analysis shows that both memory elements withstand the simulated supply sags and produce correct outputs. However, if the supply sag on ly affects the circuits producing the data and/or the clock signals applied to the memory element, errors may occur.

presence of power supply

1. Introduction

Temporary failures are a serious threat to the reliability of digital systems. It was shown in [l] that 80% of system failures are due to temporary rather than permanent failures. Therefore, it is very important to study the behavior of logic circuits in the presence of temporary failures.

Temporary failures can be either intermittent or transient [ 2 ] . Intermittent failures occur when a component is in the process of developing a permanent failure. Typical causes of intermittent failures are critical tolerances in timing and electrical parameters. Transient failures

are caused by externally induced signal perturbations due for example to @-particle radiation or power supply disturbances.

The transient failures caused by a-particle radiation are also called Single Event Upsets ( S E U ) - Several papers study the effect of SEU on logic circuits. In [ 3 ] , SEU are physically injected into a microprocessor system and the resulting errors are analyzed. This work is extended in [ 4 , 51 in order to study the effectiveness of several fault- handling mechanisms. In [ 6 ] , a very fast fault simulation environment is developed in order to evaluate the effect of SEU on synchronous sequential VLSI circuits. In [7], two fault modeling techniques for SEU are compared. In [ 8 ] , an experimental method is described for estimating the probability that transients due to SEU in combinational circuits propagate into memory elements. Finally, a new fault simulation approach is presented in [ 9 ] to handle the complex behavior of SEU. This approach uses a strength-based algorithm.

Power supply disturbances are another common cause of transient failures. Several researchers physically injected these

disturbances into digital systems. In [lo], for example, it is shown that failures caused by power supply disturbances can be modeled as delay faults. In [ 11 3 , the effect of power supply disturbances on dynamically- redundant fault-tolerant systems, is studied. The effect of power SUPPLY disturbances on microprocessors is also studied in [ 3 , 4, 51 and it is observed that errors are first manifested in the control signals but user registers are hardly affected by the disturbances.

This paper investigates the behavior of registers in the

disturbances by using the circuit-level simulator SPICE. Two memory elements are arbitrarily chosen: a D Flip-Flop from LSI [12] and a D latch from National [13]. Both memory elements are implemented in CMOS. Only the static behavior of the memory elements is studied. Voltage sags are applied to the power supply and the ability of the memory element to store the correct data is investigated. It is shown that the two implementations under study are relatively robust. When the power supply of the memory element is affected by the sag, there are no errors.

presence of power supply

The paper is organized as follows. Section 2 describes the simulated circuit and the shape of the power supply disturbance. Section 3 investigates the ability of both memory elements to make 0-1 and 1-0 transitions. Section 4 studies the ability of the memory elements to retain a logic 1 in the presence of the voltage sag. In Section 5, the results obtained in Sections 3 and 4 are discussed. Finally, the

conclusions of this research are presented in Section 6.

2 . Circui t Description

This Section describes the circuit simulated with SPICE. Figure 1 shows this circuit.

Vdat I Vmem

Memory

Vc'k I Element I ^.

Figure 1. Simulated Circuit

It consists of a memory element with a data input D and a clock input CK. Two inverters are connected to the D and CK inputs of the memory element to simulate an actual circuit environment. The memory element has two outputs: Q and Q'. Let Vmem be the supply of the memory element, Vdat the supply of the inverter connected to the data input and Vclk the supply of the inverter connected to the clock input. For the sake of generality, assume that Vmem, Vdat and Vclk are all independent, i.e., a sag on one supply does not necessarily affect the other two supplies. Consider, for example, the situation where data from one system is sampled by another system. Each system has its own power supply. In this case, a sag may only affect Vdat while Vmem and Vclk in the sampling system are correct. Similarly, the sag may affect Vmem and Vclk while Vdat remains correct.

Using SPICE, a voltage sag is

applied to the power supplies of the inverters and the memory element shown in Figure 1 and the outputs Q and Q‘ of the memory element are observed. There are seven cases to consider: a sag on Vmem, a sag on Vclk, a sag on Vdat, a sag on Vclk and Vdat, a sag on Vclk and Vmem, a sag on Vmem and Vdat and finally a sag on all three supplies, Vclk, Vdat and Vmem. Let the correct value of all three supplies be 5v. The shape of the power supply sag is chosen arbitrarily because typical disturbances vary greatly depending on system design and electromagnetic environment [5]. The sag used in this paper is shown in Figure 2; it has a magnitude of -3.5v., a duration of 50nsec, a fall time of 20nsec and a rise time of 30nsec.

xms\ I .5v. / s o n s

50ns

Figure 2. Voltage Sag

The simulations will attempt to answer two questions. The first question is whether or not the memory element can store the complement of the value initially stored in it in the presence of a sag. The second question is whether or not the memory element can retain a logic 1 in the presence of a sag. Both the D flip-flop from [12] and the D latch from [ 1 3 ] will be used to answer these two questions.

3. Effect of Sags on Output Transitions

This Section investigates the ability of a memory element to make an output transition in the presence of a power supply sag. The memory element in Figure 1 is first replaced by the D flip-flop from [12]. This flip-flop is positive-edge triggered. Two clock pulses are simulated. Before the first pulse, the data input D of the flip-flop is a logic 1 and before the second pulse, D is a logic 0. Two power supply sags are simulated during the two clock pulses. The sag starts before the rising edge of the clock and ends after the falling edge. The top three waveforms of Figure 3 show the timing relation between the clock pulses CK, the disturbed supply Vsag and the data input D .

The seven cases mentioned in Section 2 are analyzed. It is found that, in the four cases where Vmem is affected by the sag, the output response is the same. The four cases are: A sag on Vmem, a sag on Vmem and Vdat, a sag on Vmem and Vclk and finally, a sag on Vmem, Vdat and Vclk. Vsag in Figure 3 represents the voltage of the supply (or supplies) affected by the sag. The output response is also shown in Figure 3 . The Q output is initially 0 and Q’ is 1. Q switches to a logic 1 at the rising edge of the first clock pulse. However, because of the sag, the voltage at Q is not 5v. but 1.5v., which is the value of Vmem at that time. After Vmem goes back to 5v. , Q a l s o goes to 5v. The same is true for Q” except that it starts with a logic 1 of 5v., goes down to 1.5~. when the sag occurs, then goes to Ov. at the rising edge of

the first clock pulse.

5v. Vsag

I .5v. I D 5v. -

ov.

5v. 1.5v.

Q I r I I Q’ 5v.

1.5~. 7

Figure 3. l - t O and 041 Transitions

At the beginning of the second sag, Q goes to 1.5~. then becomes Ov. at the rising edge of the second clock pulse and remains a 0. Q’ jumps to 1.5~. at the rising edge of the second clock pulse and then jumps to 5v. at the end of the second sag.

If Vdat is the only supply affected by the sag, it is observed that a unidirectional error occurs during the 0-1 transition. The 1-0 transition is error-free. This behavior is expected since the value of the data signal follows Vdat and therefore, the flip-flop will interpret a logic 1 at 1.5~. as a logic 0 .

The remaining two cases are sags on Vclk alone or on Vclk and Vdat. Q and Q‘ remain unchanged and both O - t l and 1+0 transitions fail. The flip-flop does not respond a t all. T h i s behavior is similar to that of a flip-flop with a clock input stuck-at-0.

In summary, whenever Vmem is affected by the sag, the flip- flop makes correct transitions from 0-1 and from 1-0 except that the value of Voh for Q and Q’ follows Vmem. If Vmem is not affected by the sag, the flip- flop may produce erroneous outputs.

All simulations described above are then repeated with the D latch form [13] instead of the D flip-flop. The operation of the latch is different from that of the flip-flop because the latch is transparent but the flip-flop is not [ 2 ] . The latch output will follow the data input as long as the clock is high. At the falling edge of the clock, the information present at the data input is retained at Q . When comparing the results of the flip-flop simulations with those of the latch simulations, it is found they agree.

4 . Retaining a Logic 1.

It is obvious that a logic 1 will be affected by a power supply sag. This section studies the ability of the memory element to retain a stored logic 1 during the occurrence of a power supply sag. The seven cases analyzed i n Section 3 are simulated again with the D flip-flop from [ 1 2 1 - Figure 4 shows t h e input waveforms. Again two clock pulses are used. The data is constant at a logic 1. The sag occurs before the r i s i n g edge of the second clock pulse and ends after its falling edge. The first clock pulse is used to set Q to a logic 1 and Q’ to a logic 0. Q and Q f are then observed after the end of the sag. For error-free operation, Q should still be a logic 1 and Q’ a logic 0 after the voltage sag.

Vsag 5v.

1.5v. 1 D 5v.

5v.

I 1.5v. I Q

Q’ 5v.

I ov.

Figure 4. Retaining a Logic 1

If Vmem is affected by the sag (irrespective of whether or not Vdat and/or Vclk are also affected by the sag), Q does in fact remain a logic 1 and Q’ a logic 0. Figure 4 shows the waveforms for Q and Q ’ . During the sag, the value of the signal at Q is 1 . 5 ~ . instead of 5v. Q’ remains a 0. This is similar to the behavior of the flip-flop in Section 3 when Vmem was affected by the sag.

When Vclk is affected by the sag (irrespective of Vdat) , Q and Q f remain unchanged. When Vdat alone is affected by the sag, Q becomes a 0 and Q’ becomes a 1 after the rising edge of the second clock pulse. The corrupted data is interpreted as a 0 by the flip- flop thereby producing erroneous outputs.

All simulations (seven cases) are then repeated with the D latch from [13] instead of the D flip- flop and again, the results are the same.

5. Discussion

to indicate that a memory element is relatively robust in the presence of power supply sags. Among the seven cases studied, the case where the voltage sags affects the supplies of the memory element, the data circuit and the clock circuit is the most likely to occur. It represents the situation where the data, clock and memory circuits are all fed from the same power supply. The simulations with both the flip-flop and the latch showed that the data is stored correctly.

It is important to note, however, that the simulations done in this research do not address all parameters that may affect the behavior of memory elements. Some of these parameters are the design of the memory element, the Spice parameters used in the simulations, the timing of the power supply sags and the value of the sag. More simulations need to be run before any conclusive evidence can be drawn.

6 . Conclusion

This paper has investigated the effect of power supply sags on the behavior of memory elements. The Spice circuit simulator was used in the investigation of two different types of memory elements: a D flip-flop and a D latch. Two aspects of the operation of the memory element were studied: The ability to make transitions from 0 to 1 and from 1 to 0 in the presence of a power supply sag and the ability to retain a logic 1 in the presence of a sag. For completeness, it was assumed that there was no relation between the power supplies of t h e data, c lock and memory circuits.

The results obtained above seem

It was found that the two memory elements under study withstood the simulated voltage sags. The data was correctly stored except that the output voltage that represented a logic 1 was equal to the disturbed supply voltage. If the sags affected only the data circuit, unidirectional (1-0) errors occurred. If the sags affected the clock circuit but not the memory supply, an error occurred that could be modeled as a temporary stuck-at-0 fault on the clock signal.

It is important to note, however, that many parameters have been chosen arbitrarily in these simulations. The behavior of the memory elements when these parameters are changed is currently under investigation.

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AUTHOR

Hassanein Hamed Amer is an Associate Professor at the American University in Cairo, Egypt. He received his B.Sc. (1978) and M.Sc. (1981) in Electrical Engineering from Cairo University and Ph.D. (1987) from Stanford University a l s o in Electrical Engineering. He is a member of the IEEE and its Reliability Society since 1985. His research interests include reliability modeling, fault- tolerant computing, cache-memory systems, self-checking circuits, testing and temporary failures.