ieee eds mini-colloquium: wimnact 45 two dimensional ... · ieee eds mini-colloquium: wimnact 45,...

IEEE EDS Mini-Colloquium: WIMNACT 45, 2015, Hitoshi Wakabayashi, Tokyo Institute of Technology

IEEE EDS Mini-Colloquium: WIMNACT 45

Two Dimensional Material Device Technologies

11:15-11:45, Feb. 18th, Thursday, 2015

Hitoshi Wakabayashi,

Tokyo Institute of Technology

Agenda

Introduction

Advanced-CMOS Device Benchmarks

2D Material Device Technologies

w/ Transition-Metal Dichalcogenides (TMDs)

Conclusions

IEEE EDS Mini-Colloquium: WIMNACT 45, 2015, Hitoshi Wakabayashi, Tokyo Institute of Technology 2

Context computing society

Cloud

Fog

Internet of X (Things, Hearts, Minds and Everything), Smarter X


Progress of Transistors

Superimposed manner

Scaling

Perf

orm

an

ce [

a.u

.]

[Node]90 65 45 32 22 15 11 8

High mobility by channel strain

(Tensile-SiN, Compressive-SiN, e-SiGe, e-Si:C, etc.)

Metal/High-k gate

(Replace, Damascene, Gate-last, MIPS)

Tri-gates

(FinFET)

3D architecture?

(Taller fin, Nanowire)

New channel

materials?

D

S

Tri-gatesLch

Lch

D

DS

Gate

s

S

Lch

D

DS

Gate

s

S

Lch

S DMetal High-k

Lch

S D

130

Monolithic

devices?


SADP, 60→42-nm fin pitch (Wfin = 8 nm)

Subfin doping

Lg = 20 nm

13 #, 52nm pitch w/ airgap (Cpara17%↓)

0.0588um2 6T-SRAM

iedm14, 3.7, 14-nm FinFET, Intel, 1

iedm 2014


iedm14, 3.7, 14-nm FinFET, Intel, 2

Layout width = Z, Id/Z

~ 65 mV/dec., n: 60 mV/V, p: 75 mV/V

1.04 mA/um, 10 nA/um, 0.7 V

FinFETでRandom dVth↓


45 nm

Tinv = 1.4 nm

22 nm Logic

Tinv~1.3 nm

Small

Subthresholdslope

Drain induced barrier lowering (DIBL)

Intel devices

32 nm

Tinv = 1.3 nm

Ioff = 100 nA/um

Ioff = 100 nA/um Ioff =

10 nA/um


22 nm LogicTinv ~ 1.3 nm

Vdd = 0.80 V

Ioff= 10nA/um

14 nm LogicTinv ~ 1.3 nm

Vdd = 0.70 V

Ioff =10nA/um

Intel devices

22 nm SoCTinv ~ 1.3 nm

Vdd= 0.75 V

Ioff = 1 nA/um

Ioff = 10 nA/um SS~65mV/dec SS~65mV/dec

DIBL~60mV/VDIBL~75mV/V


Tech. node scaling

International Technology Roadmap for Semiconductors http://www.itrs.net/

Half-pitch scaling

Cost, Power, Speed

Technology node

Gate

Contact

Si

active

PitchContacted

gate pitch

90 65 45(40) 32(28) 22(20)

16(14) 11(10) 8(7)

x0.7 x0.7

x0.5

N N+1N-1

Plane

view

2000 2005 2010 2015 2020 20255

810

20

50

80100

200

Years

Featu

re s

ize [nm

]

Half−pitch production yearITRS 1999−2012 x0.7/3−years

Tech. nodepublish years− 2014 iedm

Intel production

node x0.7/2years

Intel

TSMC

IBM

http://www.itrs.net/


Pitch scaling

SADP, SAQP

Area scaling

SADP, SAQP

Area (cost) scaling per technology node

Gate

Contact

Si

active

PitchContacted

gate pitch

6 8 10 20 40 60 8010040

50

60708090

100

200

300

400

Technology node [nm]

Co

nta

cte

d g

ate

pitch

[n

m]

Node

Node0.5

− 2014 iedm

Intel

TSMC

IBM

6 8 10 20 40 60 80100

10−2

10−1

100


6T

−S

RA

M c

ell

siz

e [

um

2]

Node2

− 2014 iedm

Intel

TSMC

IBM

Node


Gate length scaling

SADP, SAQP

Voltage scaling

Vth limits

Lg and Tinv scaling

8 10 20 40 60 801000.1

0.2

0.4

0.6

0.8

1.0


Supply

voltage [V

]

Node

Node0.5

− 2014 iedm

TSMC

IBM

Intel

8 10 20 40 60 801005

7

910

20

40

60

80

100


Ga

te length

[n

m]

Node

Node0.5

− 2014 iedm

TSMC

IBM

Intel


Figure of merits for benchmark

Delay time(Cg+Cpara) Vdd / Ids = Ci x Lg x Vdd / Ion @Cg>>Cpara

= Cpara x Vdd / Ion @Cg<<Cpara

Power density [W/um2]Active fCV2 = I/CV x CiV2 = Vdd x Ion [A/um] / Lg [um]

Standby J_leak x Vdd


High mobility, Metal/High-k gate, Tri-gate

CV/I V/I

Tri-gate significantly improves performance.

5 910 20 60 1000.4

0.6

0.8

1.0

2.0

Power density [nW/um2]

ON

resis

tance (

V dd/I

on)

[kohm

−um

]

Published data −2013 Symp. on VLSI Tech.

M/Hk G

L

Tri−gate Logic

Strain−SiTri−gate S

oC

5 910 20 60 1000.4

0.6

0.8

1.0

2.0

4.0


Ga

te d

ela

y (

CV

/I)

[pse

c]

Published data −2013 Symp. on VLSI Tech.

M/Hk G

L

Tri−gate Logic

Strain−Si

Tri−gate S

oC


Vdd/Ion vs. Power density

Tri-gate improves the performance.

Increase in fin height is highly appropriated.

3 7 10 20 60 1000.4

0.6

0.8

1.0

2.0


ON

resis

tan

ce (

V dd/I

on)

[ko

hm

−u

m]

Published data −Symp. on VLSI Tech. 2013

MG

L/Hk−

1st

M/H

k GL

InGaA

s HEM

T Tri−

gate

Logic

Strain−Si

Tri−

gate S

oC

3 7 10 20 60 1000.2

0.4

0.6

0.8

1.0

2.0


ON

resis

tan

ce (

V dd/I

on)

[ko

hm

−u

m]

Published data −Symp. on VLSI Tech. 2013

InGaA

s HEM

T

Tri−gate SoC

x1.5 Fin height

x2.0 Fin height


Vdd/Ion - Power density

Intel performance: 14 nm = 22 nm

III-V devices: MIT > TSMC > imec > Intel

2 6 10 20 60 1000.3

0.5

0.7

0.91.0

2.0


ON

resis

tan

ce (

Vdd/I

on)

[koh

m−

um

] − 2014 iedm

Intel, InGaA

s HEM

T

Intel 14 nm

imec, InG

aAs Q

W

IBMIntel 22 nm

TSMC

, InAs Q

WMIT,

InGaA

s

MIS

FET


Intel SoC iedm12

Renesas, HV/MCUiedm12

Sony,CIS/Logicisscc12

Toyohashi U. of Tech.Bio. w/ Logic/RF

VL Tech. 08

Toshiba,3D FlashVL Tech. 07

Memory

More Moore x More than Moore


More-Comfort Direction

Performance balance is the key.

More Moore

MorethanMoore

More comfort

TargetCurrentI/F devices

Tokyo Tech.


Sony’s SmartEyeglass (Developer Edition)

3-mm thick hologram, Optical transmittance: 85% Green monochrome, 419 x 138 pixels, 15 fps,

256 gradations Diagonal 20° (19° x 6°), luminance: 1,000 cd/m2

150-min battery life, 77-g eyewear

In near future, smarter high-performance color imaging are expected by using transparent devices.

Available pre-order in Germany and UK

https://developer.sony.com/develop/wearables/smarteyeglass-sdk/


High-drivability FinFETLarge Weff/Wfootprint

Taller Fin

Narrow Fin pitch

Thinner Fin

Mobility degradations in thin Si < 10 nm for both electron & hole.

High-mobility2D channels

Thin-Si channels?

K. Uchida, et. al., IEDM, 23.1, 2008. S. Kobayashi, et. al., J. Appl. Phys. 106, 024511 (2009).


Monolayer MX2 MoX2 & WX2

TMD band structure

Jun Kang, et. al., Applied Physics Letters 102, 012111 (2013).

MoS

MoS2

0.65 nm

MoS

Tokyo Tech.

MoS2


Benchmarks for display

TMD: Transitionmetal di-chalcogenide

c-Si poly-Si a-Si InGaZnO Organic Graphene TMD

Band gap [eV] 1.12 1.12 2 3 ~ 3 0 ~ 1.8

Mobility 1600 450 2 20 10 >10,000 200~5000

Temp. [℃] 1000 600 200 R.T. ~ 100 R.T. ~ 600

Flexibility × × × × ○○ ○ ○

Clearness × × × ○ ○ ○ ○

MoS

MoS2

0.65 nm

MoS

Tokyo Tech.


Exfoliation

Scotch tape

Liquid Exfoliation

Dipping & annealing

Synthesis of MoS2

Valeria Nicolosi et al., Science, 2013: Vol. 340 no. 6139 Keng-Ku Liu et al., Nano Lett., 2012, 12 (3), pp 1538–1544


Chemical vapor deposition (CVD)

RF magnetron sputtering

Synthesis of MoS2

H. Wang, et. al., IEDM, 4.6, 2012.

Takumi Ohashi, Bachelor thesis, Tokyo Institute of

Technology, 2014.

MoS2 Target

Substrate

RF

Ar+

Accelerated

Ar ions

Plasma Ar+

Tokyo Tech.


217 cm2/Vs, electron

Depletion mode

Exfoliated single-layer MoS2 nMISFET, EPFL

B. Radisavljevic et al., Nature Nanotech. 6, 147 (2011)


~ 4 nm 6 MLs Depletion mode

Exfoliated 6-layer MoS2 nMISFET, Purdue

Lingming Yang, et. al., Symposium on VLSI Technology 2014, T-21.6.


Siloxane SiO2

n-type by sodium

Silanol SiO2

n-type by sodium

n-type Ef pinning due to sodium (Na)

Only MoS2

MoS2/no-defect/SiO2

MoS2/Na/SiO2

MoS2/H/SiO2

MoS2/Dangling-bonds/SiO2

Only SiO2

Kapildeb Dolui, et. al., Phys. Rev. B 87, 165402, 2 April 2013.


Mobility ~ 190 cm2/Vs

Depletion mode

CVD-single-layer MoS2 nMISFET, MIT

H. Wang, et. al., IEDM, 4.6, 2012.

Perylene-3,4,9,10-tetracarboxylic acid tetrapotassium salt (PTAS) acts as a seed for monolayer metal sulfides by catalyzing reduced metal oxides onto various substrates.

http://www.2dsemiconductors.com/perylene-tetracarboxylic-

acid-tetrapotassium-PTAS-p/ptas.htm


3 nm thick

Several layers

~ 1017 cm-3

Sputter-MoS2 directly on SiO2 (visit posters)

Tokyo Tech.

T. Ohashi, K. Kakushima, K Tsutsui, H. Iwai, H. Wakabayashi, et al., SSDM, 2014.

5 nm

SiO2Carbon-

Passivation

Tokyo Tech.


Natural Human Interface Society

More Moore, More than Moore & More Comfort

5-nm Si MOSFET

2050

> 1 Peta Tr’s/chip(x 106 than now)

# o

f Tr’

s

Populationw/w (7G)

Cerebrums(14G)

Cerebellums(100G)100G

10G

1G

100M

10M

Metal-gate Si MOSFET

1T

10T

100T

1Peta

● 14 nm (1.3G)

2000 2010 2020 2030

Year of Production


Conclusions

Advanced-CMOS Device Benchmarks

FinFET: Large Weff/Wfootprint

NW, III-V FET, Monolithic Tr.

Transition-Metal Dichalcogenides (TMDs) for 2D FETs

More Moore

More than Moore

More comfort

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