Partial Scan: what Problem does it Solve?

R. G. Bennetts(*) and F. P. M. Beenker (**)

(*) Bennetts Associates, Burridge Farm, Burridge Southampton, SO3 7BY, UK

(**) Philips ED&T, WAY3.51, PO Box 80.000 5656 AA Eindhoven, The Netherlands

Abstract

There has been considemble market activity recently aboutpartial scan as a natutd extension of full scan techniques. In thispaper, we will set out the arguments for and against partial scan. The paper is an extension of an earlierpaper on full scan, “Scan Design: Fact and Fiction” [l].

1. The basic reasons for Design-for-Test

In engineering terms, we can quantify the quality of a product by the twin requirements of zero escape and zero defect. The former requires the test environment to possess the property of “excellent defect detection” whereas the latter requires the property of “excellent defect location”. Essentially, the tester acts as a filter, filtering good product from bad - see Figure 1.

The Tester as a Filter

Manufacture

P, OK

F, E F, OK

P, E

px Test F, OK Environment

I Chip or Board

>-,

i d L F i g u r e 1)

Unfortunately, the tester can pass bad products (P, not OK) and fail good products (F, OK). The observed yield at the tester may not be the real yield because of the presence of escapes and the failing of good products - see Figure 2.

I Apparent versus Input Yield I

Yield Y Pass Pass + Fail

(P,OK + PFK) Observed Yield =

(P.oK + PFK) + (F,OK + F,OK)

(P,OK + F,OK)

(P.OK + PSK) t (F,OK + F ~ K ) Actual yield =

I -[Figure 2)

The efficiency and accuracy of the yield measurement is a function of the defect-detection qualities of the test environment (test hardware and associated test program). Techniques such as scan offer such properties and meeting quality requirements can now be seen to be the motivating factors for incorporating DtT.

Figure 3 shows a typical relationship between the life-cycle activities of a VLSI product, and test. In general terms, thereare threedistinct formsoftesting: structural, functional parametric, and application mode.

99 0-8186-3360-3/93 $03.00 0 1993 IEEE

Test Objectives

Design Activities

Requirement

4

stnlclural Speaficalion

Layout

-[Figure 3)

Structural testing addresses the question - was the product assembled correctly according to the original build specification? Are all the components properly assembled? Were any defects (e.g. open-circuits, short-circuits) introduced by the manufacturing process itself?

Functional parametric testing concentrates more on the question of the functionality requirement of the product: does the product do what it is supposed to do? This question assumes two things: that the original specification is well- known and complete, and that there will be enough test time to answer the question. Both these assumptions may not be true, especially for complex VLSI devices such as microprocessors.

The parametric aspect of the functional parametric test refers to features such as frequency of operation, acceptable tolerances on power supply, expected temperature range, and so on.

The third form of testing, application-mode testing, takes place when all sub-units are assembled to form the final product. As the name implies, application-mode test looks at the overall performance of the final product in terms of its end use. It may be the last formal test activity before the product is shipped to the customer, but it is not the final test. That is carried out by the customer and based on what the customer finds, he or she will either judge the product to be aquality product (that is, theproduct meetstheirexpectation), or not to be a quality product. Customers who are satisfied with what they receive are more likely to buy more products from that particular supplier than those who perceive the product to be of low quality.

In reality, these various modes of test are carried out to varying degrees of sophistication as the processes of design, manufacture and ship proceed. Figure 4 shows a typical breakdown for a VLSI device.

Stages in Testing of VLSI Devices

(Figure 4)

The ability to perform these various test activities to very high standards is vital for the success of the product and the company. Design-for-Test (Dff) is the name given to the discipline to support this requirement; and Dff techniques are used for both digital and analogue electronic products.

Testability has been defined in the following way [2]:

"An electronic circuit is testable if test-patterns can be generated, evaluated, and applied in such a way as to satisfy pre-defined levels of performance (e.g. detection, location, application) within a pre-defined cost budget and timescale".

This definition is shown more visually in Figure 5.

r What is testability ?

I Evaluate

Fault Isolation Run Time Time-tdloner

(Figure 51

A proper interpretation of the definition implies a thorough understanding of the capabilities and limitations of the various tools and techniques used to produce a working test program. That is, the tester itself (usually seen to be a piece of hardware and therefore "easy" to characterise), the pattern-generation software if it exists (more difficult to

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characterise), and of course the “humanware” test programmers (virtually impossible to characterise!).

Newt State

Decoder

2. Background to scan

- __

Memory Output $ 4 Next State . MamoJ output 2 Elements b Decoder Decoder Values Elements b Decoder

Values

Clk CIk

In the late 196Os/early 197Os, research workers in universities and industry were trying to extend algorithmic test-pattern generation techniques into the sequential domain. The algorithms, based on the concepts of path sensitisation and expressed formally through the mathematics of Jean-Paul Roth (thecalculus ofD-cubes [3]), were seen to be applicable to combinational circuits - that is, logic circuits containing no memory elements and no closed loop feedback paths. The extension into the sequential domain was proving difficult. A sequential circuit, by definition, contains memory elements. Typical elements include D-type and JK-type flip flops. The sequential circuit may also contain closed loop feedback paths. Figure 6 shows models for various forms of sequential circuits. Note that Figures 6(c) and 6(d) contain a closed feedback path.

The attempts to extend the application of the D-cube calculus and underlying sensitive-path concepts into the region of complex sequential circuits failed. Even now (1993), the problem is still notoriously difficult. Because of this failure, several companies (but particularly IBM [3]) looked at alternative solutions. They applied the “divide and conquer” principle to the problem. The basic problem was “how to design a complex sequential circuit so as to be able to generate high-quality tests given that the researchers are unable to develop commercial tools for the job?” The solution was to ask what problems could the researchers solve - the answer was combinational algorithmic pattern generation. And so the scan solution was proposed: build a shift-register (scan path) feature into the circuit such that the closed loop feedback path could be broken and the path used to reach the combinational sections of the circuit - see Figure 7. The test strategy was then broken down into two sections: first test the scan path, and then use the scan path to test the combinational parts.

Synchronous Sequential Circuits Styles

Present-Slate Values Present-State Values

(a) Simple sequential circuit structure (b) Simple sequential circuit structure

Elements Decoder Elements Decoder

Present-Slate Values Present-State Values

PO +

(c) Complex sequential circuit structure (Mealy) (d) Complex sequential circuit structure (Moore)

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The Scan Path

Scan Enable Serial Shift-In 1 (Scan-ln)

Serial Shift-Out (Scan-Out)

I [[ Figure 7

3. What is “partial” scan?

There are several definitions of partial scan. The first problem is to agree a common definition. In terms of the current market offerings, here is an explanation of what is a partial scan path.

The original papers on scan [2, Chap. 31 advocated for &l state-variable memory elements in a sequential circuit to be linked into a serial-in, serial-out shift register. If this is the case, we now refer to this path as a full scan path. At the time when full scan emerged, the motivation was to reduce the complexity of the sequential circuit in order to solve the automatic/algorithmic test-pattern generation problem. The motivation now is to produce high-quality tests in order to reduce the number of test escapes (the zero escape driver) and to providea means of locating the defect unambiguously and accurately (the zero defect driver).

There was always the battle of “overhead” however. It is still a common perception that scan, or any design-for-test change to a circuit, causes additional circuitry or pins, or

both - the “overhead”. There is a philosophical question here which is explored in [ 13. We will not go into in much detail, but the question we would always ask is “if you consider testability to be part of the design requirement, then why do you consider its implementation to be an overhead? ”

However, let us accept for now that it will be some time before designers start associating testability more with the benefits and less with the cost. Therefore, there are still market forces on Design-for-Test (Df”) techniques to reduce overhead. This is the current justification for partial scan. Designers found that it was not necessary to connect all memory elements into a scan path. Some of the elements could be left out of the path without too much impact on the final fault coverage of the patterns. In other words, it was a trade-off between 100% fault coverage and real-estate overhead, impact on performance, and extra pinning.

But the testing strategy changes: first runa patterngenerator for sequential circuits (some commercial sequential pattern generators exist), and then determine the fault coverage

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achieved by these patterns. The sequential pattem generator is not guaranteed to produce patterns for all faults (not unless it is allowed to run endlessly with infinite computing power!), and the partial scan path is built to allow the uncovered faults to be detected with further tests applied through the path.

There are various differences in the detail of this general strategy, but the commercial techniques all come up with suggestions for connecting a subset of the memory elements into a partial scan path. Techniques that are used include:

the use of controllabilitylobservability measures to identify memory elements with low input controllability or low output observability;

methods for ranking memory elements in terms of their frequency of use either as a source of stimulus or as a termination for sensitive paths through the combinational sections of the circuit;

identification of a minimal set of memory elements to break all closed path cycles in the circuit (which is arguably a full-scan path anyway);

linking only those memory elements that do not lie on a critical timing path (of which we will say more later).

So now we can look at the arguments for and against partial scan. These arguments are positioned against the arguments forandagainst full scanaspresentedin[l]. Forcompleteness, the arguments for full scan are repeated here.

4. Arguments for and against full scan

The arguments for full scan are:

Guaranteed automated and algorithmic tree-search test- pattern generation for the combinational sections of the circuit. Automated means “push-button”, algorithmic tree- search means “if there is a test for the fault, the software will find it”. Popular pattem-generation algorithms for combinational circuits include Podem [2, Chap. 41 and Fan, (an extension of Podem). Current commercial offerings are largely based on these algorithms.

Lower fault-simulation costs (because the fault simulator is needed only for the combinational sections of the circuit). The final fault coverage should be 100% of all detectable faults targeted by the pattem generator e.g 100% of all single stuck-at-1, stuck-at-0 faults plus any other faults targeted by the generator. This has a major benefit in the

implementation of a zero escape quality requirement which requires fundamentally “excellent fault detection”.

Better design debug capabilities by using the scan paths to explore the behaviour of the intended circuit (a strong message from the design and test team of the HP/Apollo DNlOOOO workstation [5] ) . There is also an emerging force to make use of scan paths at board and system level for production test and servicing, e.g. the new IEEE Computer Society Systems Test and Diagnosis Working Group [6] .

A manageable design environment because of theexistence of design tools and rule checkers. There is also a strong belief that scan enforces well-behaved clock schemes. Such schemes can reduce timing problems in the final design: LSSD [4] was particularly set up with well-defined clock schemes for this very reason. The final benefit of a controlled design environment is lower risk of a major design change (= quicker time to market).

Better able to locate the cause of a defect because of the partitioning through the scan path. The benefit here is in implementing the zero defect quality requirements (which require fundamentally to locate a defect before such a defect can be fixed or corrected).

The bottom line of these benefits is quicker time to market plus a way of servicing the twin quality drivers of zero escape and zero defect.

The arguments against full scan are:

”Scan introduces extra silicon and pins. The more there is, the more can go wrong, down goes the yield, up goes the cost. Forget it !!”

This is the classic “overhead” argument. There is a response to this observation based on exploring the accuracy of yield measurements coming from observed pasdfail rates at the tester (see Fig. 2). Basically, the argument is that although scan may impact the actual yield, the risk of a test escape is reduced. Therefore, the accuracy of the observed yield increases and, ultimately, this is probably more important than impact on yield.

Scan requires at least one extra pin (the Scan-Enable). Pins cost money, especially if the need for scan causes an increase in package size. True!

Scan memory elements are usually enhanced versions of regular memory elements. The enhancement is normally to add a multiplexer function to the front end of the memory element. This extra functionality can be seen to increase

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propagation delays - hence the potential impact on performance.

True, if done by enhancing the memory elements, but it is not always necessary to modify the memory element. The multiplexing function can be built into the combinational next-state decoder in a well-defined finite-state machine - see the example in [l]. Alternatively, and preferably, the design library is enhanced to contain dedicated scan cells.

You will sometimes hear people say that scan testing takes a long time because of the serial load/serial unload nature of each test. One reaction to this statement is: “Compared to what? How else will you achieve these levels of quality assurance if you do not make use of a scan design technique?” The answer to this question often leads to an interesting discussion as to the true objective of a particular set of tests; structural, functional parametric, or application? Scan tests are targeted on structural test objectives; not the other two possible objectives. We will return to this topic later in the paper.

You will also hear the complaint that scan inhibits the freedom of the designer and therefore he/she cannot produce the optimisedversion of the design. True, but what is meant by “optimised”?

5. Arguments for and against partial scan compared to full scan

Consider first the impact on the benefits of full scan. We will discuss them in the same order as they were presented above.

Partial scan reduces the benefit of guaranteed automatic and algorithmic test-pattern generation. You now need a pattern-generator for complex sequential circuits which is both expensive to buy and to run. You also need a way of selecting the memory elements for connection into the partial scan path. This problem is not trivial!

Fault simulation costs will increase. You now need to run a fault simulator on the full sequential circuit. This requires a more sophisticated fault simulator and will cost more in run time.

The ability to use the scan path for design debug, production test, and field servicing is reduced. There is not so much scan path access and therefore lower controllability and observability inside the circuit.

The design environment is not so manageable. Designers have more freedom (to re-introduce timing problems).

Reducing the partitioning will reduce the ability to locate faults in order to fix products or processes.

The bottom line here is an overall reduction in the ability to implement the requirements of the zero escapehro defect quality drivers.

Now consider the impact on the penalties of full scan.

Currently, the most powerful argument for partial scan is potential reduction in silicon real estate compared to full scan. We are not convinced that this is really a strong argument. Most of the cost of a volume-production device is in the cost of the packaging rather than the cost of the silicon itself. The potential saving therefore can be quite small unless the reduction in silicon causes a reduction in the size of package. The designer still needs to provide a pin for Scan-Enable at least.

In any case, the question of accuracy of measured yield retums. Reducing the fault detection increases the possibility of escapes, thereby reducing the accuracy of the yield measurement .

There may be some improvement in design performance, but we would suggest that it is difficult to generalise this statement. Any improvement in performance must betaken on a case by case basis.

One thing is true however. Full scan can seriously interfere with critical timing paths through the circuit. Partial scan can be based on excluding the critical elements from the partial scan path thus restoring the cleanliness of the timing behaviour. We would see this as probably the most powerful argument in support of partial scan over full scan (but most of the published techniques do not acknowledge this argument and, as a consequence, are not able to accommodate the requirement).

The reduction in the time it takes to apply the scan-path tests (because of shorter scan paths) is surely offset by the increased time it takes to apply the front-end sequential tests.

Partial scan restores some of the traditional freedom of the designer. True, but is this a good thing?

One final point: when a partial-scan macro is embedded in a larger design, it becomes extremely difficult to test the

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macro from the device pins. There are severe requirements on access, timing, and the allocation of other test structures for the passage of test data. These requirements can very quickly result in the need for a powerful (and expensive) sequential pattern generator. One solution to this problem is the macro test approach to the design of testable devices [7]. Such solutions are in line with current thinking on integrated design and test and with hierarchical design strategies. We would claim that partial scan is not supportive of such strategies.

6. An alternative view of partial scan

There is an alternative view on partial scan, which is based on the statement that “quality requirements are not the major drivers in the design and test processes”. The arguments in [ 11 and in this paper are based on a belief that the twin requirements of zero escape and zero defect are fundamental to the product requirements. If this is not so, then thewhole argument for scan in any form (full or partial) collapses. Indeed, it can be argued that there is no need for any special design style to accommodate the test requirement: why not just apply a functional or application-mode test? This is the basis for the discussion in reference [ 81 - the paper with the intriguing title of “The effect of different test sets on quality level predictions: when is 80% better than 90 %? ” . The 80 % ” fault-coverage tests come from a set of test patterns aimed at proving the functional or application modes of behaviour, whereas the “90 % ” fault-coverage tests come froma set of tests aimed at proving the correctness of build i.e a structural set of tests. Primarily, scan design supports structural test, not functional or application test. The “80%” figure is the fault coverage of the functional tests as determined by a fault simulator. The argument in [8] essentially says that this 80% is probably more critical than the 90% coming from the structural tests. This is because the 80% faults are faults which will directly affect the ability of theunit to carry out its design function whereas the 90% is simply 90% of a range of fault-effect models, some of which may not be relevant to the real defects in the circuit or may not cause the circuit to misbehave.

This is adangerous argument! It assumes that the functional tests are, in some way, complete and that the 80% faults represent &l faults which would cause a modification to the functional behaviour. That is, there is some belief that if the circuit passes all the functional tests, then it has been shown toconform toboththe functional and thebuild specifications. The difficulty is to prove the completeness assumption. Also, even if completeness can be proved it is often the case that there is not enough test-application time to apply all the functional patterns. So, be careful of this argument but, if

you believe it, then there is really no reason to add a partial scan path to increase fault coverage. The extra faults covered are not important since they did not prevent the circuit from carrying out its specified behaviour!

7. Conclusion

On balance, we feel that the arguments for partial scan are out-weighed by the arguments against. If “no impact on critical timing” is the premium design requirement, then it would Seem that partial scan has a role to play. Indeed, we would say that this is probably the most important reason to select a partial scan solution over a full scan solution. But, it does so at the expense of other design requirements such as quality of test and therefore quality of product. For certain lower-level ASICs such as gate arrays, partial scan may appear more attractive than full scan. More gates become available for implementing the design function and the operating speed of the circuit might increase. But, for more complex designs orientated around combinations of different styles of design macros e.g macro test, partial scan adds no value, and indeed becomes incompatible with the design style.

To summarise, we would argue that partial scan has little to offer compared to the two altematives: no scan or full scan. No scan has its attractions (optimised timing performance, minimum real estate, minimum pinning, minimum package size, reduced cost of design and test tools, reduced current consumption). Full scan also has its attractions (high quality of test, controlled design environment, potential debug applications “beyond the chip”, automated test- pattem generation). For partial scan to replace full scan, it should combine the advantages of both no scan and full scan. It seems to us at least that with the one exception of critical timing, this is not the case.

References

[l] R. G. Bennetts, “Scan Design: Fact and Fiction”, Keynote Presentation, Test ’92 Conference Proceedings, October 20, 1992, Brighton (UK). (Available from Angel Publishing Ltd., Kingsland House, 361-373 City Road, London, UK, or from the author)

[2] R. G. Bennetts, “Design ofTestable LogicCircuits”, Addison- Wesley, 1984

[3] J . P. Roth, “Diagnosis of Automata Failure: a Calculus and a Method”, IBM Journal, Vol. 10, No. 7, July 1966, pp 278-291.

[4] E. B. Eichelberger, E. Lindbloom, J. A. Waicukauski, T. W. Williams, “Structured Logic Testing”, Prentice Hall, 1991

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[SI B. I. Dervisoglu, “Using Scan Technology for Debug and Diagnostics in a Workstation Environment”, Proc. IEEE International Test Conference, 1988, Paper 45.2, pp. 976-986

[6] IEEE Computer Society Working Group “Systems Test and Diagnosis”, for details contact Colin Maunder on Tel: +44 (0)473 642706, Fax: +44 (0)473 642157

[7l F. Beenker et al., “Macro Testability: the Results of Production Device Applications”, Proc. IEEE International Test Conference, 1992, Paper 9.1

[8] P. C. Maxwell et al., “The effect of differenttest sets on quality levelpredictions: when is 80% betterthan 90%?”, Proc. IEEE Int. Test Conference, 1991, Paper 13.3, pp 358-364

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