A Solid State Variable Capacitor with Minimum DC Capacitance

Sisheng Liang, Xi Lu, Runruo Chen ,Yang Liu, Shao Zhang, and Fang Z. Peng, IEEE Fellow Department of Electrical and Computer Engineering

Michigan State University East Lansing, MI 48824 USA

liangsis@msu.edu, fzpeng@egr.msu.edu

Abstract—A new solid state variable capacitor (SSVC) with minimum dc capacitance is proposed. A variable ac capacitor (with capacitance variable from 0 to Cac) is traditionally implemented by an H-bridge inverter and a large electrolytic dc capacitor with capacitance of 20 times the ac capacitance value, Cac to absorb the 2ω dc ripple. The proposed SSVC consists of an H-bridge and an additional phase leg connected to an ac capacitor with fixed capacitance, Cac and can reduce the dc capacitance to the minimum just for absorbing switching ripples. The fixed ac capacitor controlled by the additional phase leg absorbs the 2ω component and theoretically can eliminate 2ω ripples to the dc capacitor completely. Therefore, no electrolytic capacitors would be needed. Theoretical analysis of the SSVC is provided. Simulation and experimental results are shown to prove the effectiveness of the proposed SSVC with minimum dc capacitance.

I. INTRODUCTION The concept of flexible AC transmission systems (FACTS)

has been widely accepted as a breakthrough for modernizing today’s power grids. This is because FACTS devices can enhance the network stability, reliability and controllability [1], which in turn, improve grid transmission capability and power quality. Essentially, all FACTS devices, such as series compensator, shunt compensator and unified power flow controller could be theoretically represented by “ideal” variable capacitors. Fig. 1 shows an ideal variable capacitor, of which the capacitance can vary continuously from zero to a fixed value, Cac. However, variable capacitors are not available for power grid applications, which usually require MVA ratings.

0 ~ acCsv

si

Fig. 1 An ideal variable capacitor

A variable capacitor can be implemented by an H-bridge inverter as shown in Fig. 2. By controlling the angle between the input voltage, Vs, and the input current, Is, the inverter acts as a pure capacitor. Meanwhile, by controlling the amplitude of Is, the inverter can achieve continuous variable capacitance. As a result, the inverter can be taken as a variable capacitor. A constant voltage across the dc capacitor Cdc is needed to operate the H-bridge inverter as a variable capacitor. The dc capacitor has to absorb the ripple power pulsating at twice the line frequency (2ω ripple power) and the required dc capacitance can be calculated by

s s

dc dc

V ICV Vω

=Δ

(1)

For the variable ac capacitor, the capacitance is expressed as

sac

s

ICV ω

= (2)

where ω is line frequency, VsIs is the rated power , Vdc is the mean voltage across the capacitor, ΔVdc is the allowed peak-to-peak voltage ripple. For example, in order to absorb the 2ω ripple power from mimicking a variable capacitor with capacitance (0 ~ Cac), a bulky and expensive dc capacitor (normally electrolytic capacitors are used) with 20 times the ac capacitance Cac is needed to make ΔVdc within 5% Vdc when the maximum modulation index 1 is used. That is, Cdc is 20 times of Cac, which makes low power density for FACTS devices.

Fig. 2 A variable capacitor/inductor implemented by an H-bridge inverter

Many researches have already been done to reduce the 2ω

978-1-4799-2325-0/14/$31.00 ©2014 IEEE 3496

ripple power for single-phase inverters and rectifiers by adding auxiliary circuits to the system [4]-[11]. However, none has dealt with capacitance reduction of SSVC. In this paper, we focus on SSVC and propose a new inverter circuit and active power decoupling control strategy to implement SSVC without requiring a bulky bank of electrolytic dc capacitors. As a result, only a smaller film capacitor is needed to smooth the switching ripple. Therefore, longer lifetime, higher reliability and higher power density can be achieved. Theoretical analysis of the proposed SSVC from energy point of view is conducted. The capacitance requirement is theoretically formulated. Simulation and experimental results are provided to prove the effectiveness of the proposed SSVC with minimum dc capacitance.

II. SSVC CIRCUIT CONFIGURATION AND THEORY TO ELIMINATE 2ω COMPONENT

A. Proposed circuit configuration Fig. 3 shows the proposed SSVC circuit configuration. In

this proposed SSVC, a fixed ac capacitor controlled by the additional phase leg is used to absorb the 2ω component and theoretically can eliminate 2ω ripples to the dc capacitor completely. As a result, only a small capacitor is needed on the dc side to absorb switching ripples. The ac capacitor (with a rated voltage of VS) is fully utilized to store 2ω ripple energy since it can be fully charged all the way to its rated voltage (+VS) and discharged fully to its minus rated voltage (−VS). Therefore, the proposed SSVC only requires a minimum dc capacitor and a minimum ac capacitor to implement its function.

Fig. 3. Proposed SSVC configuration

B. Theory of eliminating 2ω power to the dc bus The proposed SSVC in Fig. 3 can be considered as a three-

phase unbalanced system. Taken the line voltage vab, vcb as ideal voltage source, the equivalent circuit of the proposed SSVC is shown in Fig. 4. The instantaneous power balance theory is used here to analyze the elimination of 2ω components to the dc bus.

abv

cbv

cL

csv

si

bi

ci

cL

sv

Fig. 4. The equivalent circuit of the proposed SSVC

From Fig.4, the relationship between the grid voltage Vs and current Is can be expressed as

( )

2 sin;

22 sins s

s s

v V t

i I t

ω πϕω ϕ

⎧ =⎪ = −⎨= +⎪⎩

, (3)

where ϕ is the phase angle between Vs and Is, ω is the grid frequency. The total ripple power pab absorbed by the inverter is then represented by

2

( )

sin(2 2 ) cos(2 )

sab ab s s s c s

c s s s

dip v i v i L idt

L I t V I tω ω ϕ ω ϕ

= − = − +

= − + + +. (4)

The voltage and current of the ac capacitor are defined as

2 sin( )

2 cos( ) 2 cos( )cs cs

c c ac cs

v V t

i I t C V t

ω θ

ω θ ω ω θ

⎧ = +⎪⎨

= + = +⎪⎩, (5)

where θ is the phase angle between Vcs and Vs. The total ripple power absorbed by the ac capacitor Cac and the smoothing inductor Lc is then given by

21( ) sin(2 2 )cc c c cs c c c

cs

dip L i v i L I tdt C

ω ω θω

= + = − + . (6)

To minimize the dc capacitance, it is necessary to guarantee no 2ω components assimilated by the dc capacitor. Instead, all 2ω components will flow into the ac capacitor Cac. In other words, the ac ripple power pab needs to be equal to that of the ac capacitor as

ab cp p= . (7) Theoretically, the 2ω ripple current can be eliminated

completely if (7) is achieved. To satisfy the ripple power balance shown in (7), two requirements should be met. (1). Vs and Vcs are in phase, which is

0θ = . (8) (2). The capacitor voltage Vcs and current Ic is

2

2

3 2

1/s s c s

ccs c

c s s c scs

cs cs c cs

V I L IIC L

I V I L IVC C L C

ωω ω

ωω ω ω

⎧ +⎪ =−⎪⎪

⎨⎪ += =⎪

−⎪⎩

. (9)

Is

v s

L c

Lc

C ac

S 1

S 2

S 3 S 5

S 4 S 6

V dc

ic vcs

i b C dc

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Since the inductor Lc absorbs high frequency switching ripple, the influence of the inductor to 2ω ripple power is small and can be neglected in the following analysis. Then Ic is simplified to

1/s s

ccs

V IICω

= . (10)

The ac capacitance for the proposed SSVC, Ccs can be simplified as

2c

css s

ICV I ω

= . (11)

From (1) and (11), if dc voltage ripple ΔVdc is 5% and the maximum modulation index 1 is used, then the relationship of capacitance requirement between the new SSVC and conventional H-bridge inverter is expressed as

2

2

2120

c

cs s s cs s s

dc dc

IC V I I

I VC IV V

ω

ω

= =

Δ

. (12)

It can be found from (12) that the ac capacitance can be reduced by 20 times comparing with the dc capacitance of the conventional H-bridge based SSVC if Ic is controlled to be Is. In the proposed SSVC, the dc capacitor in the dc bus is only required to smooth the switching ripple. As discussed before, the dc capacitor only smooth the switching ripple and can be neglected. Therefore, a minimum dc capacitor and a minimum ac capacitor of the proposed SSVC can be achieved.

III. OPERATION AND CONTROL OF THE PROPOSED SSVC

The above analysis shows 2ω ripple power can be eliminated from the dc bus if properly controlled. To achieve this total elimination, the operation of the proposed SSVC should satisfy

cs s

c s

V VI I

=⎧⎨ = −⎩

. (13)

The detailed analysis of operation and control of the proposed SSVC is as follows.

A. Operation of the proposed SSVC

sI

sV

abVc sj L Iω

cI

sIcsV

cbV

cI

c cj L Iω

(a) (b)

Fig. 5. Phasor diagram of the proposed SSVC

Fig.5 shows the phasor diagram of the proposed SSVC. With KCL, the current equation can be expressed as

( )b s cI I I= − + . (14)

From (13), Ib can be controlled as zero. None of the three-phase currents are bigger than the output current in the conventional H-bridge inverter. Therefore, the current stress of the proposed SSVC is the same as conventional H-bridge inverter.

On the other hand, the voltage equations can be expressed with the KVL as

s c s ab

cs c c cb

V j L I VV j L I V

ωω

+ =⎧⎨ + =⎩

. (15)

(15) shows that Vab is the same as Vs and Vcb is equal to Vcs if voltage drops on inductors are neglected. From (13) and (15) the line voltage Vab and Vcb should be the same, which is

ab cbV V= . (16)

From (16), the line voltage of the proposed SSVC is the same as conventional H-bridge inverter. Therefore, the dc-bus voltage should be the same as conventional H-bridge inverter, which means the voltage stress of the proposed SSVC is the same as that in the conventional H-bridge inverter.

To sum up, the ac capacitor Cac can absorb 2ω ripple power without increasing current stress or voltage stress.

B. SSVC control

*dcV

dcVsV

sI*

cbv *cv

*bv

*av

sV

*sI

sin( 90 )tω + °

cI *csV

*csV

csV

*csVΔ

Fig. 6. System control block of the proposed SSVC

Fig. 6 shows the overall control diagram of the proposed SSVC which consists of three controllers, the dc voltage controller, the grid current controller and the power decoupling controller. The dc voltage controller is to maintain the dc-bus voltage Vdc. The current controller is to realize reactive power control. The power decoupling controller is to control the ac capacitor voltage Vcs and current Ic.

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1

csL R+

svsi

*si si

*abv abv

sv

Fig. 7. Current control diagram

Fig.7 shows the grid current control diagram. To track the reference current precisely, the system must have enough open-loop gain at grid frequency ω, which cannot be achieved by a proportional integral (PI) control. Hence, a proportional resonant (PR) controller is used. A grid voltage feed forward is also used to overcome the disturbance of the grid voltage.

1

csL R+

*cI

csV

*csV cI 1

cssCcsV

csV

cbV*cbV

cI *csV

Fig. 8. Power decoupling control diagram

The power decoupling controller shown in Fig.8 aims to achieve a total elimination of the 2ω ripple components. It consists of an inner-loop current controller and an outer-loop voltage controller which can eliminate the resonance between Lc and Cac. The voltage reference can be calculated by (9) and (10).

* 0ripi =

csVΔ

ripi

Fig. 9. Reference modification control

A modification of the ac capacitor voltage reference is shown in Fig. 9, which is indispensable because of parameter deviation and limitations of the power decoupling control. The ripple is feedback and a proportional controller is used to modify the reference voltage.

Finally, the reference voltages for phase a and phase b are expressed as

* * *12a b abv v v= − = . (17)

The reference for phase c is expressed as * * *

c b cbv v v= + . (18)

IV. SIMULATION AND EXPERIMENT RESULTS Simulations have been performed to confirm the above

analysis related to SSVC operation and control. Furthermore, a 10-kVA SSVC prototype is built and experimental results are also provided.

A. Circuit Parameters Table I shows the main parameters of the proposed SSVC.

TABLE I PARAMETERS OF THE SSVC

Symbol Items Value

fs Switching frequency 20 KHz f Fundamental frequency 60 Hz

Cac ac capacitor 300 μF Cdc Cdc

dc capacitor dc capacitor for H-bridge

25 μF 3 mF

Lc Smoothing inductor 0.7 mH Vdc dc bus voltage 440 VVs Is

Grid voltage RMS value Output current RMS value

300 V 33.3 A

The ac capacitance Ccs is 294 uF, which can be calculated from (11). The two inductors are designed according to

2dc

ppc s

VIL f

Δ = , (17)

where ΔIpp is peak-to-peak current ripple and taken as 20% of the fundamental current here. If the inductor is too small, the current ripple brought by switching frequency is big, which will increase current stress. However, if too large inductance is applied, the inductor will consume an amount of the reactive power in the capacitor [11]. That means the large inductance will increase the minimum ac capacitance. The oscillation between the inductor and the capacitor would be appeared.

B. Simulation results

Fig. 9. Simulation results

Fig. 9 shows the simulation results of the proposed SSVC.

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Ism is the current injected into grid which is lagging 90o to the grid voltage Vs. The dc bus ripple is 3.6%. Is and Ic are almost equal and the phase is in opposite direction. The small difference between Is and Ic is caused by two smooth inductors. This also explains the difference between Vc and Vs. The 2ω ripple voltage is not pure sinusoidal because of nonlinear of the control system. The dc capacitance is 25 uF in the proposed SSVC which can be neglected comparing to conventional H-bridge inverter.

To sum up, Vc and Ic are controlled to satisfy (13). Then the 2ω ripple can be absorbed by the ac capacitor. Therefore the dc capacitance is reduced to almost zero which can prove the effectiveness of the ripple energy decoupling control method.

C. Experiments results The parameters of the test setup are shown in table II.

TABLE II EXPERIMENT PARAMETERS AND DATA

Symbol Items Value

fs Switching frequency 10 KHz f Fundamental frequency 60 Hz

Cac ac capacitor 300 μF Cdc dc capacitor 100 μF Lc Smoothing inductor 1.5 mH

Vdc dc bus voltage 100 VVs Is Vc Ic

Grid voltage RMS value Grid current RMS value

Capacitor voltage RMS value Capacitor current RMS value

56.57 V 6.54765 A 60.81 V

6.87789V

Fig. 10. SSVC Current and Voltage

As can be seen from Fig. 10, Is flows into the SSVC, so Is is 90 degree leading the grid voltage Vs. The calculated Ic according to (10) is 6.91A which is approximately the same as the measured value 6.8779A. The reactive power injected into the grid is 370.4 Var whereas the reactive power on ac capacitor is 418 Var. The difference is due to the consumption of the two inductors.

Fig. 11. Grid current/voltage and dc-bus voltage

Some more conclusions can be drawn from Fig. 11. The dc bus ripple is within 5% Vdc. The dc capacitance is far less than conventional H-bridge variable capacitor.

V. CONCLUSION A new SSVC with minimum dc-bus capacitance was

proposed. Theoretically, 2ω ripple current to the dc bus can be entirely eliminated. Thus, the capacitance reduction is nearly 20 times comparing to the conventional H-bridge inverter. Therefore, only a small capacitor is needed on the dc side to absorb switching ripples and no electrolytic capacitor is needed. Thus, the system reliability is improved. Furthermore, the ac capacitor can absorb all the 2ω ripple power without increasing the current and voltage stress.

Simulation results show that dc capacitance can be decreased to 25 uF (almost negligible) for the 10kVA SSVC within 5% dc ripple while the dc capacitance is 3 mF in a conventional H-bridge inverter. Experimental results also showed that dc capacitance could be reduced to 100 uF and more results will be provided in the future.

It should be noted again that the proposed SSVC can be applied to FACTS devices without using a bulk of electrolytic capacitors, which will have a longer lifetime, higher power density and system reliability.

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