High Performance Wafer Level Underfill Material with High Filler Loading

Satoru Katsurayama* and Hiroshi Suzuki Sumitomo Bakelite Co., Ltd

20-7, Kiyohara Industrial Park, Utsunomiya, Tochigi, Japan * e-mail: katuras@sumibe.co.jp, Phone: +81-28-667-7669

Jae-Woong Nah, Michael Gaynes, and Claudius Feger IBM T. J. Watson Research Center

1101 Kitchawan Road, Route 134, Yorktown heights, NY

Abstract A new wafer level underfill material with filler content of

60 weight % was developed for high performance flip chip applications with lead free solder bumps. Systematic optimization of the viscosity behavior led to good spin coat ability even for the material with high filler loading. The material can be applied onto the bumped wafer with high uniformity up to a thickness of 100 m by spin coating. The thickness variation was less than 5%. Additionally, void reduction in the package was realized by optimizing the curing process. By controlling the viscosity during the post-curing step voids in the package can be eliminated. Finally, the package with the new wafer level underfill material exhibited good reliability including during thermal cycling.

1. Introduction There is renewed interest in using pre-applied underfills

such as no-flow underfill (NUF) and wafer-level underfill (WLUF) for the next generation flip chip (F/C) applications [1]-[7]. Pre-applied underfill offers advantages in fine pitch, flip chip assembly from the viewpoint of eliminating flux residues, cleaning and minimizing stress on the back-end-of-line chip structure during solder joining [8]-[10]. In particular, WLUF creates significant savings in time and cost because the application cycle time for a wafer is equivalent to a single chip dispensing operation. The WLUF material is involved in every step of F/C assembly processing such as wafer coating, wafer dicing, and chip attach as shown in Figure 1. To optimize the material requires understanding and control of the assembly process. During the spin coating process, it is important to maintain uniform filler distribution both throughout the thickness as well as from the center of the wafer to the circumference. If the thickness variation across the wafer is too large, the bonding conditions are vary with the location of the chip on the wafer. The dicing process must result in a clean cut edge without cracks or scalloped edges. During the bonding process, the WLUF material must flow and not be trapped between chip bump and substrate pad. Because of these processes challenges, material modifications are required. Initially, no-filler WLUF was studied because filler presents difficult challenges for spin coating, dicing and especially the bonding process. However, fillers are used in underfill materials to decrease the coefficient of thermal expansion (CTE) which has the effect of reducing package stresses, and helping to achieve better reliability performance.

Figure 1: Typical process flow of WLUF application.

In this paper, a new WLUF material with filler content of

60% by weight is presented for high performance flip chip applications with Pb-free solder bumps. In this case we define high performance as capable of achieving good coat-ability, B-stage ability, assembly performance and high reliability. Viscosity optimization led to good spin coat ability even if the material has high filler loading. The WLUF material can be applied onto a bumped wafer with high uniformity up to a thickness of 100 m by spin coat processing. The thickness deviation is less than 5%. Additionally, void reduction in the package is realized by optimizing the cure process. By controlling the viscosity behavior, the material could be worked to eliminate void in the package due to the flow-ability during post curing. Electrical connectivity for Pb free bumps was 100% by using a thermal-compression bonding method. Finally, the package with the new WLUF material exhibited good reliability in thermal cycle testing. By controlling the cure reactivity, the new WLUF material has a shelf life of over four months after B-staging even at a storage temperature of 25oC. This new material formulation enables a wider process window for pre-applied WLUF applications.

2. Experimental procedures

Preparation of WLUF material Two WLUF materials, W1 and W2, were prepared for

this study. Table I shows the differences between the two materials. Both are epoxy-based materials which include 60% filler after solvent removal and have almost the same formulation, however, the main differences are viscosity and cure behavior. Adjustment of the viscosity behavior was arranged by a new additive, which is called CA2 in W2.

978-1-61284-498-5/11/$26.00 ©2011 IEEE 370 2011 Electronic Components and Technology Conference

Unlike the control mixing method of W1, W2 was mixed by using a pre-mixing method of several components so that CA2 can effectively affect the viscosity of the material.

Material properties The viscosity of the WLUF materials were measured with

a BF-type viscometer (Brookfield Engineering Laboratories, HBDV-II+CP). The viscosity values at rotations of 0.5, 2.5 and 5.0 rpm, were measured at 25oC. The viscosity ratio at 0.5 and 2.5 rpm was calculated as a thixotropic index, since coating performance of the WLUF material is thought to depend on the rheologic properties [11]. The glass transition temperature (Tg) and the elastic modulus (E) of the cured WLUF materials were measured by thermo-mechanical analysis (TMA, SII, SS6100, 10oC/min, compression mode) and dynamic mechanical analysis (DMA, Perkin Elmer, DMA-7e, 5oC/min, 10 Hz, 3 point bending mode), respectively.

Spin coating test The coating performance of the WLUF materials was

evaluated by applying them onto a 6 inch wafer using a spin coater (Mikasa, 1H-DX). W1 was coated at 500 rpm / 10 s + 800 rpm / 10 s, and W2 was coated at 500 rpm / 10 s + 1000 rpm / 20 s to achieve a material thickness of around 100 m. After coating,, the WLUF films were heated in an oven (Toyo Seisaku-syo, DFB-60HS) at 90oC for 90 minutes to B-stage cure. In order to measure the coating thickness, a part of the material was scratched and the surface of the wafer exposed. As shown in Figure 2(a), the difference between the surface of WLUF coating and the wafer was measured by scanning with a surface roughness meter (Accretech, SURFCOM 1400D). The uniformity of the coated material was examined by the average and standard deviation of 5 measuring points as shown in Figure 2(b). Additionally, the surface roughness after B-staging was measured by the surface roughness meter.

Preparation of F/C package The F/C packages were built with W1 and W2. The chip and substrate were used as shown in Figure 3. Before chip assembly, W1 and W2 were applied on the chip by spin coating and the WLUF materials were heated for B-staging. Then, the chip with the B-staged WLUF material was bonded to the substrate by using a F/C bonder (Toray Engineering, FC3000S). Thermal-compression was applied as the bonding method. Finally, the bonded package was heated at 150oC for 2 hours to post cure. In order to evaluate the assembly performance, inner voids were measured by scanning acoustic tomography (SAT) (Hitachi Kenki Finetech, FineSAT FS300). The connectivity of the solder bumps was observed by cross sectioning.

Reliability test In order to examine the F/C package reliability, deep thermal cycling (DTC) was carried out. In the pre-conditioning step, the packages were treated under the humidity condition of JEDEC (Joint Electron Device Engineering Council) level 3 (at 30oC, 60%RH for 168 hour) and the packages went tomography (SAT) (Hitachi Kenki Finetech, FineSAT FS300). The connectivity of the solder bumps was observed

by cross sectioning. through three reflows with 260oC peak temperature. After this pre-conditioning DTC was performed from -55 to 125oC for 1000 cycles. The packages were monitored for delamination and change of connection resistance caused by the temperature cycling.

Figure 2: Procedure of material thickness measurement, (a) cross sectional view of thickness measurement (b) measuring points on wafer

Figure 3: Dimensions of chip and substrate used in this study.

Table 1: Comparison between W1 and W2.

371

3. Results and discussions

Properties of WLUF material Table 1 shows a comparison of W1 and W2. It shows that

W2 has a lower thixotropic index than W1. Generally, a liquid compound containing a mixture of high-molecular weight compounds such as the WLUF materials is treated as a non-Newtonian fluid [11]. From the viewpoint of wafer level spin coating process, it is very important to balance dilatancy and thixotropy due to the angular speed on the wafer. The authors thought that it was important to have a viscosity behavior independent of angular speed , i.e. lower thixotropy from the viewpoint of thickness uniformity of WLUF material during spin coating and after B-staging. This tends to lead to uniform material flow from the center to the edge of the wafer. This behavior is very important to achieve uniform coating in the plane.

In this study, low thixotropy of W2 was realized by adding CA2. In a complex mixture compounds system, an interaction is ordinarily generated, including van der Waals’ force, electrostatic force and hydrogen bond strength [12]. With the finer particle, smaller molecular compound and higher polar character, larger interaction occurred. It can be thought that in the WLUF material this interaction is generated by the formulation. In order to verify the cause of the decreasing thixotropic index of W2, the surface zeta potential of the blended filler between model material A and model material B were measured as shown in Figure 4. Zeta potential was measured by ELSZ series, Otsuka electronics. Here, the model material was composed of filler and solvent. The model material B was composed of filler, solvent and CA2. The data shows an obvious difference between the zeta potential of model material A and B. This indicates that CA2 effectively reacts with the blended filler, i.e., the surface of the filler is modified by CA2. Thus the lower thixotropy is realized by decreasing the interaction between the organic and inorganic compounds.

Figure 4: Zeta potential between model material W1 and W2.

Figure 5: (a) The thickness and (b) roughness on surface

between W1 and W2 (same location).

Figure 6: (a) Geometry on surface and (b) appearance

between W1 and W2 of 100 microns thickness.

Figure 7: Camera view of surface on coated chip by F/C

bonder between (a) W1 and (b) W1 with CA2. The thickness of WLUF is 20 microns over solder bumps.

372

Spin coat ability Figure 5 shows the thickness and geometry on the surface

of W1 and W2 after B-staging. The data shows that W1 exhibits a higher thickness in the center of the wafer than in the other areas because of the highly thixotropic character and thus worse flow-ability, and thus the WLUF material remained in the center of the wafer, where there is the slowest angular speed. W2 on the other hand shows only a very small thickness variation of less than 5%. Additionally, the appearance changed to a very smooth and mirror-like surface as shown in Figure 6. It is thought that the WLUF material can flow uniformly despite the various angular speeds across the wafer, since the thixotropic character of this WLUF material is very low. This improves the coat-ability significantly and produces uniform thickness of the WLUF material independent of location. It indicates that there is no solvent residue causing thickness deviation. This means that all chips can be processed with the same assembly condition which is significant for productivity. Figure 7 shows how chips coated with W1 and W1 withCA2, respectively, appear in the camera view of the F/C bonder. The thickness of W1 and W2 are the same, that is 20 microns above the solder bumps. The image with W1 containing CA2 was better than that with W1, although the transparency between W1 and W2 showed no difference because both materials use the same filler. It is thought that the diffused reflection is reduced since the roughness of the surface was modified to be smooth.

Package assembly and Reliability test Using W2, bonding and DTC testing were performed to evaluate the assembly performance and reliability of the package. Figure 8 shows a cross-section of the bump connections. In pre-applied underfill processes such as WLUF, voids in the gap between chip and substrate are easily generated by volatiles, since the WLUF material is heated beyond the melting temperature of the Pb-free solder during the flip chip bonding process. Since voids in a package are considered to be a reliability risk in F/C packages, void elimination in the package is required. Figure 9 shows the difference in voids in the package just after bonding and after autoclave curing at high pressure (0.8MPa). Here, bonding was performed at a high temperature in order to generate voids intentionally. And a glass plate was used to see the voids from the substrate side. The results show that autoclave cure leads to significant void reduction in the package, since the volume of the initial voids is decreased under the externally applied pressure. Unless the WLUF material maintains a high flow-ability level after chip bonding at high temperature, void eliminating can not be achieved. In this study, it was demonstrated that voids can be reduced significantly under a pressure of 0.2 MPa during post cure. W2 was modified to achieve a delayed cure performance by controlling the reactivity compared to W1. Figure 10 plots the relationship between viscosity and temperature for a temperature ramp of 15oC / minute in a rheometer (Haake, RS150). Figure 10 shows that W2 has a wider range at low viscosity than W1, that is, it has a higher flow-ability during heating. Therefore, void reduction can be achieved during the

Figure 8: Cross sectional photo after chip assembly with WLUF.

Figure 9: The comparison of voids in package between

(a) normal cure and (b) autoclave cure method after flip chip bonding with WLUF.

Figure 10: Viscosity behaviors between W1 and W2.

Figure 11: Gelation time and reaction ratio against

storage time.

373

pressure cure process. Additionally, the wider low viscosity window facilitates good connectivity because the material can move away from the bumps during joining. This indicates that the process window of the assembly condition is wider, andproductivity improved significantly.

The authors carried out DTC testing to verify the reliability of the package and found that the packages passed pre-conditioning and DTC of 1000 cycles. Detailed information on the flip chip bonding process with the described WLUF material, the post pressurized cure for void reduction, and reliability test results are presented in another paper [13]. W2 has a Tg of 90oC, 1 of 25 ppm, and E of 7 GPa (Table 1). This balance of properties of the WLUF material led to the high reliability performance with this assembly process.

Floor life In wafer level processing, storage stability after coating

significantly affects the productivity. Unlike freezing or cooling storage, ordinary temperature storage has a big advantage for handling. If a coated wafer can be stored at room temperature, control of thawing conditions or handling limitations can be eliminated. For this reason, long floor life is an important factor for wafer level applications. Figure 11 shows the gelation time at 200oC and the reaction ratio against storage time at 25oC after B-staging. The results show that W2 shows long floor life after coating because there is no change during 4 months.

As a result it was possible to develop this high performance WLUF material with good coat-ability, high connectivity and long floor life after B-staging. This means that it has not only high productivity but also high workability. It also indicates that this pre-applied UF process has possibility for wide-ranging application including high density and stacked style assemblies.

Conclusions In the flip chip applications, it is thought that WLUF

material has a big advantage for process and cost reduction. On the other hand, it can be said that it is difficult to control all parameters, since the WLUF process has many process steps.

In this study, a high performance WLUF material was developed. Properties include high spin coat-ability and good connectivity even at 60% filler loading. Reduction of the thixotropic index led to a wafer coating performance with less than 5% thickness variation. Additionally, delayed cure can open the process window and achieve both high connectivity and a “void-less” performance. The developed material passed 1000 DTC cycles demonstrating high reliability performance. Control of the cure behavior led to long floor life at 25oC after B-stage.

Acknowledgments Firstly, the authors would like to express their grateful

thanks to Mr. Yusuke Kizaki and Mr. Bryan Miskin for their support. The authors also would like to express their gratefulness to IBM Research and Sumitomo Bakelite Co. Ltd. for giving them this opportunity and contributions

including equipment and research positions for research data acquisitions.

References 1. Wong, C. P., Shi, S., Jefferson, G. "High Performance No

Flow Underfills for Low-cost Flip-chip Application: Materials Characterization," IEEE Trans of CPMT, Part A, Vol. 21, No. 3, (1998), pp. 450-458.

2. Wong, C. P., Baldwin, D., Vincent, M. B., Fennell, B., Wang, L. J. and Shi, S.H., “Characterization of a No-Flow Underfill Encapsulant Duringthe Solder Reflow Process,” Proc IEEE 48th Electronic Components and Technology Conf, Seattle, WA, May. 1998, pp.1253-1259.

3. Katsurayama, S., and Sakamoto, Y., “High Reliability Non-flow Underfill Material with Filler Laoding,” Proc 27th Annual IEEE/SEMI, IEMT Symp, San Jose, CA, Jul, 2002, pp. 85-87.

4. Katsurayama, S., and Watabe, H., “Development of Assembly Technologyfor High Reliability Flip Chip Pakages Using No-flow UnderfillMaterial,” Proc The Sixth VLSI Packaging Workshop, Kyoto, Japan, Nov., 2002, pp. 117-120.

5. Nguyen, L., Nguyen, H., and Nagasi, A., “Wafer Level Underfill-Processing and Reliability,” Proc 27th Annual IEEE/SEMI, IEMT Symp, San Jose, CA, Jul, 2002, pp. 53-62.

6. Lee, W., H., Wang,Y., P., Hsiao, C., S., Katsurayama,S., Sakamoto, Y., and Yamada, H., “Development of Wafer Level Underfill Processes,” Proc IMAPS 2005-38th Symp. Microelectronics, Philadelphia, PE, Sep, 2005, pp.361-366.

7. Lu, J., Smith, B., and Baldwin, D., E., “Adhesion Characterization of No-Flow Underfills Used in Flip Chip Assemblies and Correlation with Reliability,” IEEE Trans. On Electron, Packag. Manufac., Vol. 24, Iss. 1, 2001, pp. 26-30.

8. Feger, C., LaBianca, N., Gaynes, M., Steen, S., Liu, Z., Peddi R., and Francis, M., “The Over-Bump Applied Resin Wafer-Level Underfill Process: Process, Material and Reliability,” Proc IEEE 59th Electronic Components and Technology Conf, Las Vegas, NV, Jun, 2009, pp.1502-1505.

9. Katsurayama, S., and Tohmyoh, H., “Effect of Warpage of Flip Chip Packages due to the Underfill Encapsulating Processon Interconnect Reliability,” ASME J. Electron. Packag., Vol. 131, Iss. 3, 2009, pp. 031005-1 – 031005-5.

10. Katsurayama, S., Tohmyoh,H., and Saka, M., “High Performance Flip Chip Package with Higher Mountability and Longer Interconnect Life,” ASME InterPACK 2009, DVD-ROM program, San Francisco, CA, Jul, 2009, RELIABILITY(RE), IPACK2009-89148.

11. Onogi, S., Rheology for Chemist, Kagakudojin (Kyoto, 1982), pp. 37-49, in Japanese.

12. Honda, K., et al, Surface and Interface Engineering System, 1st tome, Basic Edition, Fuji Techno-System (Tokyo, 2005), pp. 83-118, in Japanese.

13. Nah, J-W., Gaynes, M., Feger C., Katsurayama, S., and Suzuki, H., “Development of wafer level underfill materials and assembly processes for fine pitch Pb-free solder flip chip packaging”, Proc. IEEE 61st Electronic Components and Technology Conf., session 22, Orlando, FL, June 2011.

374