A Novel Flash Fast-Locking Digital Phase-Locked Loop By

Dr. Mahmoud Fawzy Wagdy, Professor And

Brandon Casey Cabrales Department of Electrical Engineering,

California State University, Long Beach, Long Beach, CA 90840, U.S.A.

ABSTRACT - A FLASH digital phase-locked loop (DPLL) is designed using 0.18�m CMOS process and a 3.3V power supply. It operates in the frequency range 200MHz – 2GHz. The DPLL operation includes two stages: (1) a novel coarse-tuning stage based on a flash algorithm similar to the algorithm employed in flash A/D converters, and (2) a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder, and a decoder which drives a multiple charge pump (CP)/lowpass filter (LPF) combination. Design considerations of the flash DPLL circuit components as well as implementation using Cadence design tools are presented. Spectre simulations demonstrated a significant improvement in the lock time of the flash DPLL as compared to the conventional DPLL. By increasing the number of frequency comparators, the lock time is expected to be always less than 100ns . Key Words: DPLL, lock time, coarse-tuning, fine-tuning, CMOS.

I. INTRODUCTION PLLs are commonplace in applications like cellular phones, wireless transceivers, global positioning systems, clock generators, etc. A major characteristic of the PLL is the lock time; it is the time the PLL takes to adapt and settle after a sudden change of the input signal frequency. Conventional PLLs inherently take long time to lock, which render them unfit for contemporary high-speed high-throughput applications needed for information technology. Fast locking is required for fast frequency hopping among data bursts in high-speed digital communications [1]. PLLs with low-power constraints demand that they be turned off during inactivity, but then require that they lock quickly when turned back on [2]. Fast locking is therefore a necessity for spread-spectrum communications, cellular phones, clock/data recovery circuits, etc.

Although the literature on PLLs contains several thousands of designs and research papers, the literature on fast-locking PLLs is very limited (several tens) due to the more recent great demand. Example research papers include: [3-4]. Examples of U.S. patents include: [5-7]. There are a number of industrial corporations that produce fast-locking PLLs, e.g. Analog Devices Inc. [8], True Circuits Inc. [9], and National Semiconductor Inc. [10]. The above literature reveals that fast-locking DPLLs fall under the following categories: (1) techniques based on a mathematical algorithm to achieve fast convergence, (2) techniques based on nonlinear characteristics of the charge pump to change the convergence rate, (3) techniques based on a feedback mechanism associated with the PD or the charge pump, and (4) techniques based on using current-mode techniques in lieu of voltage-mode techniques.

II. THEORY OF OPERATION The original block diagram of the novel flash fast-locking DPLL is given in [11]. The technique is conceptually similar to the one used in the flash ADC. The circuit quickly and simultaneously compares the input frequency with many equi-spaced fixed reference frequencies covering the entire frequency range of operation. This is done via frequency comparators which compare frequencies in a way analogous to voltage comparators used in flash ADCs. Now, frequency comparison results will be represented by a thermometer code (similar to that of flash ADCs). This hypothesis fills an important gap in the literature since it is the counterpart of the concept given in [5] which achieves fast locking via a S-A (successive-approximation) algorithm similar to the one used in S-A ADCs. A slightly modified block diagram, compared to the one in [11], is given below in Fig. 1. The Flash DPLL operates by monitoring any changes in the input signal frequency (Fin) every, say 20ns, using an array of , say 8, frequency comparators with reference frequencies (Fref), ranging from 250MHz to

2009 Sixth International Conference on Information Technology: New Generations

978-0-7695-3596-8/09 $25.00 © 2009 IEEE

DOI 10.1109/ITNG.2009.298

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2009 Sixth International Conference on Information Technology: New Generations

978-0-7695-3596-8/09 $25.00 © 2009 IEEE

DOI 10.1109/ITNG.2009.298

47

Fig. 1. Block Diagram of the Novel Flash DPLL 2GHz. Once a change in Fin is detected during any 20ns cycle, an additional 20ns cycle is needed to coarsely estimate the new input frequency, since the hop takes place at any time during the first 20ns cycle. Thus 40ns are needed to estimate the new input frequency. The thermometer code, at the output of the frequency comparators, is applied to a priority encoder which outputs a 3-bit binary code to a decoder, which in turn selects 1-out-of-8 charge pumps (CPs)/lowpass filters (LPFs). The output of the selected CP has an initial voltage level which is slightly larger than the required voltage level for each specific frequency. The LPF output voltage is then inputted into the VCO which produces the closest frequency to the new input frequency, with a slight overshoot to speed up the DPLL. This marks the end of the coarse-tuning stage. The selected CP/LPF will stay in use until a new Fin has been detected. The remaining time to lock the DPLL is regarded as the fine-tuning stage, where locking will take place like a conventional DPLL while the frequency comparators, encoder, and decoder are not affecting circuit operation. Since coarse tuning sets the VCO frequency to the closest possible to Fin, the fine-tuning time is thus cut down tremendously, as compared to the conventional DPLL thus resulting in a much faster lock-time.

III. DESIGN OF THE FLASH DPLL The circuit components of the flash DPLL of Fig. 1 are given below: 1. Phase-Frequency Detector (PFD) The block diagram of the PFD is shown in Fig. 2. The outputs UP and DN (Down) depend on the frequency and lead/lag relationship between the input Fref and Fvco (VCO output frequency), as in [12]. It should be noted that Fref of Fig. 2 is the same as Fin of Fig. 1.

Fig. 2. Phase-Frequency Detector (PFD)

2. Voltage-Controlled Oscillator (VCO) A current starved VCO is built, which is basically composed of an odd number of inverter stages [12], as shown in Fig. 3. For proper operation, M4 and M5 have to be in the saturation region [13].

Fig. 3. Current Starved VCO A 5-stage VCO was used as it requires less input voltage than that of a 7-stage or 9-stage VCO. Table 1 shows the required voltages needed to produce a specific frequency. Two inverters were used at the VCO output to give sharp waveform edges. In order to test the VCO, a ramp was used at the input to allow oscillations to begin. The ramp was set up to 1.36 V. Fig. 4 shows the test results, which agree with Table 1.

FREQUENCY VOLTAGE (Vctnl)

250 MHz 865 mV 500 MHz 1.038 V 750 MHz 1.14 V

1 GHz 1.2 V 1.25 GHz 1.25 V 1.5 GHz 1.28 V

1.75 GHz 1.32 V 2 GHz 1.36 V

Table 1. VCO Frequency vs. Voltage (Vctnl)

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Fig. 4. VCO Simulations for Vcrtl = 1.36V, Fvco = 2GHz

3. Multiple Charge Pumps and Lowpass Filters 3.1. Single Charge Pump and Lowpass Filter A single Charge Pump (CP) is shown in Fig. 5. The UP signal from the PFD is fed to PMOS P2 through an inverter, while the DN signal is directly fed to NMOS N1. A precise current mirror is used to remove instability and ripple in the control voltage. The output control voltage Vcntrl will increase/ decrease depending on whether the UP/DN pulse occurs. The CP starting voltage is an important design factor since it helps in decreasing the lock time of the DPLL. This voltage can be controlled by modifying the aspect ratio (W/L) of N1 and P2. The lowpass filter is shown in Fig. 6; it has R0 = 500�, C0 = 100pF and C1 = 10pF. 3.2. Multiple Charge Pumps and Lowpass Filters The Multiple CP design, shown in Fig. 7, is made up of 8 individual CPs; each CP has a different starting control voltage. Only one CP is selected at a time. Table 2 displays the required aspect ratios to produce the starting voltage levels of the CPs. Each CP has its own LPF although all LPFs are identical; this prevents the capacitor from keeping the charge of the previously used CP thus each capacitor starts fresh when a new input frequency is detected.

Fig. 5. Single Charge Pump

Fig. 6. Lowpass Filter (LPF) 3.3. Testing the Multiple CP The Multiple Charge Pump was tested by connecting a vpulse=3.3V, set at any frequency, to the UP input pin, and the DN signal to GND. CP#6 was selected and was verified to have an initial voltage of 1.28V as per Table 1; Vcntrl ramped up because the UP signal is constantly getting pulses while the DN signal stays at 0V. After simulating this set-up for 200ns, the results are shown in Fig. 8.

CHARGE PUMP

Aspect Ratio Voltage (Vctnl) P2 (W/L) N1 (W/L)

1 11� /0.18� 10.5� /0.18� 1.04V 2 11� /0.18� 8.5� /0.18� 1.20V 3 11� /0.18� 8� /0.18� 1.26V 4 11� /0.18� 7.75� /0.18� 1.29V 5 11� /0.18� 7.25� /0.18� 1.35V 6 11� /0.18� 7� /0.18� 1.39V 7 11� /0.18� 6.65� /0.18� 1.44V 8 11� /0.18� 6.25� /0.18� 1.50V

Table 2. Starting CP Voltage Control Output per Aspect Ratio

Fig. 7. Multiple Charge Pump and LPF Schematic

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Fig. 8. Multiple Charge Pump UP Simulation

4. Frequency Comparators The Frequency Comparator is the most essential component of the FLASH DPLL. It is what determines which CP to use. The Frequency Comparator Array is shown in Fig. 9. Depending on the input frequency Fin and the reference frequencies Fref, the output of each individual comparator will be either high “1” or low “0.” The block diagram of Fig. 9 has one input and seven outputs; it also shows that each individual frequency comparator has 3 inputs (Fin, Fref, and Reset). The “Reset” input receives a pulse every 20ns to reset the entire array of frequency comparators so that it can begin a new comparison every 20ns. In this design, a novel frequency comparator [14] was attempted; it uses ring counters to determine whether the input signal is slower or faster than the reference signal. The advantage of this type of

Fig. 9. Block Diagram of the Array of Frequency Comparators

frequency comparators is that it always gives correct comparison results regardless of the phase shift between the input and reference signals. To account for the cases when the comparator cannot decide during the arbitrarily allotted time (say 20ns), we added a Time-Out flag to the output of the frequency comparator. The idea is that “Time-Out =1” means that both Fin and Fref are too close, thus it is a good approximation to assume Fin > Fref for that particular comparator even if this is not true and thus the decision would be “1”; this likely small error during coarse tuning would be accounted for anyhow during the fine-tuning stage of the flash DPLL. The Frequency Comparators block of Fig. 9 is made up of 7 of such a novel comparator, the original circuit of which is given in [14], and the reference frequencies of which are equi-spaced in the frequency range 0-2GHz starting at 500MHz. It is also possible to use 8 frequency comparators, with the lowest Fref set at 250MHz. It should be noted that, during the testing of the block in Fig. 9, output pins were connected to capacitor loads (1fF). 5. Priority Encoder To generate a 3-bit binary code at the output, i.e. b1-b3 (b1 being the LSB) from an input array A1-A7 (A1 being the LSB), the design procedure used is outlined in [15]. The circuit was implemented using AND, OR, and NOT logic. Again, outputs were tested while capacitor loads (1fF) were connected to the output pins. It should be noted that in our present design, using only 7 frequency comparators, when the encoder inputs are all “0” or “1”, this corresponds to (Fin < 500MHz) or (Fin > 2GHz) respectively. 6. Decoder The 3 to 8 decoder selects 1-out-of-8 CPs. When all 3 inputs are “0”, this makes B0=1, and when all inputs are “1”, this makes B7=1. Bits B0-B7 energize CPs # 1-8 respectively. The circuits was implemented using AND, OR, and NOT logic. Again, outputs were tested while capacitor loads (1fF) were connected to the output pins.

IV. IMPLEMENTATION AND SIMULATIONS OF THE FLASH DPLL 1. Conventional DPLL Fig. 10 shows part of the flash DPLL, namely the conventional DPLL. It is composed of a PFD, CP, LPF, and VCO. CP#1 was used in this circuit. Many example positive and negative frequency jumps (hops) were performed in the frequency range 300MHz-2GHz. The DPLL is considered to be

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Fig. 10. Conventional DPLL Schematic locked when Vcntl becomes ripple-free and the phase shift between Fvco and Fref becomes zero or constant.

2. The Flash DPLL Fig. 11 shows the Flash DPLL schematic used for simulations.

Fig. 11. Flash DPLL Simulation Schematic

It should be noted that attempted simulations while using the array of frequency comparators took very long times which were disproportionate to the time taken by an individual frequency comparator. To avoid simulation interruptions due to kick offs by Cadence servers, the array of frequency comparators was replaced by a block which merely exhibits 40ns delay then places the thermometer code, corresponding to the new input frequency under consideration (after the hop), at the input of the priority encoder, as shown in Fig. 11. This method of simulation provides a reasonably good estimate of the DPLL lock times for different input frequency hops. Many example frequency hops were performed in the frequency range 300MHz-2GHz. Example simulations for the frequency hop of 300MHz-1.8GHz are shown in Figs. 12, 13. Fig. 12 clearly shows an input frequency hop taking place at 200ns, which will be followed by a “conventional” change of Vcntrl during the above-mentioned 40ns delay. At about 240ns, Vcntrl jumps steeply when the new CP is selected thus marking the end of the coarse- tuning stage and the beginning of the fine-tuning stage; the later stage ends with DPLL locking at 297ns.

Fig. 12. Flash DPLL 300MHz-1.8GHz Hop (Hop Took Place at 200ns & Tlock = 97ns)

Fig. 13. Flash DPLL 300MHz-1.8GHz Hop (Zoomed to View Waveforms at Locking)

3. Comparison Table Table 3 provides a summary of simulation results. It compares the fast-locking DPLL versus the conventional DPLL; it also compares all lock times for different values of positive and negative frequency hops.

Frequency Hop

Fast-Locking DPLL

(ns)

Conventional DPLL

(ns) 300M–800M 92 150

300M–1G 103 217 300M–1.8G 97 312 600M–1.3G 98 181 800M–300M 116 302

1G–300M 120 362 1.8G–300M 119 502 1.3G–600M 140 388

Table 3. Lock-Time Comparison for Flash and

Conventional DPLLs at Different Frequency Hops (M=MHz & G=GHz)

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V. CONCLUSIONS

A novel fast-locking DPLL was designed to improve the lock time over that of the conventional DPLL. The fast-locking DPLL employs a flash algorithm similar to the one employed in flash A/D converters, thus expecting a fast response at the expense of increased hardware. The flash DPLL operation employs two stages: a novel coarse-tuning stage followed by a fine-tuning stage that resembles the operation of conventional DPLLs. Design considerations for the various circuit components were discussed and some Cadence- Spectre testing results for these components were provided. The entire conventional DPLL was easy to simulate using Cadence-Spectre. However, the entire flash DPLL was possible to simulate using Cadence-Spectre only after replacing the frequency comparator array with a block that exhibits time delay and finally produces a thermometer code representing the target input frequency (after the frequency hop). The flash DPLL was verified to operate in frequency range 200MHz – 2GHz. Table 3 demonstrates that there is a significant improvement in the lock time by using the flash DPLL as opposed to the conventional DPLL. Faster lock times of the flash fast-locking DPLL can be achieved by including a larger array of frequency comparators composed of 16 or 32 comparators; this will result in a finer coarse-tuning stage and consequently a faster fine-tuning stage. It is thus expected that all lock times will be below the 100ns mark in the above-mentioned frequency range.

VI. ACKNOWLEDGEMENT This work is sponsored by the U.S.-Egypt Science and Technology Joint Fund in cooperation with the National Science Foundation under NSF Grant No. 0710887.

VII. REFERENCES [1] M. Keaveney, P. Walsh, M. Tuthill, C. Lyden, and B. Hunt, “ADF4193 Low Phase Noise, Fast Settling PLL Frequency Synthesizer Based on a 10�s Fast Switching PLL Synthesizer for a GSM/EDGE Base Station”, Cellular Systems and Building Blocks, ISSCC 2004. [2] C. Ajluni, “PLLs Plot an Adjustable Course”, Electronic Design, June 2003, http://www. wsdmag.com/Articles/ArticleID/6451/6451.html.

[3] P. Larsson, “Reduced Pull-In Time of Phase- Locked Loops Using a Simple Nonlinear Phase Detector”, IEE Proc. on Communications, vol. 142, pp. 221-226, 1995. [4] M. F. Wagdy and S. Vaishnava, “A Fast- Locking Digital Phase-Locked Loop”, Proc. of the 3rd Intl Conf. on Information Technology: New Generations (ITNG-2006), Las Vegas, Nevada, pp. 742-746, April 10-12, 2006. [5] A. Bellaouar and K. Sharaf “Fast Lock Self Tuning VCO Based PLL”, U. S. Patent #6,566,966, May 20, 2003. [6] C. M. Davis, D. L. Broughton, and E. W. Porter, “Method and Circuit for Improving Lock-Time Performance for a Phase-Locked Loop”, U. S. Patent # 6,624,707, September 23, 2003. [7] J. J. McDonald, II and R. B. Hulfachor, “Circuitry to Reduce PLL Lock Acquisition Time”, U. S. Patent # 6,940,356, Sept. 6, 2005. [8] Analog Devices Inc., “ADF4007 – High Frequency Divider/PLL Frequency Synthesizer”, http://www.analog.com. [9] True Circuits, Inc., www.truecircuits.com/ product_matrix.html. [10] National Semiconductor, Inc., “A Fast Locking Scheme for PLL Frequency Synthesizers”, Application Note 1000, July 1995, http://www.national.com. [11] M. F. Wagdy, NSF Grant No: 0710887 for the Proposal: “US-Egypt Cooperative Research: A Novel Flash Fast-Locking Wide-Band Digital Phase-Locked Loop”. Project duration is Aug. 1, 2007 to July 31, 2009. [12] R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation”, 2nd Edition, IEEE Press (Wiley Interscience), Piscataway, NJ, 2005. [13] P. Gadde and M. F. Wagdy, “A 2-GHz Digital PLL Using 0.18μm CMOS Technology”, Proc. of the IEEE 2nd International Computer Engineering Conference (ICENCO 2006), Cairo, Egypt, pp. HW 61-66, Dec. 26-28, 2006. [14] Nizamani, Abdul Shakoor, “A Novel Frequency Comparator: Applications in Frequency Meters and in Difference Clocks for Generator Frequency Error Monitors,” IEEE Trans. on I&M, Vol. 45, No. 1, pp. 320-323, Feb. 1996. [15] M. F. Wagdy and Q. Xie, "Comparative ADC Performance Evaluation Using a New Emulation Model For Flash ADC Architectures", Proc. of the 37th Midwest Symp. on Circuits and Systems, pp. 1159-1163, Lafayette, LA, August 3-5, 1994.

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