ics basic simula

8/13/2019 Ics Basic Simula

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Chapter 11

Operational Amplifiers and Applications


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Chapter Goals

Understand the magic of negative feedback and thecharacteristics of ideal op amps.

Understand the conditions for non-ideal op amp behavior sothey can be avoided in circuit design.

Demonstrate circuit analysis techniques for ideal op amps. Characterize inverting, non-inverting, summing and

instrumentation amplifiers, voltage follower and first orderfilters.

Learn the factors involved in circuit design using op amps.

Find the gain characteristics of cascaded amplifiers.

Special Applications: The inverted ladder DAC and successiveapproximation ADC


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Differential Amplifier Model: Basic

Represented by:

A = open-circuit voltage gain

vid= (v+-v-) = differential input signal

voltage

aRid= amplifier input resistanceRo= mplifier output resistance

developed at the amplifier output is in

phase with the voltage applied at the +

input (non-inverting) terminal and 180

out of phase with that applied at the -

input (inverting) terminal. The signal


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Ideal Operational Amplifier

The ideal op amp is a special case of the ideal differential amplifierwith infinite gain, infiniteRidand zeroRo.

and

If A is infinite, vidis zero for any finite output voltage.

Infinite input resistanceRidforces input currents i+and i-to be zero.

The ideal op amp operates with the following assumptions:

It has infinite common-mode rejection, power supply rejection, open-loop bandwidth, output voltage range, output current capability and

slew rate

It also has zero output resistance, input-bias currents, input-offsetcurrent, and input-offset voltage.

Aov

idv 0id

vlim A


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The Inverting Amplifier: Configuration

The positive input is grounded. A feedback network composed of resistorsR1andR2is connected

between the inverting input, signal source and amplifier output node,

respectively.


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Inverting Amplifier:Voltage Gain

The negative voltage gainimplies that there is a 1800phaseshift between both dc andsinusoidal input and outputsignals.

The gain magnitude can begreater than 1 ifR2>R1

The gain magnitude can be lessthan 1 ifR1>R2

The inverting input of the op

amp is at ground potential(although it is not connecteddirectly to ground) and is said to

be at virtual ground.

0ov22i

1isv RRs

1

svsi

R

But is= i2 and v-= 0 (since vid= v+ - v-= 0)

and

1

2

svov

R

R

vA


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Inverting Amplifier: Input and Output

Resistances

Rinvsis

R1 since v 0

Routis found by applying a test current

(or voltage) source to the amplifier

output and determining the voltage (or

current) after turning off all

independent sources. Hence, vs = 0

11i

22ixv RR

But i1=i2

)12

(1ixv RR

Since v- = 0, i1=0. Therefore vx = 0

irrespective of the value of ix .

0out

R


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Inverting Amplifier: Example

Problem: Design an inverting amplifier

Given Data: Av= 20 dB,Rin= 20kW,

Assumptions: Ideal op amp

Analysis: Input resistance is controlled byR1

and voltage gain is set

byR2/R1.

andAv = -100

A minus sign is added since the amplifier is inverting.

AvdB

20log

10Av

, Av10

40dB/20dB100

W k201 inRR

AvR

2R

1

R2

100R1

2MW


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The Non-inverting Amplifier: Configuration

The input signal is applied to the non-inverting input terminal. A portion of the output signal is fed back to the negative input

terminal.

Analysis is done by relating the voltage at v1to input voltage vsand

output voltage vo.


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Non-inverting Amplifier: Voltage Gain,

Input Resistance and Output Resistance

Since i-=0 and

Butvid=0

Since i+=0

21

1ov1

vRR

R

1vid

vsv

1vsv

1

21

1

21

svov

121svov

R

R

R

RRvA

R

RR

isv

inR

Routis found by applying a test current source to the amplifier output

after setting vs = 0. It is identical to the output resistance of the inverting

amplifier i.e.Rout= 0.


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Non-inverting Amplifier: Example

Problem: Determine the output voltage and current for the given non-

inverting amplifier.

Given Data: R1= 3kW,R2= 43kW, vs= +0.1 V

Assumptions: Ideal op amp

Analysis:

Since i-=0,

Av1R

2R

1

1 43kW3kW

15.3

voAvvs(15.3)(0.1V)1.53V

A3.33k3k43

V53.1

12

ovoi WW

RR


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Finite Open-loop Gain and Gain Error

21

1

ovov

21

11v

RR

R

RR

R

is called the

feedback factor.

A

AvA

AAA

1svov

)ovsv()1vsv(id

vov

Ais called loop gain.

ForA>>1,

Av1

1

R2

R1

This is the ideal voltage gain of

the amplifier. IfA is not >>1,

there will be Gain Error.


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Gain Error

Gain Error is given by

GE = (ideal gain) - (actual gain)

For the non-inverting amplifier,

Gain error is also expressed as a fractional or percentage

error.

)1(

1

1

1

AA

AGE

FGE

1

A

1A1

11A 1A

PGE 1A

100%


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Gain Error: Example

Problem: Find ideal and actual gain and gain error in percent

Given data: Closed-loop gain of 100,000, open-loop gain of

1,000,000.

Approach: The amplifier is designed to give ideal gain and deviations

from the ideal case have to be determined. Hence,.

Note: R1andR2arent designed to compensate for the finite open-loop

gain of the amplifier.

Analysis:

1

105

Av A

1A

106

1106

105

9.09x104

PGE105 9.09x104

105 100%9.09%


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Output Voltage and Current Limits

Practical op amps have limited

output voltage and current ranges.

Voltage: Usually limited to a few

volts less than power supply span.

Current: Limited by additionalcircuits (to limit power dissipation

or protect against accidental short

circuits).

The current limit is frequently

specified in terms of the minimum

load resistance that the amplifier

can drive with a given output

voltage swing. Eg: io

5V500W

10mA

)21(

ov

12

ovov

Fi

Lioi

RRLREQR

EQRRR

LR

For the inverting amplifier,

2R

LR

EQR


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Example PSpice Simulations of

Non-inverting Amplifier Circuits


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The Unity-gain Amplifier or Buffer

This is a special case of the non-inverting amplifier, which is alsocalled a voltage follower, with infiniteR1and zeroR2. HenceAv= 1.

It provides an excellent impedance-level transformation while

maintaining the signal voltage level. The ideal buffer does not require any input current and can drive anydesired load resistance without loss of signal voltage.

Such a buffer is used in many sensor and data acquisition systemapplications.


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The Summing Amplifier

Scale factors for the 2 inputscan be independently adjusted

by the proper choice ofR2andR1.

Any number of inputs can beconnected to a summing

junction through extraresistors.

This circuit can be used as asimple digital-to-analogconverter. This will beillustrated in more detail, later.

1

1v

1i

R

2

2v

2i

R

3

ov

3i

R

Since the negative amplifier

input is at virtual ground,

Since i-=0, i3= i1+ i2,

voR

3R

1

v1

R

3R

2

v2


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The Difference Amplifier

This circuit is also called adifferential amplifier, since itamplifies the difference betweenthe input signals.

Rin2is series combination ofR1andR2because i+is zero.

For v2=0,Rin1= R1, as the circuitreduces to an inverting amplifier.

For general case, i1is a functionof both v1and v2.

1v

1

2-v

1

21)-v1v(

1

2-v

21i-v22

i-vov

R

R

R

RR

R

R

RR

v R

2R

1R

2

v2

Also,

Since v-= v+ )2v

1(v

1

2v R

Ro

ForR2= R1)

2v

1(vv o


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Difference Amplifier: Example

Problem: Determine vo

Given Data: R1= 10kW,R2=100kW, v1=5 V, v2=3 V

Assumptions: Ideal op amp. Hence, v-= v+and i-= i+= 0.

Analysis: Using dc values,

Adm

R

2R

1

100kW10kW

10

VoAdmV1

V2

10(53)

Vo20.0 V

HereAdmis called the differential mode voltage gain of the difference amplifier.


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Finite Common-Mode Rejection Ratio

(CMRR)A(orAdm) = differential-mode gainAcm= common-mode gain

vid= differential-mode input voltage

vic= common-mode input voltage

A real amplifier responds to signal

common to both inputs, called the

common-mode input voltage (vic).

In general, voAdm

v

id

Acm

vic

Adm

Adm

v

id

vic

CMRR

CMRRAdm

Acm

and CMRR(dB)20log10

(CMRR)

An ideal amplifier hasAcm= 0, but for a

real amplifier,

21 id

v

icvv 22 id

v

icvv

voAdm(v

1v

2)Acm

v1

v2

2

voAdm(vid

)Acm(vic)


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Finite Common-Mode Rejection Ratio:

Example

Problem: Find output voltage error introduced by finite CMRR.

Given Data: Adm= 2500, CMRR = 80 dB, v1= 5.001 V, v2= 4.999 V

Assumptions: Op amp is ideal, except for CMRR. Here, a CMRR in dBof 80 dB corresponds to a CMRR of 104.

Analysis:

The output error introduced by finite CMRR is 25% of the expected idealoutput.

vid

5.001V4.999V

vic

5.001V4.999V2

5.000V

voAdmvid

vicCMRR

2500 0.002 5.000

104

V6.25V

In the "ideal" case, v

o

Adm

v

id

5.00 V

% output error 6.255.005.00

100%25%


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uA741 CMRR Test: Differential Gain


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Differential Gain Adm

= 5 V/5 mV = 1000


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uA741 CMRR Test: Common Mode Gain


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Common Mode Gain Acm= 160 mV/5 V = .032


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CMRR Calculation for uA741

CMRRA

dm

Acm

1000

.0323.125x10

4

CMRR(dB) 20log10CMRR 89.9 dB


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Instrumentation Amplifier

Combines 2 non-inverting amplifiers

with the difference amplifier to

provide higher gain and higher input

resistance.

)bva(v

3

4v R

Ro

bv

2i)

1i(2

2iav RRR

12

2

v

1

v

iR

)2

v1

(v

1

21

3

4v

R

R

R

R

o

Ideal input resistance is infinite

because input current to both op

amps is zero. The CMRR is

determined only by Op Amp 3.

NOTE


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Instrumentation Amplifier: Example

Problem: Determine Vo

Given Data: R1 = 15 kW,R2= 150 kW,R3= 15 kW,R4= 30 kWV1 = 2.5 V,

V2 = 2.25 V

Assumptions: Ideal op amp. Hence, v-= v+and i-= i+= 0.

Analysis: Using dc values,

Adm

R

4R

3

1R

2R

1

30kW15kW

1150kW15kW

22

VoAdm(V1V2)22(2.52.25)5.50V


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The Active Low-pass Filter

Use a phasor approach to gain analysis of

this inverting amplifier. Let s = jw.

Avvo

(jw)

v(jw)

Z2(jw)

Z1(jw)

Z1jw R1

Z2(jw)

R2

1

jwC

R2

1jwC

R2jwCR2

1

AvR2

R1

1

(1jwCR2

)R2

R1

ej

(1

jw

wc

)

wc2fc 1R2C

fc 12R2C

fcis called the high frequency cutoff of

the low-pass filter.


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Active Low-pass Filter (continued)

At frequencies belowfc(fHin thefigure),the amplifier is aninverting amplifier with gain set

by the ratio of resistorsR2andR

1

.

At frequencies abovefc, theamplifier response rolls off at-20dB/decade.

Notice that cutoff frequency andgain can be independently set.

AvR2

R1

ej

(1jwwc

)

R2

R1

12 wwc

2

ej

ejtan1(w/w

c)

R2

R1

1 wwc

2ej[ tan1(w/w

c)]

magnitude phase


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Active Low-pass Filter: Example

Problem: Design an active low-pass filter

Given Data: Av= 40 dB,Rin= 5 kW,fH= 2 kHz

Assumptions:Ideal op amp, specified gain represents the desired low-frequency gain.

Analysis:Input resistance is controlled byR1and voltage gain is set byR2/R1.

The cutoff frequency is then set by C.

The closest standard capacitor value of 160 pF lowers cutoff frequencyto 1.99 kHz.

100dB20/dB4010 vA

W k51 in

RR

AvR

2R

1

R2

100R1

500kW

C 12fHR2

12(2kHz)(500kW)159pF

and


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Low-pass Filter Example PSpice Simulation


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Output Voltage Amplitude in dB


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Output Voltage Amplitude in Volts (V) and Phase in Degrees (d)


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Cascaded Amplifiers

Connecting several amplifiers in cascade (output of one stage connected tothe input of the next) can meet design specifications not met by a singleamplifier.

Each amplifer stage is built using an op amp with parametersA, Rid

, Ro

,called open loop parameters, that describe the op amp with no externalelements.

Av, Rin, Routare closed loop parameters that can be used to describe eachclosed-loop op amp stage with its feedback network, as well as the overallcomposite (cascaded) amplifier.


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Two-port Model for a 3-stage Cascade

Amplifier

Each amplifier in the 3-stage cascaded amplifier is replaced by its 2-portmodel.

voAvAvsRinB

RoutA

RinB

AvB

RinC

RoutB

RinC

AvC

vCAvBAvAAvA svov

SinceRout= 0

Rin= RinA and Rout=RoutC= 0


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A Problem: Voltage Follower Closed

Loop Gain Error due to A and CMRR

ovsvidv

2ovsv

icv

voA vsvo vsvo

2(CMRR)

Avvovs

A1 1

2(CMRR)

1A1 12(CMRR)

The ideal gain for the voltage

follower is unity. The gain error

here is:

GE1Av1 ACMRR

1A1 12(CMRR)

Since, both A and CMRR are

normally >>1,

GE 1

A 1

CMRR

SinceA~ 106and CMRR ~ 104at

low to moderate frequency, the gain

error is quite small and is, in fact,

usually negligible.


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Inverted R-2R Ladder DAC

A very common DAC circuit architecture with good precision.

Currents in the ladder and the reference source are independent of digital

input. This contributes to good conversion precision. Complementary currents are available at the output of inverted ladder.

The bit switches need to have very low on-resistance to minimize

conversion errors.


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Successive Approximation ADC

Binary search is used by the SAL to determine vX.

n-bit conversion needs nclock periods. Speed is

limited by the time taken by the DAC output to

settle within a fraction of an LSB of VFS, and by the

comparator to respond to input signals differing by

small amounts.

Slowly varying input signals, not changing bymore than 0.5 LSB (VFS/2

n+1) during the

conversion time (TT= nTC) are acceptable.

For a sinusoidal input signal with p-p amplitude =

VFS,

To avoid this frequency limitation, a high speedsample-and-hold circuit is used ahead of the

successive approximation ADC.

This is a very popular ADC with fast conversion

times, used in 8- to 16- bit converters.

fo fc

2n2(n1)


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SAADC: Block Diagram


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SAADC: Method of Operation

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