i ee115al outline - uclaicslwebs.ee.ucla.edu/yang/labswiki/images/.../ee115al_introduction.pdf ·...

ELECTRICAL ENGINEERING DEPARTMENT: EE115AL ANALOG ELECTRONICS LABORATORY INTRODUCTION

1

INTRODUCTION TO EE115AL

OUTLINE

EE115AL ANALOG ELECTRONICS LABORATORY I: COURSE APPROACH .......................... 2 COURSE WIKI ........................................................................................................................................... 2 LABORATORY APPROACH .................................................................................................................. 3 CRITICAL ACTIONS FOR TODAY ....................................................................................................... 3 FIRST ASSIGNMENT: PRE-LAB ........................................................................................................... 4 PREVIEW OF EE115AL LABORATORIES .......................................................................................... 5 EE115AL LABORATORY SUPPORT .................................................................................................... 7 ENGINEERING PIPELINE KIT .............................................................................................................. 7 GRADING ................................................................................................................................................... 9 EE115AL PERSONAL INSTRUMENTS ............................................................................................... 10 EE115AL: MYDAQ INSTRUMENTS .................................................................................................... 11 EE115AL FIRST PROJECT: COMMON COLLECTOR AMPLIFIER DESIGN ........................... 14 EE115AL: CIRCUIT IMPLEMENTATION PRACTICE ................................................................... 17 PREVIEW OF LABORATORY 1: COMMON COLLECTOR AMPLIFIER .................................. 25 APPENDIX: REVIEW OF BIPOLAR JUNCTION TRANSISTOR STRUCTURE AND DEVICE OPERATION ............................................................................................................................................ 27

SEMICONDUCTOR P-N JUNCTION ELECTROSTATICS .............................................................................. 27 THE SEMICONDUCTOR BIPOLAR JUNCTION TRANSISTOR: STRUCTURE AND OPERATION ............................................................................................................................................ 31 EMITTER, BASE, AND COLLECTOR CURRENT RELATIONSHIPS ......................................... 35 NPN AND PNP TRANSISTORS ............................................................................................................. 36 TRANSISTOR CURRENT-VOLTAGE CHARACTERISTICS ......................................................... 37


2

EE115AL ANALOG ELECTRONICS LABORATORY I: COURSE APPROACH

• EE115AL is developed to provide all students with hands-on design experience with the flexibility of learning on each student’s schedule and at their preferred location on campus or home.

• EE115AL is developed to provide experience and confidence with physical design, experimental system assembly, and experimental evaluation

• EE115AL is developed to provide experience in designing systems to meet the most important performance objectives

• Component and Complete System Gain

• Input and Output Resistance Characteristics

• Linear response amplification (sensing)

• Linear response drive signals (actuation)

• Design of sensor and sensor interface circuits

• Design of source and source drive circuits

• An audio presentation on the EE115AL Background and Systems is available at the Course Wiki.

http://icslwebs.ee.ucla.edu/yang/labswiki/index.php/EE115AL

Please see EE115A Course Orientation Video 1

• Please do review this – this is quite essential for understanding our new instrument systems.

COURSE WIKI

• All reference materials, Laboratory descriptions, tutorials, syllabus, and grading information are here:

http://icslwebs.ee.ucla.edu/yang/labswiki/index.php/EE115AL

• Please create a Wiki account immediately


3

LABORATORY APPROACH

• Design, development, and experimental verification is completed anywhere and anytime convenient for students

• Lab Sessions are devoted to:

• Obtaining assistance

• System demonstration to Teaching Assistants for Project Grading

• Quiz completion

• Lab Assistance

• Please arrive prepared

CRITICAL ACTIONS FOR TODAY

• Select a Lab Partner Today!

• Students work in pairs

• At least one partner should have notebook, PC workstation, or Mac with VMWare/Windows XP systems available

• SEASnet systems (4th Floor Lab) will be available

• Critical Next Steps

• Get a Kit!

• Please plan to return the myDAQ in its original box when the course is over note that this is convenient for assembly

• Complete the Pre-Lab now

http://icslwebs.ee.ucla.edu/yang/labswiki/index.php/Pre-Laboratory


4

FIRST ASSIGNMENT: PRE-LAB

• Please proceed on this immediately

• Install myDAQ system software

• Then, complete the myDAQ Tutorial

• Please read the Wiki pages associated with introduction and the Pre-Lab

• We will review this in lecture today.

• However, you can also download and carefully listen to the presentation

• This is noted that the Pre-Lab page of the Wiki http://icslwebs.ee.ucla.edu/yang/labswiki/index.php/Pre-Laboratory#Introduction

• and is at this link: http://www.seas.ucla.edu/~kaiser/EE115A/EE115AL_myDAQ_Tutorial_With_Narration.pptx


5

PREVIEW OF EE115AL LABORATORIES

• Laboratory 1 will introduce us to the design of transistor amplifiers with the

classic Common Emitter amplifier. We will implement this amplifier using a convenient method for modifying its performance in gain, input resistance, and linear response. We will be using our myDAQ instruments to characterize this device. We will also optimize our design to meet specific performance objectives.

• Laboratory 2 will introduce us to the design of circuits that support optoelectronic devices.

• We will be implementing an “optical coupler”. Optical couplers are widely used and important electronic components that appear in these applications that we will discuss:

- Optical sensor systems are critical in control systems appearing in vehicle control systems, industrial automation, and now new entertainment systems.

- These apply optical sources to direct optical radiation towards a mechanism that may block or redirect the radiation in a manner that is sensitive to orientation.

- This can produce remarkably accurate sensor systems for position, rotation, and other orientation measurements.

- Devices ranging from advanced actuator control for aircraft, to the ubiquitous optical mouse, and the Microsoft Kinect all depend on this. These apply the same technology we are implementing in EE115AL

- Optical couplers are applied to enable close range communication between two electronic system modules by communicating analog or digital signals between the two modules.

- This allows the modules to themselves be isolated with regards to direct links via electronic conductors. This finally enables an important architecture enabling


6

electronic safety in medical instruments that exploit this electronic conductor isolation to protect patients.

• This Laboratory will include both amplifier circuits that support optoelectronic sensors as well as circuits that drive optoelectronic light sources. Our sensors and sources will be coupled in free space on your circuit prototyping board.

• We will also be introducing the transistor “current mirror” circuit to support linear operation of our optical coupler

• Laboratory 3 will introduce us to the design of complete operational amplifier circuits that support optoelectronic devices. These will include devices that provide both sensitive detection and high performance source drive circuits.


7

EE115AL LABORATORY SUPPORT

• Laboratory Hours

• Meet Teaching Assistants and Instructor

• Tuesday 12:00 – 4:00 and 4:00 – 8:00

• Thursday 12:00 – 4:00 and 4:00 – 8:00

• Stock room

• Available for additional components as needed

• Quiz Sessions

• Three quizzes to be announced

• One quiz assigned for each Laboratory

• Course Assessment and Grading Noted on Course Wiki

• Laboratory Assignment Demonstrations

• Student partners must arrive at lab session and demonstrate their circuit system

• Students must also explain their designs

• Both partners must be ready to answer questions on their system

• Laboratory Reports

• Describes design approach

• Describes problems encountered and solutions

ENGINEERING PIPELINE KIT

• Components

• Circuit Protoboard

• Circuit Protoboard Wire Kit

• Tools

• Passive and Active Components


8

• The National Instruments myDAQ

• DAC and ADC with 200 ksps sampling

• USB interface to platform

• Many instruments described in the Tutorial

• Laboratory Resources

• All available on course Wiki

• Laboratory Description

• Hints

• Videos

• Background materials


9

GRADING

• Laboratory 1 contributes 25%

• Laboratory 2 contributes 25%

• Laboratory 3 contributes 30% to overall grade.

• Quizzes collectively contribute 15% to the overall grade.

• Quizzes will require 20 minutes (or less) and will be assigned at the beginning of Lab Section as noted in the Course Syllabus Schedule on the Wiki page.

• Completing the course evaluation contributes 5% to the overall grade. Please complete course evaluations on eeweb (as opposed to CourseWeb).

• Grading

• For each laboratory, the live demonstration of the working design contributes one-half of the credit for each laboratory. The Report contributes the additional one-half.

• Students on the same team receives the same grade. The grade of a team depends on equal parts the demonstration of a working design and the report.

• The demonstration involves not only showing the proper signals and functionality, but students should also be prepared to answer questions on their design.

• Students are encouraged to discuss design approaches and help each other debug.

• However, each team must do their own work.


10

EE115AL PERSONAL INSTRUMENTS

• Primary Instruments

• Please see the myDAQ Tutorial information on the Wiki Pre-Lab page

• Digital Multimeter

• Voltage

• Resistance

• Current (not required or recommended)

• Oscilloscope

• Digital Signal Analyzer

• Function Generator


11

EE115AL: MYDAQ INSTRUMENTS

Figure 1. Digital Multimeter

Figure 2. Oscilloscope


12

Figure 3. Function Generator


13

Figure 4. Dynamic Signal Analyzer (DSA) with 100mVp-p input applied to Common Emitter Amplifier, with Emitter Degeneration Resistor of 750 kΩ. Note the Total Harmonic Distortion of 0.09%. Also, note that the Power Spectral Density mode is selected.

Figure 5. Dynamic Signal Analyzer (DSA) with 100mVp-p input applied to Common Emitter Amplifier, without Emitter Degeneration. Note the Total Harmonic Distortion of 32%.


14

EE115AL FIRST PROJECT: COMMON COLLECTOR AMPLIFIER DESIGN

• Now, our development and first laboratory will begin with the development of a classic and critical amplifier that you have learned about in EE115A. Please note that this set of lectures includes a review of the princilpes of this amplifier.

• We will wish to design this device to meet a specific gain, to establish bias point at a specific operating condition selected for greatest reliability, and to measure gain and input resistance for a circuit operating with and without emitter degeneration (that you also learned about in EE115A).

• We will also be using a myDAQ tool that is designed to measure circuit linearity, in particular, Total Harmonic Distortion (THD) to which you were introduced in EE102.

• This tool is the Dynamic Signal Analyzer (DSA) that computes Power Spectral Density of a signal and also computes THD as the ratio of power in all signal harmonics to the power at the signal fundamental. An ideal amplifier would exhibit a zero THD value.

• However, we will find that THD depends on our circuit design choices - in particular whether we select emitter degeneration.

• The Lecture 1 materials will provide a complete review of Small Signal properties of the Common Collector amplifier

• The Lecture 2 materials will provide a complete review of Bias Circuit Design

• A preview of Laboratory 1 also appears at the end of this Lecture 1.


15

Figure 6. Common Emitter Amplifier in Circuit Characterization Configuration

Figure 7. Common Emitter Amplifier in Circuit Characterization Configuration with Source Resistance present for measurement of input resistance.


16

• Nominal circuit component values and circuit terminal potentials are listed here.

• It is very important to always check and verify the values of all potentials and all resistor and capacitor values. Direct measurement with the DMM will be important.

• RB1 = 40kΩ (May be implemented as two 20kΩ resistors in series)

• RB2 = 20kΩ

• RE =750Ω

• RC = 1.2kΩ

• CInput = 0.39 microF

• COutput = 0.39 microF

• CBypass = 100 microF

• VC ≈ 3.31V

• VE ≈ 0.87V

• VB ≈ 1.50V

• VCC ≈ 4.70V

Figure 8. The 2N2222A Transistor package specification


17

EE115AL: CIRCUIT IMPLEMENTATION PRACTICE

• Assembly Approach

• Use DMM to check ALL connections and values below.

• Note that DMM can only be used to measure isolated terminals when examining resistance values.

• Assembly Problems

• Short circuits

- Bare leads

- Leads contacting device packages – the 2N222A metallic package is connected to the Emitter terminal – accidental contact may lead to a short

- Reverse polarity of electrolytic capacitors

• Power supply faults

- Power supply disconnected or polarized incorrectly!

- Analog Ground fault

- Sensing Terminal faults

- Output Terminal faults

• Resistor values

- Always check and confirm before applying power

- Transistor and integrated circuit connections - always check and confirm before applying power


18

• Resistor color code (please see

http://en.wikipedia.org/wiki/Electronic_color_code )

Figure 9. Resistor color code information

• The resistor shown above has a value of 27 x 105 Ohm or 2.7 MegOhm


19

• Circuit Construction

• Take effort to ensure organized and neat layout

• This is essential for examining a circuit, detecting and solving for errors, and seeking help

• Avoid long (non-insulated) resistor or capacitor leads

• Never use a wire gauge larger than in the kit

• Circuit Construction and myDAQ connection figures discussed in the audio lecture for this document, available at the Wiki

• Capacitor Technology

• Now, the capacitor technology we will be using in EE115AL will include devices of small value (less than one microFarad) to those in the range of 100 microFarad.

• Large value capacitors are implemented using an electrolytic technology that permits operation for only one polarity. These capacitors will fail if reverse polarized. This can create a fault in your circuit and can also be generally unsafe.

• Note in the images below that a 100 microFarad capacitor is present.

• Its package contains a grey stripe along the length of the package. This indicates the negative (cathode) terminal.

• Please be very careful in this selection.

1)


20

2)

3)

4)

5)

6)


21

7)

8)

9)

10)

11)


22

12)

13)

14)

15)

16)


23

17)

18)

19)

20)

21)


24

22)

23)

24)

25)


25

PREVIEW OF LABORATORY 1: COMMON COLLECTOR AMPLIFIER

1) Design

a. We will duplicate and test a circuit design provided

b. We will then apply our Bias Circuit analysis background to adjust its component selection to meet design criteria

2) Analysis

a. We will apply small signal analysis to estimate gain and input resistance

3) Experimental Characterization

a. We will implement our circuit and characterize its operation to compute gain and input resistance

b. Figure 6 shows an experimental configuration we may apply in computing gain

c. Figure 7 shows an experimental configuration we may apply in computing input resistance.

d. We will begin with measuring the device β value

4) Amplifier Optimization

a. Finally, we will adjust our design to meet performance specifications


26

Figure 10. Measureing signal at Collector of Common Emitter Amplifier. Note that the Function Generator is configured with a 20 kHz signal frequency, amplitude of 0.01Vp-p and no offset applied. Note also that Run has been selected to enable the instrument. The Scope is set for 20 microseconds per division sweep rate to create a time axis and an amplitude of 500 mV/division for vertical range sensitivity. Note that the offset is maximum and negative at -6. This is also Edge Triggered (this is an optional setting that students should become familiar with).

Figure 11. An example of measuring signals at both of the RS Terminals. This enables a computation of current in RS and ultimately input resistance, Ri , for the amplifier.


27

APPENDIX: REVIEW OF BIPOLAR JUNCTION TRANSISTOR STRUCTURE AND DEVICE OPERATION

SEMICONDUCTOR P-N JUNCTION ELECTROSTATICS

• We must begin by discussing the fundamental p-n junction electrostatic characteristics.

• First, a typical p-n junction formed by “diffusion” or “implantation” methods is shown below.

Figure 12. p-n diode showing circuit symbol and corresponding physical structure

• A schematic view of the p-n junction where we consider a cross-sectional view is shown below.

• Now, the semiconductor p- and n-doped regions will display high conductivity at room temperature in the “bulk” region of the material. However, novel phenomena will appear at the p-n interface.

Figure 13, p-n diode showing symbol and cross-sectional view.

• First, we can examine the variation in density of donors (NA) and acceptors

(NB)

• First, we can examine the variation in density of donors (NA) and acceptors (NB)

pnpn

p np n


28

Figure 14. p-n diode showing dopant density distribution.

• Now, the density of hole carriers in the p region, pp, and electron carriers in

the n region, nn , is shown.

• Now, when a p-n junction is formed, the vast difference in electron and hole density drives the physical process of diffusion.

Figure 15. p-n diode showing carrier density distirbution adn carrier flux due to diffusion

• Diffusion continues to transfer charge carriers between n and p material.

• If carriers were uncharged, an equilibrium with a uniform spatial distribution of carriers would occur.

• However, as charge transfer occurs, the presence of displaced charge induces an electric field that opposes further transport.

• The p-n junction arrives at an equilibrium with a “built-in” dipole charge and “built-in” potential.

• This “built-in” potential induces an electric field that sweeps carriers away from the region of the p-n junction interface

• This creates a “depletion region”

• The “depletion region” appears in the region for –xp < x < xn. The charge distribution appears:

ND

-NA

log (ND – NA)

x

ND

-NA

log (ND – NA)

x

nn = ND

log n, p

x

np(x)

pp(x)= NA

pn(x)

e-h+

xn-xp

nn = ND

log n, p

x

np(x)

pp(x)= NA

pn(x)

e-h+

xn-xp


29

Figure 16. p-n diode showing charge density distribution in equilibrium

• Of course, this charge distribution yields an electric field:

Figure 17. p-n diode showing field distribution in equilibrium

• And the electric field produces this associated potential energy difference for charge carriers

Figure 18. p-n diode showing potential distribution in equilibrium

• First, we examine the electron energy diagram below. This displays both the energy-dependent distribution of electron carriers and the spatial dependence of electron energy.

• Note that two currents exist: 1) A drift current due to electric field (and associated potential energy difference) acting on the available minority carriers, and 2) A diffusion current.

ND

log ρ(x)

xNA

xn

-xpND

log ρ(x)

xNA

xn

-xp

ND

xNA

xn

-xp

E(x)

ND

xNA

xn

-xp

E(x)

xxn

-xp

V(x)

VBI

xxn

-xp

V(x)

VBI


30

Figure 19. p-n diode showing drift and diffusion carrier flux.

• Of course, there is a corresponding hole energy diagram.

Figure 20. p-n diode showing drift and diffusion carrier flux.

• Under equilibrium conditions, net current is zero

• Now, under an applied Forward Bias, V , electron energy at the n side is promoted relative to that at zero bias.

Figure 21. p-n diode showing drift and diffusion carrier flux under forward bias

xxn

-xp

Electron Energy (x)

JnDrift JnDiffusion

xxn

-xp

Electron Energy (x)

JnDrift JnDiffusion

xxn

-xp

Hole Energy (x)

JpDiffusion JpDrift

xxn

-xp

Hole Energy (x)

JpDiffusion JpDrift

xxn

-xp

ElectronEnergy (x)

JnDrift JnDiffusion

V

xxn

-xp

ElectronEnergy (x)

JnDrift JnDiffusion

V


31

• Now, the change in bias has negligible effect on drift current (since the

distribution of electrons in the p region is unaffected by the potential change and the electric field in the depletion region remains). This electric field is very large compared to the applied field.

THE SEMICONDUCTOR BIPOLAR JUNCTION TRANSISTOR: STRUCTURE AND OPERATION

• As we discussed in our first lecture, the transistor resulted from the effort to produce a “semiconductor amplifier”, replacing the vacuum tube. It was invented by Bardeen and others at Bell Laboratories.

• Germanium semiconductor material composed the first transistor.

• The bipolar junction transistor (or BJT) relies on the concept of minority carrier transport and a novel means for harnessing this phenomenon.

• The modern “npn” bipolar transistor has this symbol denoting its three terminals (Emitter, Base, and Collector) and its structural form. Note the designation of the emitter.

Figure 22. Bipolar junction transistor showing circuit symbol and corresponding physical structure

• Now, to understand transistor properties, we will consider the electron energy diagram for this npn transistor along the dashed line above.

• First, we have the n, p, n structure:

np

n+

n n+ n+

E B C

E

B

C

np

n+

n n+ n+

E B C

E

B

C


32

Figure 23. Bipolar junction transistor showing physical structure

• Then, we can consider the donor and acceptor density

Figure 24. Bipolar junction transistor showing dopant density distribution.

• Now, this creates two depletion regions – one at the Emitter–Base Junction,

one at the Collector-Base Junction.

Figure 25. . Bipolar junction transistor showing charge density distribution.

• And the electric field and corresponding built-in potential appears:

Figure 26. . Bipolar junction transistor showing field and potential distribution.

• Now, at zero bias, the electron energy diagram and electron density distribution will schematically appear as:

n npn np

ND

-NA

log (ND – NA)

x

ND

-NA

log (ND – NA)

x

ND

log ρ(x)

xNA

W

ND

log ρ(x)

xNA

W

x

Electron Potential Energy (x)

x

E(x)

x

Electron Potential Energy (x)

x

E(x)


33

Figure 27. Bipolar junction transistor showing potential energy and carrier density distribution at zero bias.

• Now, as for the diode, there will be no net current as the electron diffusion currents (from n-type E and C regions to p-type B region) and drift currents will match.

• But, as we apply a positive voltage between Emitter and Base, VBE and larger positive voltage between Collector and Emitter, VCE, we have

Figure 28. Bipolar junction transistor showing potential energy and carrier density distribution at a bias condition appropriate for operation.

• Now, under action of VBE , the electron diffusion current increased exponentially, as for the pn junction diode.

• However, the minority carriers that arrive in the base region may be transported for distances of 1 to 100µ. This is greater than the typical base width!

• Thus, the application of a positive VBE induces an Emitter-to-Base diffusion current. The resulting minority carrier flux may reach the collector, and then be swept into the Base-Collector depletion region and into the collector to join other majority carrier electrons.

• If recombination of minority carriers in the base is low, then nearly all Emitter-to-Base diffusion current is collected.

x

Electron Energy (x)

Wx

Electron Energy (x)

W

JnDiffusion

VBE x

Electron Energy (x)

W

VCE

JnDiffusion

VBE x

Electron Energy (x)

W

VCE


34

• In addition, with appropriate structure, only a small fraction of Emitter-to-Base diffusion current exits via the base contact.

• For normal operation of the NPN transistor, the terminal bias voltages and currents will appear with these polarities and directions and with positive values. As we will see, VBE ≈ 0.7V, VCB >> VBE. Also, iE ≥ iC and iB << iE

Figure 29. Bipolar junction transistor showing bias and current distribution under condition of properly biased electrode potentials in conventional operation.

• Now, a schematic view of electron carrier flux for the NPN transistor will appear:

Figure 30. Bipolar junction transistor showing current distribution under condition of properly biased electrode potentials in conventional operation.

• Note the natural choice of terminology for the Emitter, Base, and Collector structures.

• The BJT may also be structured with PNP layers – producing a complimentary device. The reversal of roles of P and N layers reverses the polarity of forward bias for the Base-Emitter junction. The PNP terminal bias voltages and currents will appear with these polarities and directions

C

iBVBE

VCB

E

iC

iE

B

C

iBVBE

VCB

E

iC

iE

BiBVBE

VCB

E

iC

iE

B

nn+

p n n+ n+

E B C

electron transport

nn+

p n n+ n+

E B C

nn+

p n n+ n+

E B C

electron transport


35

and with positive values. Note the reversal in direction of the emitter terminal “arrow”.

EMITTER, BASE, AND COLLECTOR CURRENT RELATIONSHIPS

• Now, Emitter current leaving the transistor (a current of assumed positive charges) must be equal to the sum of Collector and Base currents. We will use a notation that follows are diode current and voltage notation where a lower case variable letter with uppercase subscript denotes the complete signal that may be decomponsed into large (static) and small signal (time dependent) contributions:

E B Ci i i= +

• And,

/B Ci i β=

• Also,

1E Ci iβ

β+= and ( 1)E Bi iβ= +

• We can define another current gain, the Common Base Current Gain, α. This is

1βα

β≡

+ and 1αβα

=−

• And,

C Ei iα= and (1 )B Ei iα= −

• Finally, we can complete the description of the BJT terminal currents with the Collector current dependence of Base-Emitter Voltage:


36

BE

T

vV

C Si I e=

NPN AND PNP TRANSISTORS

• Note that both NPN and PNP transistors are available in integrated systems and as discrete devices. Their complimentary properties are critical for many amplifier applications.

• The NPN and PNP circuit symbols and typical operating potentials are shown below.

• As discussed, VBE will typically operate in the range of 0.6 – 0.8V. Also, VCB will range from 0 (or small negative values to many tens of Volts or even one kilovolt for a very high voltage device.

• Now, note the reveral of polarities for current and voltage between NPN and PNP devices.

Figure 31. BJT NPN and PNP transistors

C

iBVBE

VCB

E

iC

iE

B

C

iBVBE

VCB

E

iC

iE

BiBVBE

VCB

E

iC

iE

BiBVBC

VEB

C

iE

iC

B

E

iBVBC

VEB

C

iE

iC

B

E


37

TRANSISTOR CURRENT-VOLTAGE CHARACTERISTICS

Figure 32. Circuit used for characterizing Collector current vs Base-Emitter voltage.

Figure 33. BJT NPN Collector current vs Base-Emitter voltage, VBE

0

Qbreakn

Q1

VCE3Vdc

VBE0Vdc


38

Figure 34. BJT NPN Collector current and Base current vs Base-Emitter voltage. Note that β = 100 for this transistor.

Figure 35. Circuit used for characterizing Collector current vs Collector-Emitter voltage for varying Base Currents

IB

0Adc

VCE3Vdc

0

Qbreakn

Q1


39

Figure 36. Collector current vs Collector-Emitter voltage for varying Base Current values of 0, 2, 4, 6, 8, and 10 mA


40

i ee115al outline - uclaicslwebs.ee.ucla.edu/yang/labswiki/images/.../ee115al_introduction.pdf ·...

Documents