HYPER: An Interactive Synthesis Environment for Real Time ApplicationsIntroduction to High Level Synthesis

EE690 Presentation

Sanjeev Gunawardena

March 3rd 1998

OverviewSome explanation of terms Architectures for real time applicationsIntroduction to the Hyper synthesis toolHardware Mapper for HyperExamples: The wavelet filterConclusionAcknowledgements

Some Explanation of TermsHigh level synthesisA task in ASIC development which takes an algorithm, transforms it, assigns operations to suitable units and develops a schedule for the operations that share units. Layout generators (Silicon compilers)A tool used in ASIC development after High level synthesis that deals with the placement of hardware units and the routing of wiring between them.Note: There is often a gap between high level synthesis and layout generators. The synthesis is considered finished when a design has been scheduled, but the layout tool expects a completely specified design.Hardware MapperA tool that interfaces the above two steps. It derives a basic implementation of a design from a high level synthesis data representation and decorates the implementation with necessary details and presents a fully specified design to a layout generator.

Some Explanation of TermsSignal-flowgraph languageA language used to describe high level digital systems that have little explicit control.Examples: Silage, Ptolemy, Comdisco, Mentor Graphics

Hardware Mapper

Some Explanation of TermsControl/data flowgraph

FIR3 block diagram and flowgraph

Some Explanation of TermsHardware Description LanguageThe format in which a design is presented to a layout generator.This is the output generated by the hardware mapper.Examples: VHDL, SDL (the structural description language used by the Larger layout generation tools.

Architectures for Real Time ApplicationsTraditional microprocessor architectureAll operations are time-multiplexed on a single, general purpose ALUControl driven

Hard wired (Data flow driven) architectureEach operation is represented by a separate hardware unitData paths are hard wired to match the algorithmic data flowStructures are heavily pipelined to achieve high data rates, often equaling or exceeding the maximum achievable clock rate.Examples: Systolic arrays, speech recognition, and image processing systems.Programmability is restricted. Results in small controller section.Design process is very cumbersome. Requires many design iterations.The Hyper synthesis environment can derive the data path and controller structure starting from a high-level description.

The HYPER SystemInteractive menu-driven design environment for synthesizing high-performance digital ASICs.Input to HYPER is a Silage description of an algorithm.The Silage description is translated into a control/data flowgraph.Flowgraph represents the same information as the original Silage description, but is easier to manipulate.The flowgraph can be adorned with details not possible with the Silage description.Example: timing, area information

The HYPER SystemThe HYPER Modules

The HYPER SystemThe selection stepAssigns a unit (or group of units) from a hardware library to each type of node in the flowgraphThe library will contain many implementations of the same block each of which are optimized for performance, area, power consumption etc.The transformation phasePerforms algorithmic transformations on the flowgraph to achieve a specific result.Examples:fixed-coefficient multiplications => series of adds and shiftsalgebraic transformationsloop unrollingretiming and pipelining

The HYPER SystemThe estimation stageProvides the designer with estimated resource requirementsnumber of cycles in the critical pathnumber and type of execution units (EXUs)number of registers associated with each EXUnumber of buses connecting EXUs to registersThe assignment/scheduling stepAssigns each flowgraph node to a specific hardware unitDerives the number of needed hardware unitsNOTE: The clock period and sampling rates must be specified prior to scheduling in order to define the number of cycles available to the system.

The HYPER SystemThe hardware mapping (architecture mapping) stagemaps the flowgraph onto the selected hardware units.Generates interconnect informationplaces multiplexers and buffers where neededdefines the FSM and control logicpartitions the datapathOutput of hardware mapper is a group of HDL files.VHDLSDL (Structural Description Language used by LargerIV silicon compiler)After hardware mapping, the system is completely defined.

The Hardware Mapper (Overview)The Hardware Mapper has two main phasesTarget independent phaseextracts information from flowgraph and adds detailsbuffers and multiplexers added and control specifications are derivedTarget specific phasegenerates VHDL or SDL descriptions

ResourcesHigh level synthesis tools decide how all operations of an algorithm are performed.Involves matching a process (e.g. addition) with a pre-designed hardware unit.The hardware units are organized in libraries.An index lists all units and their capable operations.A library may contain more than one unit for the same operation.It is necessary to select the most appropriate unit (based on speed, area or power efficiency).

ResourcesA library data sheet contains other relevant information for the high level synthesis tool.Size, speed or power consumption of unitsConnectivity information of unitsSpecial unit specific information (such as multiple operation units) The data sheet is the only view HYPER has of a library. It uses the data sheet to organize relevant information about hardware units.

ResourcesLibrary access routines

ResourcesLibrary Access Routines

ResourcesA technology file is used by HYPER which describes common characteristics of units. (e.g. supply voltage).

Technology File

Target Independent PhaseFirst phase of the Hardware MapperTranslates flowgraph into an intermediate representation to allow subsequent mapping to different target platforms.

Target Independent Phase - Architecture ModelHYPER architecture model contains:Execution units (EXUs)Register filesCrossbar interconnect network

Target Independent Phase - Architecture ModelRegister filesHave a single input port => one value written at a timeDedicated bus exists between output of register and input of EXU it belongs to.Crossbar interconnect networkprovides connections from any EXU to register file.May form different connections at different times.Implemented by set of dedicated buses, bus drivers and MUXs.Configured by choosing active bus drivers and selected MUX inputs.

HYPERs Refined Architecture ModelResult of merging basic architecture with crossbar implementation.A group of muxes, registers, EXUs and buffers connected only by dedicated buses is known as a cluster.Typically, a cluster has only one EXU.A cluster can have unlimited EXUs.

Target Independent Phase - Register SelectionMapper considers only area when selecting register hardware.The Mapper has four types of registers.Register filescontain one or more registerscan be read/write or read onlycan address one location for reading and one for writing in one clock cycleall registers in the file have the same bit width (at least 1-bit)Single registers with tri-stated outputscan store one value at a timeread/write or read onlycan be both read and written in one clock cycleregister must have a parameterizable bit width (at least 1-bit)can be connected in parallel with other registers of this type to create a register file

Target Independent Phase - Register SelectionSingle Registers without tri-stated outputscan store one value at a timeread/write or read onlycan both be read and written in a clock cyclecannot be connected in parallel with other registers.Can only be used when a HYPER design requires a register file with a single location.Flip-flopssingle-bit standard cell registersD-FFsrising edge triggered

Target Independent Phase - Register Selection ProcessDetermine the size of each Hyper register file, as annotated in the flowgraph.Determine which register or combination offers a better solutionDone on a per-register-file basisSmallest viable solution is chosen as the optimal

Target Independent Phase - Flowgraph TranslationHardware mapper takes a scheduled flowgraph and extracts the necessary information from it.

Target Independent Phase - Bus MergingHardware mapper is capable of minimizing the number of physical buses in a design (optional).Area of bus merged design is 40-60% smaller than non bus merged implementation.Bus merging routinesFanin bus mergingFanout bus mergingGlobal bus mergingBus merging flowchart

Target Independent Phase - Bus MergingFanin bus mergingjoins all input buses of a register file to a single busFanout bus mergingJoins all output buses of an EXU to a single busGlobal bus merging

Target Independent Phase - Bus Merging ExampleSeventh order IIR filter was generated by HyperCritical path - 10 clock cycles (16 clock cycles available time)Implementation2 shifters1 adder1 subtractorResults:

Target Independent Phase - Buffers and MultiplexersAfter bus merging, buffers and muxes are added to the designBuffer selectionNeeded to drive large loads of buses.Can be turned ON or OFF so that one buffer can drive a bus at a given time.Selection routine inserts a simple buffer between EXUs and buses when the bus is driven by one EXU.Selection routine inserts a tri-state buffers when multiple EXUs are driving the same bus.

Target Independent Phase - Buffers and MultiplexersMux selectionAlways placed at the inputs of register files.Mux servers at a bus selector for the register file with which it is associated.Selection routines recognize how many buses are connected to the input of a register file.Examples:register file has one bus connected to input => no mux assignedregister file has two buses connected to input => 2:1 mux assigned

Target Independent Phase - Control GenerationLast step in the target independent phase of hardware mapper

Target Independent Phase - Control GenerationState transition graph generation (from flowgraph)Keeps track of all the states and the operations that must take place during those states.Determines which control signals will be used for control flow (branches, jumps etc)Two types of control flow are supportedsequential flow (does not require any control signals to flow from the datapath to the controller)simple loops (requires that the controller can receive feedback from the datapath to determine when or if to branch.Example:

Examples - The Wavelet FilterContains a high pass and a low pass FIR filter.High and low pass sections share constant coefficients for their 14 taps.

Examples - The Wavelet FilterImplementation using 22 clocks/sample

No bus mergingWith bus mergingBuses:155Muxes:54Buffers:186Registers:5656

Actual layout:7.0 mm2 4.6 mm2

Mapper predicted area:5.2 mm2 3.6 mm2

Examples - The Wavelet FilterImplementation of the wavelet filter without bus merging

Examples - The Wavelet FilterImplementation of the wavelet filter with global bus merging

Examples - The Wavelet Filter (conclusion)The mappers area predictions are too small because the area of control logic and control wiring is not known at the time the prediction is made.Bus merging is clearly desirable when chip area is a concern. Fir this example, a savings of 2.4 mm2 was realized.

ConclusionThe Hyper synthesis environment can be effectively used to derive the data path and controller structure from a high level description (Silage)The Hyper system is comprised of several functional blocks which include selection, transformation, estimation, assignment/scheduling and hardware mapping.The hardware mapper takes the scheduled flowgraph generated by Hyper and maps it to specific hardware units described in a library, generating an HDL output. The hardware mapper is the interface between the high level synthesis tool (Hyper) and the silicon compiler.The real time example shows that the design can be optimized for users specific needs (area, speed, etc)

AcknowledgmentsThe bulk of the material for this presentation was obtained from Ole Bentz (University of California, Berkley) masters thesis titled A Hardware Mapper for the Hyper High Level Synthesis System.http://infopad.eecs.berkeley.edu/~bentz/MastersReport/index.html