ht32f52342/ht32f52352 user manual - holtek€¦ · holtek 32-bit microcontroller with arm®...

Holtek 32-Bit Microcontroller with Arm® Cortex®-M0+ Core

HT32F52342/HT32F52352 User Manual

Revision: V1.30 Date: September 28, 2018

Rev. 1.30 2 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCUHT32F52342/HT32F52352

Table of Contents

Table of Contents1 Introduction ........................................................................................................... 26

Overview .............................................................................................................................. 26Features ............................................................................................................................... 27Device Information ............................................................................................................... 32Block Diagram ..................................................................................................................... 33

2 Document Conventions ....................................................................................... 34

3 System Architecture ............................................................................................. 35Arm® Cortex®-M0+ Processor .............................................................................................. 35Bus Architecture ................................................................................................................... 36Memory Organization .......................................................................................................... 37

Memory Map ................................................................................................................................... 38Embedded Flash Memory ............................................................................................................... 41Embedded SRAM Memory ............................................................................................................. 41AHB Peripherals ............................................................................................................................. 41APB Peripherals ............................................................................................................................. 41

4 Flash Memory Controller (FMC) .......................................................................... 42Introduction .......................................................................................................................... 42Features ............................................................................................................................... 42Functional Descriptions ....................................................................................................... 43

Flash Memory Map ......................................................................................................................... 43Flash Memory Architecture ............................................................................................................. 44Wait State Setting ........................................................................................................................... 44Booting Configuration ..................................................................................................................... 45Page Erase ..................................................................................................................................... 46Mass Erase ..................................................................................................................................... 47Word Programming ......................................................................................................................... 48Option Byte Description .................................................................................................................. 49Page Erase/Program Protection ..................................................................................................... 49Security Protection .......................................................................................................................... 51

Register Map ....................................................................................................................... 52Register Descriptions ........................................................................................................... 53

Flash Target Address Register – TADR .......................................................................................... 53Flash Write Data Register – WRDR ............................................................................................... 54Flash Operation Command Register – OCMR ............................................................................... 55Flash Operation Control Register – OPCR ..................................................................................... 56Flash Operation Interrupt Enable Register – OIER ........................................................................ 57Flash Operation Interrupt and Status Register – OISR .................................................................. 58Flash Page Erase/Program Protection Status Register – PPSR .................................................... 60Flash Security Protection Status Register – CPSR ........................................................................ 61

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Flash Vector Mapping Control Register – VMCR ........................................................................... 62Flash Manufacturer and Device ID Register – MDID ...................................................................... 63Flash Page Number Status Register – PNSR ................................................................................ 64Flash Page Size Status Register – PSSR ...................................................................................... 65Flash Cache & Pre-fetch Control Register – CFCR ........................................................................ 66Custom ID Register n – CIDRn, n = 0 ~ 3 ...................................................................................... 67

5 Power Control Unit (PWRCU) .............................................................................. 68Introduction .......................................................................................................................... 68Features ............................................................................................................................... 69Functional Descriptions ....................................................................................................... 69

Backup Domain .............................................................................................................................. 69VDD Power Domain .......................................................................................................................... 701.5 V Power Domain ....................................................................................................................... 72Operation Modes ............................................................................................................................ 72


Backup Domain Status Register – BAKSR ..................................................................................... 75Backup Domain Control Register – BAKCR ................................................................................... 76Backup Domain Test Register – BAKTEST .................................................................................... 78Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 79Backup Register n – BAKREGn, n = 0 ~ 9 ..................................................................................... 81

6 Clock Control Unit (CKCU) .................................................................................. 82Introduction .......................................................................................................................... 82Features ............................................................................................................................... 84Function Descriptions .......................................................................................................... 84

High Speed External Crystal Oscillator – HSE ............................................................................... 84High Speed Internal RC Oscillator – HSI ........................................................................................ 85Auto Trimming of High Speed Internal RC Oscillator – HSI ............................................................ 85Phase Locked Loop – PLL .............................................................................................................. 87Low Speed External Crystal Oscillator – LSE ................................................................................. 89Low Speed Internal RC Oscillator – LSI ......................................................................................... 89Clock Ready Flag ........................................................................................................................... 89System Clock (CK_SYS) Selection ................................................................................................ 90HSE Clock Monitor ......................................................................................................................... 91Clock Output Capability .................................................................................................................. 91


Global Clock Configuration Register – GCFGR .............................................................................. 93Global Clock Control Register – GCCR .......................................................................................... 95Global Clock Status Register – GCSR ........................................................................................... 97Global Clock Interrupt Register – GCIR .......................................................................................... 98PLL Configuration Register – PLLCFGR ........................................................................................ 99

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PLL Control Register – PLLCR ....................................................................................................... 99AHB Configuration Register – AHBCFGR .................................................................................... 100AHB Clock Control Register – AHBCCR ...................................................................................... 101APB Configuration Register – APBCFGR ..................................................................................... 103APB Clock Control Register 0 – APBCCR0 .................................................................................. 104APB Clock Control Register 1 – APBCCR1 .................................................................................. 106Clock Source Status Register – CKST ......................................................................................... 108APB Peripheral Clock Selection Register 0 – APBPCSR0 ........................................................... 109APB Peripheral Clock Selection Register 1 – APBPCSR1 ............................................................111HSI Control Register – HSICR .......................................................................................................113HSI Auto Trimming Counter Register – HSIATCR .........................................................................114Low Power Control Register – LPCR ............................................................................................115MCU Debug Control Register – MCUDBGCR ...............................................................................116

7 Reset Control Unit (RSTCU) .............................................................................. 119Introduction ........................................................................................................................ 119Functional Descriptions ..................................................................................................... 120

Power On Reset ........................................................................................................................... 120System Reset ............................................................................................................................... 120AHB and APB Unit Reset .............................................................................................................. 120

Register Map ..................................................................................................................... 121Register Descriptions ......................................................................................................... 121

Global Reset Status Register – GRSR ......................................................................................... 121AHB Peripheral Reset Register – AHBPRSTR ............................................................................. 122APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 123APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 125

8 General Purpose I/O (GPIO) ............................................................................... 127Introduction ........................................................................................................................ 127Features ............................................................................................................................. 128Functional Descriptions ..................................................................................................... 128

Default GPIO Pin Configuration .................................................................................................... 128General Purpose I/O – GPIO ........................................................................................................ 128GPIO Locking Mechanism ............................................................................................................ 130


Port A Data Direction Control Register – PADIRCR ..................................................................... 131Port A Input Function Enable Control Register – PAINER ............................................................ 132Port A Pull-Up Selection Register – PAPUR ................................................................................. 133Port A Pull-Down Selection Register – PAPDR ............................................................................ 134Port A Open Drain Selection Register – PAODR .......................................................................... 135Port A Output Current Drive Selection Register – PADRVR ......................................................... 136Port A Lock Register – PALOCKR ................................................................................................ 137Port A Data Input Register – PADINR ........................................................................................... 138

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Port A Output Data Register – PADOUTR .................................................................................... 139Port A Output Set/Reset Control Register – PASRR .................................................................... 140Port A Output Reset Register – PARR .......................................................................................... 141Port B Data Direction Control Register – PBDIRCR ..................................................................... 142Port B Input Function Enable Control Register – PBINER ........................................................... 143Port B Pull-Up Selection Register – PBPUR ................................................................................ 144Port B Pull-Down Selection Register – PBPDR ............................................................................ 145Port B Open Drain Selection Register – PBODR ......................................................................... 146Port B Output Current Drive Selection Register – PBDRVR ........................................................ 147Port B Lock Register – PBLOCKR ................................................................................................ 148Port B Data Input Register – PBDINR .......................................................................................... 149Port B Output Data Register – PBDOUTR ................................................................................... 150Port B Output Set/Reset Control Register – PBSRR .................................................................... 151Port B Output Reset Register – PBRR ......................................................................................... 152Port C Data Direction Control Register – PCDIRCR .................................................................... 153Port C Input Function Enable Control Register – PCINER ........................................................... 154Port C Pull-Up Selection Register – PCPUR ................................................................................ 155Port C Pull-Down Selection Register – PCPDR ........................................................................... 156Port C Open Drain Selection Register – PCODR ......................................................................... 157Port C Output Current Drive Selection Register – PCDRVR ........................................................ 158Port C Lock Register – PCLOCKR ............................................................................................... 159Port C Data Input Register – PCDINR .......................................................................................... 160Port C Output Data Register – PCDOUTR ................................................................................... 161Port C Output Set/Reset Control Register – PCSRR ................................................................... 162Port C Output Reset Register – PCRR ......................................................................................... 163Port D Data Direction Control Register – PDDIRCR .................................................................... 164Port D Input Function Enable Control Register – PDINER ........................................................... 165Port D Pull-Up Selection Register – PDPUR ................................................................................ 166Port D Pull-Down Selection Register – PDPDR ........................................................................... 167Port D Open Drain Selection Register – PDODR ......................................................................... 168Port D Output Current Drive Selection Register – PDDRVR ........................................................ 169Port D Lock Register – PDLOCKR ............................................................................................... 170Port D Data Input Register – PDDINR .......................................................................................... 171Port D Output Data Register – PDDOUTR ................................................................................... 172Port D Output Set/Reset Control Register – PDSRR ................................................................... 173Port D Output Reset Register – PDRR ......................................................................................... 174

9 Alternate Function Input/Output Control Unit (AFIO) ...................................... 175Introduction ........................................................................................................................ 175Features ............................................................................................................................. 176Functional Descriptions ..................................................................................................... 176

External Interrupt Pin Selection .................................................................................................... 176Alternate Function ......................................................................................................................... 177Lock Mechanism .......................................................................................................................... 177

Register Map ..................................................................................................................... 177

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Register Descriptions ......................................................................................................... 178EXTI Source Selection Register 0 – ESSR0 ................................................................................ 178EXTI Source Selection Register 1 – ESSR1 ................................................................................ 179GPIO x Configuration Low Register – GPxCFGLR, x = A, B, C, D ............................................... 180GPIO x Configuration High Register – GPxCFGHR, x = A, B, C, D ............................................. 181

10 Nested Vectored Interrupt Controller (NVIC) .................................................. 182Introduction ........................................................................................................................ 182Features ............................................................................................................................. 183Function Descriptions ........................................................................................................ 184

SysTick Calibration ....................................................................................................................... 184

Register Map ..................................................................................................................... 184

11 External Interrupt/Event Controller (EXTI) ...................................................... 185Introduction ........................................................................................................................ 185Features ............................................................................................................................. 185Function Descriptions ........................................................................................................ 186

Wakeup Event Management......................................................................................................... 186External Interrupt/Event Line Mapping ......................................................................................... 187Interrupt and Debounce ................................................................................................................ 187


EXTI Interrupt Configuration Register n – EXTICFGRn, n = 0 ~ 15 ............................................. 189EXTI Interrupt Control Register – EXTICR ................................................................................... 190EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR ................................................................ 191EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 192EXTI Interrupt Software Set Command Register – EXTISSCR .................................................... 193EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 194EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 195EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG ........................................................... 196

12 Analog to Digital Converter (ADC) .................................................................. 197Introduction ........................................................................................................................ 197Features ............................................................................................................................. 198Function Descriptions ........................................................................................................ 199

ADC Clock Setup .......................................................................................................................... 199Channel Selection ......................................................................................................................... 199Conversion Mode .......................................................................................................................... 199Start Conversion on External Event .............................................................................................. 202Sampling Time Setting .................................................................................................................. 203Data Format .................................................................................................................................. 203Analog Watchdog.......................................................................................................................... 203Interrupts ....................................................................................................................................... 204PDMA Request ............................................................................................................................ 204

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ADC Conversion Control Register – ADCCR ............................................................................... 206ADC Conversion List Register 0 – ADCLST0 ............................................................................... 208ADC Conversion List Register 1 – ADCLST1 ............................................................................... 209ADC Input Sampling Time Register – ADCSTR ........................................................................... 210ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ................................................................211ADC Trigger Control Register – ADCTCR .................................................................................... 212ADC Trigger Source Register – ADCTSR ..................................................................................... 213ADC Watchdog Control Register – ADCWCR .............................................................................. 214ADC Watchdog Threshold Register – ADCTR .............................................................................. 215ADC Interrupt Enable Register – ADCIER .................................................................................... 216ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 217ADC Interrupt Status Register – ADCISR ..................................................................................... 218ADC Interrupt Clear Register – ADCICLR .................................................................................... 219ADC DMA Request Register – ADCDMAR ................................................................................... 220

13 Comparator (CMP) ............................................................................................ 221Introduction ........................................................................................................................ 221Features ............................................................................................................................. 221Function Descriptions ........................................................................................................ 222

Comparator Inputs and Output ..................................................................................................... 222Comparator Voltage Reference .................................................................................................... 222Interrupts and Wakeup.................................................................................................................. 223Power Mode and Hysteresis ......................................................................................................... 224Comparator Write-Protected mechanism ..................................................................................... 224


Comparator Control Register n – CMPCRn, n = 0 or 1 ................................................................ 225Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 or 1 ................................. 227Comparator Interrupt Enable Register n – CMPIERn, n = 0 or 1 ................................................. 228Comparator Transition Flag Register n – CMPTFRn, n = 0 or 1 .................................................. 229

14 General-Purpose Timer (GPTM) ...................................................................... 230Introduction ........................................................................................................................ 230Features ............................................................................................................................. 231Functional Descriptions ..................................................................................................... 232

Counter Mode ............................................................................................................................... 232Clock Controller ............................................................................................................................ 235Trigger Controller .......................................................................................................................... 236Slave Controller ............................................................................................................................ 237Master Controller .......................................................................................................................... 240Channel Controller ........................................................................................................................ 241Input Stage ................................................................................................................................... 244

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Quadrature Decoder ..................................................................................................................... 246Output Stage ................................................................................................................................. 248Update Management .................................................................................................................... 252Single Pulse Mode ........................................................................................................................ 253Asymmetric PWM Mode ............................................................................................................... 255Timer Interconnection ................................................................................................................... 256Trigger ADC Start.......................................................................................................................... 259PDMA Request ............................................................................................................................. 259


Timer Counter Configuration Register – CNTCFR ....................................................................... 261Timer Mode Configuration Register – MDCFR ............................................................................. 263Timer Trigger Configuration Register – TRCFR ............................................................................ 266Timer Counter Register – CTR ..................................................................................................... 267Channel 0 Input Configuration Register – CH0ICFR .................................................................... 268Channel 1 Input Configuration Register – CH1ICFR .................................................................... 270Channel 2 Input Configuration Register – CH2ICFR .................................................................... 272Channel 3 Input Configuration Register – CH3ICFR .................................................................... 274Channel 0 Output Configuration Register – CH0OCFR ............................................................... 276Channel 1 Output Configuration Register – CH1OCFR ............................................................... 278Channel 2 Output Configuration Register – CH2OCFR ............................................................... 280Channel 3 Output Configuration Register – CH3OCFR ............................................................... 282Channel Control Register – CHCTR ............................................................................................. 284Channel Polarity Configuration Register – CHPOLR .................................................................... 285Timer PDMA/Interrupt Control Register – DICTR ......................................................................... 286Timer Event Generator Register – EVGR ..................................................................................... 288Timer Interrupt Status Register – INTSR ...................................................................................... 290Timer Counter Register – CNTR................................................................................................... 293Timer Prescaler Register – PSCR ................................................................................................ 294Timer Counter Reload Register – CRR ........................................................................................ 295Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 296Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 297Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 298Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 299Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 300Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 301Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 302Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 303

15 Basic Function Timer (BFTM) .......................................................................... 304Introduction ........................................................................................................................ 304Features ............................................................................................................................. 304Functional Description ....................................................................................................... 305

Repetitive Mode ............................................................................................................................ 305One Shot Mode ............................................................................................................................. 306

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BFTM Control Register – BFTMCR .............................................................................................. 307BFTM Status Register – BFTMSR ................................................................................................ 308BFTM Counter Register – BFTMCNTR ........................................................................................ 309BFTM Compare Value Register – BFTMCMPR ........................................................................... 310

16 Motor Control Timer (MCTM) ........................................................................... 311Introduction ........................................................................................................................ 311Features ............................................................................................................................. 312Functional Descriptions ..................................................................................................... 313

Counter Mode ............................................................................................................................... 313Clock Controller ............................................................................................................................ 317Trigger Controller .......................................................................................................................... 318Slave Controller ............................................................................................................................ 319Master Controller .......................................................................................................................... 321Channel Controller ........................................................................................................................ 322Input Stage ................................................................................................................................... 325Output Stage ................................................................................................................................. 327Update Management .................................................................................................................... 337Single Pulse Mode ........................................................................................................................ 339Asymmetric PWM Mode ............................................................................................................... 341Timer Interconnection ................................................................................................................... 342Trigger ADC Start.......................................................................................................................... 346Lock Level Table ........................................................................................................................... 346PDMA Request ............................................................................................................................. 347


Timer Counter Configuration Register – CNTCFR ....................................................................... 349Timer Mode Configuration Register – MDCFR ............................................................................. 351Timer Trigger Configuration Register – TRCFR ............................................................................ 354Timer Counter Register – CTR ..................................................................................................... 355Channel 0 Input Configuration Register – CH0ICFR .................................................................... 356Channel 1 Input Configuration Register – CH1ICFR .................................................................... 358Channel 2 Input Configuration Register – CH2ICFR .................................................................... 360Channel 3 Input Configuration Register – CH3ICFR .................................................................... 362Channel 0 Output Configuration Register – CH0OCFR ............................................................... 364Channel 1 Output Configuration Register – CH1OCFR ............................................................... 366Channel 2 Output Configuration Register – CH2OCFR ............................................................... 368Channel 3 Output Configuration Register – CH3OCFR ............................................................... 370Channel Control Register – CHCTR ............................................................................................. 372Channel Polarity Configuration Register – CHPOLR .................................................................... 374Channel Break Configuration Register – CHBRKCFR ................................................................. 376Channel Break Control Register – CHBRKCTR ........................................................................... 377

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Timer PDMA/Interrupt Control Register – DICTR ......................................................................... 379Timer Event Generator Register – EVGR ..................................................................................... 381Timer Interrupt Status Register – INTSR ...................................................................................... 383Timer Counter Register – CNTR................................................................................................... 386Timer Prescaler Register – PSCR ................................................................................................ 387Timer Counter Reload Register – CRR ........................................................................................ 388Timer Repetition Register – REPR ............................................................................................... 389Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 390Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 391Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 392Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 393Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 394Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 395Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 396Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 397

17 Single-Channel Timer (SCTM) ......................................................................... 398Introduction ........................................................................................................................ 398Features ............................................................................................................................. 399Functional Descriptions ..................................................................................................... 399

Counter Mode ............................................................................................................................... 399Clock Controller ............................................................................................................................ 400Trigger Controller .......................................................................................................................... 401Slave Controller ............................................................................................................................ 402Channel Controller ........................................................................................................................ 404Input Stage ................................................................................................................................... 406Output Stage ................................................................................................................................. 407Update Management .................................................................................................................... 409


Timer Counter Configuration Register – CNTCFR ........................................................................411Timer Mode Configuration Register – MDCFR ............................................................................. 412Timer Trigger Configuration Register – TRCFR ............................................................................ 413Timer Counter Register – CTR ..................................................................................................... 414Channel Input Configuration Register – CHICFR ......................................................................... 415Channel Output Configuration Register – CHOCFR .................................................................... 417Channel Control Register – CHCTR ............................................................................................. 418Channel Polarity Configuration Register – CHPOLR .................................................................... 419Timer Interrupt Control Register – DICTR .................................................................................... 420Timer Event Generator Register – EVGR ..................................................................................... 421Timer Interrupt Status Register – INTSR ...................................................................................... 422Timer Counter Register – CNTR................................................................................................... 423Timer Prescaler Register – PSCR ................................................................................................ 424Timer Counter Reload Register – CRR ........................................................................................ 425Channel Capture/Compare Register – CHCCR ........................................................................... 426

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18 Real Time Clock (RTC) ..................................................................................... 427Introduction ........................................................................................................................ 427Features ............................................................................................................................. 427Functional Descriptions ..................................................................................................... 428

RTC Related Register Reset ........................................................................................................ 428Reading RTC Register .................................................................................................................. 428Low Speed Clock Configuration ................................................................................................... 428RTC Counter Operation ................................................................................................................ 429Interrupt and Wakeup Control ....................................................................................................... 429RTCOUT Output Pin Configuration............................................................................................... 430


RTC Counter Register – RTCCNT ................................................................................................ 431RTC Compare Register – RTCCMP ............................................................................................. 432RTC Control Register – RTCCR ................................................................................................... 433RTC Status Register – RTCSR..................................................................................................... 435RTC Interrupt and Wakeup Enable Register – RTCIWEN ............................................................ 436

19 Watchdog Timer (WDT) .................................................................................... 437Introduction ........................................................................................................................ 437Features ............................................................................................................................. 437Functional Description ....................................................................................................... 438Register Map ..................................................................................................................... 440Register Descriptions ......................................................................................................... 440

Watchdog Timer Control Register – WDTCR ............................................................................... 440Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 441Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 442Watchdog Timer Status Register – WDTSR ................................................................................. 443Watchdog Timer Protection Register – WDTPR ........................................................................... 444Watchdog Timer Clock Selection Register – WDTCSR ................................................................ 445

20 Inter-Integrated Circuit (I2C) ............................................................................. 446Introduction ........................................................................................................................ 446Features ............................................................................................................................. 447Functional Descriptions ..................................................................................................... 447

Two Wire Serial Interface .............................................................................................................. 447START and STOP Conditions ....................................................................................................... 447Data Validity .................................................................................................................................. 448Addressing Format ....................................................................................................................... 449Data Transfer and Acknowledge ................................................................................................... 451Clock Synchronization .................................................................................................................. 452Arbitration ..................................................................................................................................... 452General Call Addressing ............................................................................................................... 453

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Bus Error ....................................................................................................................................... 453Address Mask Enable ................................................................................................................... 453Address Snoop ............................................................................................................................. 453Operation Mode ............................................................................................................................ 453Conditions of Holding SCL Line .................................................................................................... 459I2C Timeout Function .................................................................................................................... 460PDMA Interface ............................................................................................................................. 460


I2C Control Register – I2CCR ....................................................................................................... 462I2C Interrupt Enable Register – I2CIER ........................................................................................ 464I2C Address Register – I2CADDR ................................................................................................. 466I2C Status Register – I2CSR ......................................................................................................... 467I2C SCL High Period Generation Register – I2CSHPGR .............................................................. 470I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 471I2C Data Register – I2CDR ........................................................................................................... 472I2C Target Register – I2CTAR ....................................................................................................... 473I2C Address Mask Register – I2CADDMR .................................................................................... 474I2C Address Snoop Register – I2CADDSR ................................................................................... 475I2C Timeout Register – I2CTOUT.................................................................................................. 476

21 Serial Peripheral Interface (SPI) ...................................................................... 477Introduction ........................................................................................................................ 477Features ............................................................................................................................. 478Function Descriptions ........................................................................................................ 478

Master Mode ................................................................................................................................. 478Slave Mode ................................................................................................................................... 478SPI Serial Frame Format .............................................................................................................. 479Status Flags .................................................................................................................................. 483


SPI Control Register 0 – SPICR0 ................................................................................................. 486SPI Control Register 1 – SPICR1 ................................................................................................. 488SPI Interrupt Enable Register – SPIIER ....................................................................................... 490SPI Clock Prescaler Register – SPICPR ...................................................................................... 491SPI Data Register – SPIDR .......................................................................................................... 492SPI Status Register – SPISR ........................................................................................................ 493SPI FIFO Control Register – SPIFCR ........................................................................................... 495SPI FIFO Status Register – SPIFSR ............................................................................................ 496SPI FIFO Time Out Counter Register – SPIFTOCR ..................................................................... 497

22 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 498Introduction ........................................................................................................................ 498Features ............................................................................................................................. 499

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Function Descriptions ........................................................................................................ 500Serial Data Format ........................................................................................................................ 500Baud Rate Generation .................................................................................................................. 501Hardware Flow Control ................................................................................................................. 502IrDA ............................................................................................................................................... 504RS485 Mode ................................................................................................................................. 506Synchronous Master Mode ........................................................................................................... 509Interrupts and Status .....................................................................................................................511PDMA Interface ..............................................................................................................................511


USART Data Register – USRDR .................................................................................................. 512USART Control Register – USRCR .............................................................................................. 513USART FIFO Control Register – USRFCR................................................................................... 515USART Interrupt Enable Register – USRIER ............................................................................... 516USART Status & Interrupt Flag Register – USRSIFR................................................................... 518USART Timing Parameter Register – USRTPR ........................................................................... 520USART IrDA Control Register – IrDACR ...................................................................................... 521USART RS485 Control Register – RS485CR............................................................................... 522USART Synchronous Control Register – SYNCR ........................................................................ 523USART Divider Latch Register – USRDLR................................................................................... 524USART Test Register – USRTSTR ............................................................................................... 525

23 Universal Asynchronous Receiver Transmitter (UART) ................................ 526Introduction ........................................................................................................................ 526Features ............................................................................................................................. 527Function Descriptions ........................................................................................................ 527

Serial Data Format ........................................................................................................................ 527Baud Rate Generation .................................................................................................................. 528Interrupts and Status .................................................................................................................... 529PDMA Interface ............................................................................................................................. 529


UART Data Register – URDR ....................................................................................................... 530UART Control Register – URCR ................................................................................................... 531UART Interrupt Enable Register – URIER .................................................................................... 533UART Status & Interrupt Flag Register – URSIFR ....................................................................... 534UART Divider Latch Register – URDLR ....................................................................................... 536UART Test Register – URTSTR .................................................................................................... 537

24 Smart Card Interface (SCI) ............................................................................... 538Introduction ........................................................................................................................ 538Features ............................................................................................................................. 539Functional Descriptions ..................................................................................................... 539

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Elementary Time Unit Counter ...................................................................................................... 539Guard Time Counter ..................................................................................................................... 541Waiting Time Counter ................................................................................................................... 542Card Clock and Data Selection ..................................................................................................... 543Card Detection ............................................................................................................................. 543SCI Data Transfer Mode ............................................................................................................... 544Interrupt Generator ....................................................................................................................... 546PDMA Interface ............................................................................................................................. 547


SCI Control Register – CR ............................................................................................................ 548SCI Status Register – SR ............................................................................................................. 550SCI Contact Control Register – CCR ............................................................................................ 552SCI Elementary Time Unit Register – ETUR ................................................................................ 553SCI Guard Time Register – GTR .................................................................................................. 554SCI Waiting Time Register – WTR................................................................................................ 555SCI Interrupt Enable Register – IER ............................................................................................. 556SCI Interrupt Pending Register – IPR ........................................................................................... 558SCI Transmit Buffer – TXB............................................................................................................ 560SCI Receive Buffer – RXB ............................................................................................................ 560SCI Prescaler Register – PSCR ................................................................................................... 561

25 USB Device Controller (USB) .......................................................................... 562Introduction ........................................................................................................................ 562Features ............................................................................................................................. 562Functional Descriptions ..................................................................................................... 563

Endpoints ...................................................................................................................................... 563EP-SRAM ..................................................................................................................................... 563Serial Interface Engine – SIE ........................................................................................................ 564Double-Buffering ........................................................................................................................... 564Suspend Mode and Wake-up ....................................................................................................... 566Remote Wake-up .......................................................................................................................... 566


USB Control and Status Register – USBCSR .............................................................................. 568USB Interrupt Enable Register – USBIER .................................................................................... 570USB Interrupt Status Register – USBISR ..................................................................................... 571USB Frame Count Register – USBFCR ....................................................................................... 573USB Device Address Register – USBDEVA ................................................................................. 574USB Endpoint 0 Control and Status Register – USBEP0CSR ..................................................... 575USB Endpoint 0 Interrupt Enable Register – USBEP0IER ........................................................... 576USB Endpoint 0 Interrupt Status Register – USBEP0ISR ............................................................ 578USB Endpoint 0 Transfer Count Register – USBEP0TCR ........................................................... 579USB Endpoint 0 Configuration Register – USBEP0CFGR ........................................................... 580

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USB Endpoint 1 ~ 3 Control and Status Register – USBEPnCSR, n = 1 ~ 3 ............................... 581USB Endpoint 1 ~ 3 Interrupt Enable Register – USBEPnIER, n = 1 ~ 3 ..................................... 582USB Endpoint 1 ~ 3 Interrupt Status Register – USBEPnISR, n = 1 ~ 3 ...................................... 583USB Endpoint 1 ~ 3 Transfer Count Register – USBEPnTCR, n = 1 ~ 3 ..................................... 584USB Endpoint 1 ~ 3 Configuration Register – USBEPnCFGR, n = 1 ~ 3 ..................................... 585USB Endpoint 4 ~ 7 Control and Status Register – USBEPnCSR, n = 4 ~ 7 ............................... 586USB Endpoint 4 ~ 7 Interrupt Enable Register – USBEPnIER, n = 4 ~ 7 ..................................... 589USB Endpoint 4 ~ 7 Interrupt Status Register – USBEPnISR, n = 4 ~ 7 ...................................... 590USB Endpoint 4 ~ 7 Transfer Count Register – USBEPnTCR, n = 4 ~ 7 ..................................... 591USB Endpoint 4 ~ 7 Configuration Register – USBEPnCFGR, n = 4 ~ 7 ..................................... 592

26 Peripheral Direct Memory Access (PDMA) ..................................................... 593Introduction ........................................................................................................................ 593Features ............................................................................................................................. 593Functional Description ....................................................................................................... 594

AHB Master .................................................................................................................................. 594PDMA Channel ............................................................................................................................. 594PDMA Request Mapping .............................................................................................................. 594Channel transfer ........................................................................................................................... 596Channel Priority ............................................................................................................................ 596Transfer Request .......................................................................................................................... 597Address Mode ............................................................................................................................... 597Auto-Reload .................................................................................................................................. 597Transfer Interrupt .......................................................................................................................... 598


PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 5 .................................................... 600PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 5 .................................. 602PDMA Channel n Destination Address Register – PDMACHnDADR, n=0~5 ............................... 603PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 5 ......................................... 604PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n=0~5 ............................. 605PDMA Interrupt Status Register – PDMAISR ............................................................................... 606PDMA Interrupt Status Clear Register – PDMAISCR ................................................................... 607PDMA Interrupt Enable Register – PDMAIER .............................................................................. 609

27 Extend Bus Interface (EBI) ............................................................................... 610Introduction ........................................................................................................................ 610Features ............................................................................................................................. 610Function Descriptions ........................................................................................................ 611

Non-multiplexed 8-bit Data 8-bit Address Mode ........................................................................... 612Non-multiplexed 16-bit Data N-bit Address Mode ......................................................................... 613Multiplexed 16-bit Data, 16-bit Address Mode .............................................................................. 614Multiplexed 8-bit Data, 20-bit Address Mode ................................................................................ 615Write Buffer and EBI Status .......................................................................................................... 616

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Table of Contents

Bus Turn-around and Idle Cycles ................................................................................................. 616AHB Transaction Width Conversion ............................................................................................. 617EBI Bank Access .......................................................................................................................... 619PDMA Request ............................................................................................................................. 620


EBI Control Register – EBICR ...................................................................................................... 620EBI Status Register – EBISR ........................................................................................................ 622EBI Address Timing Register – EBIATR ....................................................................................... 623EBI Read Timing Register – EBIRTR ........................................................................................... 624EBI Write Timing Register – EBIWTR ........................................................................................... 625EBI Parity Register – EBIPR ......................................................................................................... 626

28 Inter-IC Sound (I2S) ........................................................................................... 627Introduction ........................................................................................................................ 627Features ............................................................................................................................. 627Functional Description ....................................................................................................... 628

I2S Master and Slave Mode .......................................................................................................... 628I2S Clock Rate Generator ............................................................................................................. 629I2S Interface Format ...................................................................................................................... 631FIFO Control and Arrangement .................................................................................................... 638PDMA and Interrupt ...................................................................................................................... 639


I2S Control Register – I2SCR ........................................................................................................ 640I2S Interrupt Enable Register – I2SIER ......................................................................................... 642I2S Clock Divider Register – I2SCDR ........................................................................................... 643I2S TX Data Register – I2STXDR ................................................................................................. 644I2S RX Data Register – I2SRXDR ................................................................................................. 644I2S FIFO Control Register – I2SFCR ............................................................................................ 645I2S Status Register – I2SSR ......................................................................................................... 646I2S Rate Counter Value Register – I2SRCNTR ............................................................................ 648

29 Cyclic Redundancy Check (CRC) .................................................................... 649Introduction ....................................................................................................................... 649Features ............................................................................................................................. 650Function Descriptions ........................................................................................................ 650

CRC Computation ......................................................................................................................... 650Byte and Bit Reversal for CRC Computation ................................................................................ 650CRC with PDMA ........................................................................................................................... 651


CRC Control Register – CRCCR .................................................................................................. 652CRC Seed Register – CRCSDR ................................................................................................... 653

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Table of Contents

CRC Checksum Register – CRCCSR .......................................................................................... 654CRC Data Register – CRCDR ...................................................................................................... 655

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List of Tables

List of TablesTable 1. Series Features and Peripheral List .......................................................................................... 32Table 2. Document Conventions ............................................................................................................. 34Table 3. Register Map ............................................................................................................................. 39Table 4. Flash Memory and Option Byte ................................................................................................. 44Table 5. Relationship Between Wait State Cycle and HCLK .................................................................. 44Table 6. Booting Modes .......................................................................................................................... 45Table 7. Option Byte Memory Map ......................................................................................................... 49Table 8. Access Permission of Protected Main Flash Page .................................................................... 50Table 9. Access Permission When Security Protection is Enabled ......................................................... 51Table 10. FMC Register Map .................................................................................................................. 52Table 11. Operation Mode Definitions ..................................................................................................... 72Table 12. Enter/Exit Power Saving Modes .............................................................................................. 73Table 13. Power Status After System Reset ........................................................................................... 74Table 14. PWRCU Register Map ............................................................................................................ 74Table 15. Output Divider2 Value Mapping............................................................................................... 88Table 16. Feedback Divider2 Value Mapping.......................................................................................... 88Table 17. CKOUT Clock Source ............................................................................................................. 91Table 18. CKCU Register Map ............................................................................................................... 92Table 19. RSTCU Register Map ........................................................................................................... 121Table 20. AFIO, GPIO and IO Pad Control Signal True Table............................................................... 129Table 21. GPIO Register Map ............................................................................................................... 130Table 22. AFIO Selection for Peripheral Map Example ......................................................................... 177Table 23. AFIO Register Map ................................................................................................................ 177Table 24. Exception Types .................................................................................................................... 182Table 25. NVIC Register Map ..................................................................

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