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High-speed Serial Interface Lect. 10 – Charge-pump PLL 2013-1 High-Speed Circuits and Systems Lab., Yonsei University 1

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Page 1: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

High-speed Serial Interface

Lect. 10 – Charge-pump PLL

2013-1High-Speed Circuits and Systems Lab., Yonsei University1

Page 2: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

PLL Review

2013-1High-Speed Circuits and Systems Lab., Yonsei University2

Clock Signal Generation Frequency Synthesis

Page 3: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

PLL Review

2013-1High-Speed Circuits and Systems Lab., Yonsei University3

Frequency Demodulation

(FM signal)

(Recovered message)

(PLL output)

Page 4: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Limitation of PLL with PD– Narrow linear phase detection range

2013-1High-Speed Circuits and Systems Lab., Yonsei University4

AB

VPD

A

BVPD

A

BVPD

Page 5: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Phase Frequency Detector (PFD)

2013-1High-Speed Circuits and Systems Lab., Yonsei University5

Vin

Vout

UP

DOWN

UP-DOWN

2π-2π

Duration of (UP-DOWN)

Page 6: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

PFD Implementation

2013-1High-Speed Circuits and Systems Lab., Yonsei University6

Subtraction and integrationSubtraction Integration

Subtraction

Integration

Voltage modeusing OP amplifiers

Current modeusing charge pump

Page 7: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Charge Pump PLL

2013-1High-Speed Circuits and Systems Lab., Yonsei University7

Page 8: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Charge Pump Transfer Function

– Charging (or discharging) time for phase error during one period= 2– Integrated voltage = = 2– Transfer function = 2

2013-1High-Speed Circuits and Systems Lab., Yonsei University8

Transfer function of PD + Charge pump + LF

Page 9: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Charge pump

2013-1High-Speed Circuits and Systems Lab., Yonsei University9

21

1 1( )2 CP VCOH s I K

s C

( )H s

( )H s

0 dB

-180

ω

ω

-40dB/decade

Page 10: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Feedback Stability• Negative feedback system

– It is unstable when denominator of closed loop transfer function is equal to 0.

– Criteria for unstable condition is;

2013-1High-Speed Circuits and Systems Lab., Yonsei University10

H(s)

G(s)

= ( )1 + ( ) ( )

Adder+

-

= −1 0 @∠ − 180°

Page 11: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Charge-pump PLL

2013-1High-Speed Circuits and Systems Lab., Yonsei University11M

Open loop gain:

12

1

11( )2 CP VCO

sRCH s I Ks C

( )G s

( )G s

0 dB

-180

ω

ω

-90

-40dB/decade

-20dB/decade

zero

Large ripple during transient

Page 12: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Charge-pump PLL

2013-1High-Speed Circuits and Systems Lab., Yonsei University12

Ripple reduction with small C2 (≈C1/10)Simplification as 2nd-order system

Page 13: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Stability• Transfer function for charge-pump PLL

– : damping factor– : natural frequency

2013-1High-Speed Circuits and Systems Lab., Yonsei University13

= (2 + )/ + 2 + = 2 2 , = 2

Page 14: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Stability

– Poles of transfer function:

– Location of poles are defined by

2013-1High-Speed Circuits and Systems Lab., Yonsei University14

+ 2 + = 0= − ± − 1Location of poles Damping

=0 2 imaginary Undamped (oscillation)

0< <1 2 complex conjugate Underdamped

=1 2 real (same) Critically damped

>1 2 real Overdamped

Page 15: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Step Response• x-axis is normalized;

2013-1High-Speed Circuits and Systems Lab., Yonsei University15

Undamped

OverdampedCriticallyDamped

Page 16: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Frequency Response

– Transfer function vs. various damping factor.– Large peaking for small damping factor

2013-1High-Speed Circuits and Systems Lab., Yonsei University16

Page 17: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Stability

2013-1High-Speed Circuits and Systems Lab., Yonsei University17

• Damping factor– Use of = 0.707 is popular even though it is underdamped

because settling time is shorter than = 1

Page 18: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Phase Margin– Open-loop transfer

= 2 ( + 1 )– Gain vs. Phase Margin?

– Zero location vs. Phase Margin

– Damping Factor vs. Phase Margin?

2013-1High-Speed Circuits and Systems Lab., Yonsei University18

Page 19: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Phase Margin• Phase margin enhances as loop gain increases

2013-1High-Speed Circuits and Systems Lab., Yonsei University19

Magnitude [dB]

Phase [deg]

-90

-180

Page 20: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Phase Margin • Phase margin enhances as zero freq. decreases

2013-1High-Speed Circuits and Systems Lab., Yonsei University20

Magnitude [dB]

Phase [deg]

-90

-180

Page 21: High-speed Serial Interface - High-Speed Circuits ...tera.yonsei.ac.kr/class/2013_1_2/lecture/Lect10_CPPLL.pdf · PLL Review 2 High-Speed Circuits and Systems Lab., Yonsei University

Phase Margin

2013-1High-Speed Circuits and Systems Lab., Yonsei University21

• Damping factor vs. phase margin– It is OK to use one of both for stability analysis.

http://www.scribd.com/doc/57004703/86/Relationship-Between-Damping-Ratio-and-Phase-Margin