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High Speed Equalizer Circuits ECE1352 Jenkin Wong November 28, 2003

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High Speed Equalizer Circuits. ECE1352 Jenkin Wong November 28, 2003. Agenda. Background Why Equalize? Equalization for 100Base-TX Ethernet Introduction Define Problem Proposed Solution. Background. Why Equalize? Non-ideal Channel In frequency domain – Amplitude and Phase attenuation - PowerPoint PPT Presentation

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Page 1: High Speed Equalizer Circuits

High Speed Equalizer Circuits

ECE1352Jenkin Wong

November 28, 2003

Page 2: High Speed Equalizer Circuits

Jenkin Wong 2

AgendaBackground

• Why Equalize?

Equalization for 100Base-TX Ethernet• Introduction• Define Problem• Proposed Solution

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Jenkin Wong 3

Why Equalize?• Non-ideal Channel• In frequency domain – Amplitude and Phase

attenuation• In time domain – Intersymbol Interference (ISI)

Background

Maximize Data Rate on a Bandlimited Channel

Page 4: High Speed Equalizer Circuits

Jenkin Wong 4

Equalizer for 10Mb/s and 100Mb/s EthernetBackground

• A CMOS Transceiver for 10Mb/s and 100Mb/s Ethernet by Everitt, Parker, Hurst, Nack and Konda

• Uses an Adaptive Equalization scheme implemented in the analog domain

• MLT3 Encodingfor 100Base-TX

Focus on 100Base-TX

Page 5: High Speed Equalizer Circuits

Jenkin Wong 5

Equalization for 100Base-TX

What are the problems?• Attenuation vs. Frequency characteristic of the

CAT-5 Cable, At 62.5MHz, 18dB loss after 100m of cable

• Baseline Wander Worst case is when 56 consecutive zeros

(max), followed by 4 ones• DC Insertion Loss of Cable

2dB for 100m cable

f

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Equalization for 100Base-TXSolution

• Adaptive Equalizer - Analog Implementation Combines a coarse ADC and digital algorithms

based on signal statistics to achieve equalization

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Equalization for 100Base-TX

Equalization Control

• Over-equalized – overshoot at each symbol transition

• Under-equalized – Too much high frequency Attenuation

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Equalization for 100Base-TX

Gain and DC wander Control

• Too much Gain – always +1 error• Not enough Gain – always –1 error

Page 9: High Speed Equalizer Circuits

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Equalization for 100Base-TXAdaptive Equalizer Block

• Implementation issues Position of Zero and Poles Range of Gm Controlling R

22

132

2

)1(

])(1[*

RCs

KsgmgmgmgmR

VinVout

Digital Logic will Tune Gm1 and Gm2

Page 10: High Speed Equalizer Circuits

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Equalization for 100Base-TX

Transconductance Cell

• Used in both the tuning PLL and the LPF• Bias for the LPF Gm cell is copied from the

Gm-C cells inside PLL• R = 1/Gm

Page 11: High Speed Equalizer Circuits

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Equalization for 100Base-TX

Wander Cancellation Cell

• Digital logic controls the charge pump changing the current Icp

• Voltage I*R is add to cancel the DC wander

Page 12: High Speed Equalizer Circuits

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Equalization for 100Base-TX

Equalization performance at 100m

The Eye is opened

Page 13: High Speed Equalizer Circuits

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Equalization for 100Base-TX

Performance Summary

Equalization works!

Page 14: High Speed Equalizer Circuits

Jenkin Wong 14

Equalization for 100Base-TX

Conclusion• Crash course on Equalization• Analog Implementation of a High Speed adaptive

equalization scheme for 100 Base-TX• Equalization is one of the many keys to reliable

high speed digital data communication• ECE1392 – IC for Digital Communication• Q&A

Page 15: High Speed Equalizer Circuits

Jenkin Wong 15

Equalization for 100Base-TX

References• A CMOS Transceiver for 10Mb/s and 100Mb/s

Ethernet by Everitt, Parker, Hurst, Nack and Konda

• A Mixed-Signal Tuning Loop for Variable Bandpass Filter, A Final Report by Wee-Guan Ben Tan, EE, University of California

• Slides from Research Overview in Analog IC Design by Prof. Phillip E. Allen, ECE Georgia Institute of Technology

• Notes from Analog versus DSP for Disk Drive by Prof. Richard Spencer, University of California