high speed edge detection inside a sequential block in verilog
DESCRIPTION
A Verilog code to detect edges of a pulse inside a sequential blockTRANSCRIPT
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High Speed edge detection inside a Sequential Block in Verilog
Detecting a PWM signal using Verilog
Positive Level Detection Block:-
always@(posedge clk)begin
if(pwm_in == 1)begin
count_h = count_h +1;
pwm_flag_h = 0;
end
else begin
if(pwm_flag_h == 0)
temp_h = count_h;
pwm_flag_h =1;
count_h = 0;
end
end
When the pwm_in is high the count_h reg keeps on counting ( at clk freq ) since the pwm_in is high each
time this block is repeated the program flow is confined to the if block. When the pwm_in is low the else block
keeps repeating until the pwm_in is high. Since the pwm_flag_h is equal to zero when the pwm_in was high
previously the following snippet of code
if(pwm_flag_h == 0)
temp_h = count_h;
executes only once inside the else block ( i.e when pwm_in == 0 ). In the next iteration of the always block
when the pwm_in is zero the above statement wont execute since the pwm_flag_h was set to high. Hence the
negedge of the pwm_in signal has been detected.
Negative Level Detection Block:- always@(posedge clk)begin
if(pwm_in == 0)begin
count_l = count_l +1;
pwm_flag_l = 0;
end
else begin
if(pwm_flag_l == 0)
temp_l = count_l;
pwm_flag_l =1;
count_l = 0;
end
end
The same algorithm applies for the posedge detection inside the negative level detection block.
In both the blocks the total count value for the positive level and negative level has been assigned to the temp_h
and temp_l at negedge and posedge of the pwm_in.
Finally the temp_h and temp_l values are assigned to the output ports of the module at the end of the pwm_in
pulse ( i.e at negedge ).
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Full Verilog Code for PWM:- module pwm_detect( input clk,
input pwm_in,
output reg [0:31] high_count,
output reg [0:31] low_count
);
reg [0:31] count_h = 0, count_l = 0, temp_h =0, temp_l =0 ;
reg pwm_flag_h = 0, pwm_flag_l = 0;
//Block to detect posedge
always@(posedge clk)begin
if(pwm_in == 1)begin
count_h = count_h +1;
pwm_flag_h = 0;
end
else begin
if(pwm_flag_h == 0)
temp_h = count_h;
pwm_flag_h =1;
count_h = 0;
end
end
//Block to detect negedge
always@(posedge clk)begin
if(pwm_in == 0)begin
count_l = count_l +1;
pwm_flag_l = 0;
end
else begin
if(pwm_flag_l == 0)
temp_l = count_l;
pwm_flag_l =1;
count_l = 0;
end
end
//Output the data on negedge
always@(negedge pwm_in)begin
low_count = temp_l;
high_count = temp_h;
end
endmodule