high-speed digital russ mchugh - keysight · how to characterize and debug high speed digital links...

High-Speed Digital

Design and Verification

How to characterize and debug high speed digital links on

your physical prototype?

What part of your design is eating up your Eye margins?

Russ McHugh

Senior Application Engineer,

High Speed Digital and

Analog Test

Signal Integrity Challenges

EQ

+

-

Connecto

r

TP0 TP1

Channel

Connecto

r

EQ

+

-

TP2 TP3 TP4

TXp

TXn RXn

RXp

Tx Rx

Inter-Symbol Interference (ISI)

Probing Effects

Impedance Mismatches and Reflections

Cross Talk

Loss

Methods to Compensate for Measurements

Calibration

Mathematical Signal Processing

De-embedding/Embedding Techniques

2

Separating out the Transmitter Effects

TX RX Channel

Capturing an eye diagram

The easiest way to get an overall idea of the quality of the serial signal

Created relative to a clock (explicit, recovered)

Eye Diagram is the superposition of all the bit transitions

Clock Recovery settings greatly effect the shape of the eye

101 Sequence 011 Sequence Overlay of all combinations

What represents “good enough”?

The Eye Mask

The eye-mask is the common industry approach to measure the eye opening

Failures usually occur at mask corners

• But what is cause of failure?

Violating USB FS 12Mb/s Eye Diagram Good Displayport Eye Diagram

Types of Jitter

Jitter

Deterministic

(DJ) Random (RJ)

Correlated with Data

(DDJ)

Uncorrelated with

Data

Duty Cycle

Distortion

(DCD)

Inter Symbol

Interference

(ISI)

Periodic

(PJ)

Aperiodic

(ABUJ)

Skewed

Gaussian

Uncorrelated with

Data

Xtalk

Non Linear

CR

Events

Thermal

Shot

1/f

Burst

Tr, Tf D BW Limits

Reflections

Clocks

Bounded UnBounded

Tx

Threshold

Measuring Jitter: Bit Error Ratio (BER) Testing

The only way to directly

measure Total Jitter is

with a Bit Error Ratio

(BER) test.

Sample at various points

along unit interval,

directly measure BER at

each point. Plot “bathtub”

curve.

TB

0

0.5

10-3

10-6

10-9

10-12

BE

R

Gaussian

Tails

0.5TB

Eye Opening at

BER=10-12

Can be slow depending on the

data rate

TJ(BER) = UI – W W

/UI

Time Interval Error

Waveform transitions deviate from expected transition time

Generate Time Interval Error (TIE) by measuring transitions versus

reference clock

(a) Clock Reference

(b) Source Waveform

time

time

time

voltage

tim

e e

rror

0

0

(c) Time Interval Error (TIE)

measurement

threshold

Measures total

jitter of the

acquisition. The

more transitions

you measure,

the greater TIE

will become.

Dual Dirac Model – Total Jitter

L

R

L

R

JPP

DJ

)([ Lx )]( Rx +

2

2

2exp

x

2

2

2

2

2

)(exp

2

)(exp

RL xx

Total Jitter

7

DJ

BER n

1x10-8

1x10-10

1x10-12

1x10-14

6.47

5.73

7.13

7.74

RJpp / 2 n =

( = RJrms)

TJ(BER) = UI – W

TJ(BER) = 2n*RJrms + DJ

TJ can be measured directly

using a BER test

OR

TJ can be calculated using RJ

and DJ in the Dual Dirac

model

Tail Fit

-30 -20 -10 0 10 20 300

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1Total Jitter Histogram

RJ/PJ/ABUJ Histogram

Problem

The spectral method lumps ABUJ

in with RJ and greatly

overestimates TJ.

Solution

1. Perform Gaussian Tail fit on

RJ/PJ/ABUJ Histogram to get

RJrms directly

2. Spectral fit gives

(RJ+ABUJ)rms & PJrms

3. Subtract RJ rms to get

ABUJrms

RJrms

EZJIT Plus – Advanced Jitter Decomposition

Easy to use

wizard guides

you through

jitter

measurement

setup

Fully compatible

with Infiniium

Software such

as Equalization,

PrecisionProbe,

and InfiniiSim

Customizable

jitter views

Jitter Measurement Demonstration

Why is vertical noise floor important ?

Let’s consider theoretical signals with Zero jitter and fixed voltage noise

with three different edge speeds and crossing a Threshold at 50%

1)Voltage noise translates directly to Timing uncertainty (Jitter)

2)Higher Vertical Noise Floor translates to higher Timing uncertainty

3)At constant amplitude noise floor, slower edge speed translates to higher

timing uncertainty

EZJIT Complete – Vertical Noise Decomposition

Vertical slice of

real time eye

allows for noise

decomposition

using the same

concepts and

algorithms as

timing jitter

Analyze One

level, Zero

level, or both

Vertical Noise Measurement Demonstration

Separating out the Channel Effects

TX RX Channel

Analyzing a serial Link

TX RX Channel

Clean Source Signal Closed Eye

Received Signal Channel

Frequency Response

We are going to analyze a 12Gb/s Link

Channel will be 9 Inch FR4 PCB

AGILENT SI Seminar 2012

by Pascal GRISON

Eye & Jitter Break Down Analysis on TX output

Transmitter 12Gb/s

Intrinsic Jitter Analysis

33GHz 80GSa/s Scope

RJ: 500fs (RMS)

PJ: 740fs

DCD: 660fs

ISI: 10.52ps


by Pascal GRISON


by Pascal GRISON

Eye Diagram on TX output and Channel Output

Depending on Link

Target Data rate &

Transmission Channel

Losses

Even with Perfect TX Eye

Opening…

You may end up with a

completely closed

at Receiver Side

Why is the RX Eye

Closed? ISI Jitter!

Does that mean that this

link will never Work?

Well it Depends….


by Pascal GRISON

What is Inter-Symbol Interference?

ISI Jitter is coming from Signal Distortions in Transmission Channel


by Pascal GRISON

Scope can Emulate Receiver EQUALIZATION

Modern SerDes are incorporating

Reciever Equalization

Using Oscilloscope Equalization

we can emulate most DUT RX EQ

configurations:

• Feed Forward Equalizer

Continuous Time Linear Equalizer

• Decision Feedback Equalizer


by Pascal GRISON

Emulate Receiver EQUALIZATION on Oscilloscope

From almost Zero RX

Eye Opening

with no TX De-

Emphasis and

No RX EQ

RX Eye Opening of

132mV X 65ps

Was achieved with

EQUALIZATION

You MUST Emulate your RX Equalization in Oscilloscope to Analyze True RX Eye Diagram

Commonly Encountered Insertion Losses

Typical Insertion Loss Through FR4

100MHz …….. 2 dB/m (20%/m)

500MHz …….. 4 dB/m (37%/m)

1GHz ………… 7 dB/m (55%/m)

5GHz ………… 25 dB/m (94%/m)

10GHz ……….. 45 dB/m or 1.14 dB/in (99%/m)

Typical Insertion Loss Through SMA

100MHz …….. 0.25 dB/m (2.8%/m)

1GHz ………… 0.8 dB/m (8.8%/m)

5GHz ………... 2 dB/m (20%/m)

10GHz ………. 3 dB/m (29%/m)

20GHz ………. 5 dB/m (44%/m)

Loss increases exponentially with frequency.

Non-idealities you could ignore at <1GHz now severely erode design margins

Same Measurement Setup, VERY Different Results

Uncorrected

Corrected

PHY PHY

De-embedding – Loss Compensation or Gain

Function (De-convolve)

25

Tx Rx

Con

ne

cto

r

Con

ne

cto

r

Channel

• Compensate for Probing and Fixture

Loss – Add Margin to Transmitter

Characterization

• PCI Express 2, SATA, and Custom

• Compliance Requirement for Gen 2 S4P

De-embedding the DDR2 BGA Probe

26

Probe at BGA

Probe at VIA

De-embed Probe

RT BGA = 390 ps

RT VIA = 183 ps

RT De-embed = 175 ps

27

PHY PHY

Embedding – Loss Function (Convolve)

28

Tx Rx

Con

ne

cto

r

Con

ne

cto

r

Channel

Virtual Probe and De-

emphasis/Equalization

• Simulate Channel Loss on Signal

Measured at Tx

• Simulate Equalization/De-emphasis at

Rx

Virtual Probe

Tx

Signal

Rx

Equalization

TP1

TP2

TP3

TP2 TP3

Connector Pin Rx

TP1

Channel.s4p+

conn.s4p+package.s4p

Separating out the Receiver Effects

TX RX Channel

How do we ensure ‘Error Free’ operation?

How can we specify to the transmitter plus channel design the quality of

the signal that the receiver needs?

Answer - We need to measure the Receiver’s tolerance to jitter.

30

Characteristic eye closure by sinusoidal Jitter

BER Scan

Eye Diagram

31


by Pascal GRISON

Receiver Jitter Tolerance

with Loopback

Rx latch

DLL

Rx

PLL

ISI

Channel

Receiver RX Data

Customers are using J-BERT to characterize SERDES receiver susceptibility

to ISI, Random Jitter, Periodic Jitter, and BUJ

Tx latch

Tx

DLL

Transmitter

DUT SerDes in

Loopback Mode

TX Data

JBERT up to 28Gb/s PRBS Generation

with Calibrated Jitter insertion

and integrated adjustable ISI channel

JBERT Real time Error Detector allow

thorough BER Analysis

32

Error detector supports 8B/10B encoded data, and

can deal with re-timed data and filler symbols

RX Testing with asycronous devices

(SER / FER Support)

Product under test

Receiver

Loop-

back

Device function

FF

CDR

EQ

Transmitter

Elastic

buffer

Clock

Data-out with fBERT

D+ D- D+ F+ F+ D+ D- D+

Expected data with fproduct

Loopback data with fproduct

and new disparity

Re-timed data with fProduct

D+ D- D+ F+ D+ D- D+

D- D+ D- F- D- D+ D-

D D D D D D

Clock

CDR

Rx Compliance and Jitter Tolerance

Testing

34

Summary

• TX characterization is frequently captured with eye diagrams.

• The Dual Dirac model allows us to extrapolate jitter measurements to low BER rates.

• Amplitude noise can contribute to random jitter.

• ISI is a dominant source of eye closure at high data rates.

• De-embedding and virtual probing can correct for fixture and provide measurements at inaccessible locations.

• Equalizers are a key feature of receivers.

• Receiver jitter tolerance testing is becoming a requirement.

• Asynchronous systems require the BER error detector to handle filler symbols.

Page 36

Questions

Page 37

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