high-performance high- sonos-type flash memory

2354 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 9, SEPTEMBER 2008

High-Performance High-k Y2O3

SONOS-Type Flash MemoryTung-Ming Pan and Wen-Wei Yeh

Abstract—In this paper, we propose a novel high-k Y2O3

poly-Si–oxide–nitride–oxide–silicon (SONOS)-type flash memory.The structural and morphological features of Y2O3 films werestudied using atomic force microscopy, transmission electronmicroscopy, and X-ray photoelectron spectroscopy. These high-kY2O3 SONOS-type memories exhibited large threshold voltageshifting (memory window of 1.9–4.33 V), almost negligible readand gate disturb (threshold voltage shift of ∼2-mV operation atVG = 3 V and VD = 4 V and ∼4-mV operation at VG = 8 V,respectively), excellent data retention (charge loss of ∼4% mea-sured time up to 104 s and at room temperature, expected ∼22%charge loss for ten years at 125 C), and superior endurance char-acteristics (program/erase cycles up to 105) because of the higherprobability for trapping charge carriers. These Y2O3 films appearto be a very promising charge trapping layer for high-densitytwo-bit nonvolatile flash memory applications.

Index Terms—Charge trapping layer, data retention, drain dis-turb, endurance, gate disturb, memory window, poly-Si–oxide–nitride–oxide–silicon (SONOS), read disturb, Y-silicate, Y2O3.

I. INTRODUCTION

THE CONVENTIONAL floating gate (FG) memory em-ployed poly-Si film as a charge-storage layer that can

achieve high-density integration and good program/erase (P/E)speed; however, there are concerns regarding the capability toscale down the tunneling dielectric thickness [1]. When thetunneling oxide thickness is below 10 nm, the storage charge inthe FG loses easily because a large number of defects form inthe tunneling oxide after repeated P/E cycles or through directtunneling of the current [2]. The poly-Si–oxide–nitride–oxide–silicon (SONOS)-type structure memories, including nitridememories and nanocrystal memories, recently have been in-vestigated as an approach to solve the issue of scaling FGmemory [3], [4]. Due to their spatially isolated deep-leveltraps, SONOS memories exhibit better charge retention thanFG memories that have a bitcell tunneling oxide thickness lessthan 10 nm. Consequently, a single defect in the tunnelingoxide will not lead to the discharge of the memory cell [2].However, many concerning issues are still presented forSONOS memories. For nitride memories, erase saturation andvertical stored charge migration [5], [6] are the major draw-

Manuscript received January 23, 2008; revised June 3, 2008. This workwas supported in part by the National Science Council (NSC) of China underContract NSC-96-2221-E-182-045 and in part by the National Nano DeviceLaboratories under Contract NDL-95S-C123. The review of this paper wasarranged by Editor M. J. Kumar.

The authors are with the Department of Electronics Engineering, ChangGung University, Taoyuan 333, Taiwan, R.O.C. (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2008.927401

Fig. 1. Schematic representation of flash memory cell structure using theY2O3 as a charge trapping layer.

backs, whereas for nanocrystal memories, good enough chargemaintaining capability of the discrete storage nodes and theformation of nanocrystals with constant size, high density, anduniform distribution are the extremely challenging issues [7].Therefore, it is very difficult to promote the programming speedand data retention simultaneously. In recent years, differentONO processing technologies [8], [9] and alternating trappingmaterials [10]–[14] have been explored to improve the dataretention. For example, a combination of SiO2 and Al2O3 [15]and amorphous carbon on SiO2 [16] to replace the traditionalSiO2 have been investigated because of their well-controlledgrowth of Si quantum dots or Si nanocrystals leading to highthreshold voltage shift and good reliability behavior. In addi-tion, the use of an Al2O3 trapping layer and HfAlO3 to replaceSi3N4 has attracted much attention for the application in thenext-generation nonvolatile memories because their materialbandgaps and high trap densities exhibit fast P/E speed andsuperior data retention [17], [18].

The rare earth oxides such as yttrium oxide (Y2O3) areattractive candidate for nanocrystal or trapping layer memorybased on thermodynamic stability consideration, a high dielec-tric constant of 18, a high conduction band offset over 2 eV,and a low lattice mismatch with silicon [19]–[21]. On the otherhand, excellent electrical properties were reported for Y2O3

films grown on a Si substrate by physical vapor deposition [19].In this paper, we propose a novel high-k Y2O3 SONOS-typememory device for application in high-density two-bit non-volatile flash memory. Memory cell prepared under the Y2O3

film as a charge trapping layer exhibits excellent characteristics,

0018-9383/$25.00 © 2008 IEEE

PAN AND YEH: HIGH-PERFORMANCE HIGH-k Y2O3 SONOS-TYPE FLASH MEMORY 2355

Fig. 2. AFM images of Y2O3 layer annealed at 700 C in (a) O2, (b) N2O,or (c) N2 gas.

such as a large memory window, negligible read and gatedisturb, long retention time, and good endurance.

II. EXPERIMENTAL SETUP

Fig. 1 shows the schematic diagram of the fabricated deviceused in this paper. NMOSFETs were fabricated on 150-mmp-type (100)-oriented Si wafers with a resistivity of 5–10 Ω · cm.

Fig. 3. TEM cross-sectional images of the Y2O3 trapping layer memoriesafter annealing at 700 C in (a) O2, (b) N2O, or (c) N2 gas.

First, after a standard RCA clean, a 2-nm tunneling oxide wasthermally grown at 950 C in a vertical furnace system. An∼3-nm Y2O3 film was deposited on the tunneling oxide bysputtering with yttrium target in a system with a base pressureof 9.8 × 10−3 mbar at room temperature (RT). The sputteringprocess was performed in diluted O2(Ar/O2 = 25/5) ambientsputtering power of 100 W, at sputter rates of about 2.5 Å/min.Rapid thermal process anneal of 700 C in N2, O2, or N2O am-bient for 30 s was then performed to transform Y2O3 film intoY-silicate charge trapping layer. The film composition and mor-phology were analyzed using X-ray photoelectron spectroscopy(XPS), transmission electron microscopy (TEM), and atomicforce image microscopy (AFM). Next, an ∼15-nm blockingoxide was grown through plasma-enhanced chemical vapor de-position, followed by a nitrogen densification process at 900 Cfor 30 s to reduce the number of defects. Subsequently, poly-Sideposition, gate pattering, source/drain implanting, and the re-maining standard CMOS processes were completed to fabricatethe high-k Y2O3 SONOS-type memory device.


Fig. 4. XPS spectra of (a) Y 3d and (b) O 1s in Y2O3 films after annealing at 700 C in three different gases.

The surface morphology and roughness of each film wereinvestigated using AFM. The Y-silicate layer and the qualityof interfaces were studied by TEM. The bonding structures ofthe Y2O3 dielectrics were determined using XPS. All cells de-scribed in this paper have dimensions of width/length (W/L) =10/2 µm. The electrical properties of high-k Y2O3 SONOS-type memory devices were measured using an HP 4156Csemiconductor parameter analyzer.

III. RESULTS AND DISCUSSION

A. Structural Analysis of the Films Using AFM,TEM, and XPS

Fig. 2 shows the AFM surface morphologies of Y2O3 di-electric films prepared under the three various annealing gases.The surface of the Y2O3 film after O2 annealing exhibited asmall surface roughness (Rrms = 1.48 Å), whereas annealingperformed under N2 had a roughened surface (Rrms = 1.65 Å).These features indicate that the diffusion of oxygen toward theY2O3/oxide interface during O2 annealing reduces the surfaceroughness of the Y2O3 film, thereby enhancing the formationof amorphous silica layer. The increase in surface roughnesscaused by nanocrystals present in the metal oxide film seems toarise from the formation of silicate layer containing Y and O.

Fig. 3 shows the cross-sectional TEM images of theY2O3 trapping layer memories after annealing at 700 Cin three various gases. As can be seen from the TEM image,the Y2O3 SONOS-type memory annealed in O2 gas has athicker tunnel oxide of 24 Å than other annealing gases. Thisindicates that diffusion of oxygen reacted with Si atom to form aSiO2 film at the Y2O3/oxide interface during high-temperatureannealing, thereby enhancing the formation of SiO2 layer [22].In addition, it is found that a high-k Y2O3 SONOS-type mem-ory after N2 annealing exhibits a thin tunnel oxide of 21 Å,suggesting the reduction of SiO2 layer.

Fig. 4 shows the Y 3d and O 1s peaks of Y2O3 layersprepared under the three different gases and annealed at 700 C.The sample annealed in O2 gas shifts the peak position to ahigher binding energy by approximately 1.5 eV compared withthe Y2O3 peak reference position (Y 3d5/2 and 3d3/2 at 156.8and 158.8 eV, respectively) [19], whereas the shifting of the

Y 3d peak to a higher binding energy for dielectric film pre-pared under the N2 ambient is about 0.9 eV. There was a suddenchange in the Y bonding status owing to the large formation ofY-silicate [20]. The change in O 1s peak position and intensityafter RTA treatment supports an explanation of the chemicalbonding state. The O 1s spectra of the Y2O3 films annealedin three various gases are shown in Fig. 4(b) with their propertwo-peak curve-fitting lines. In two sets of spectra, each fittingpeak is assumed to follow the general shape of the Gaussianfunction. The O 1s peak of the film after annealing under N2

at 700 C illustrates two components: a large intensity peak atlower binding energy (531 eV) is attributed to silicate with aslightly high Y concentration, and a small intensity at higherbinding energy (533 eV) is assigned to SiO2 [19]. Moreover,the weak intensity of O 1s peak corresponding to Y-silicate andthe strong and wide intensity of O 1s peak corresponding toSiO2 for the sample annealed in N2O gas are compared withthe N2 gas. This suggests that N2O rapidly decomposes in thegas phase to N2 and O [23], and then, the reaction of O with Siatom forming a SiO2 film at the Y2O3/oxide interface enhancesthe formation of SiO2 layer, consistent with Fig. 3(b). On theother hand, the sample after O2 annealing exhibits a strong peakat 531.4 eV (corresponding to silicate with a slightly low Yconcentration) and a weak peak at 533 eV for O 1s. The SiO2

layer grew monotonically at the film/oxide interface because ofthe diffusion of oxygen toward the interface.

B. Electrical Characterization

For the flash memory cell operation, channel-hot-electron(CHE) and band-to-band hot-hole (BTBHH) injections for theprogramming and erasing have been employed, respectively.Fig. 5(a) shows program characteristics of the Y2O3 SONOS-type memory devices after annealing at 700 C in three differentgases as a function of pulsewidth. Both source and substrateterminals were grounded. The Vth shift is defined as the changeof threshold voltage of a device between the programmed andthe erased states. For the condition of VD = 6 V and VG =8 V at 1 ms, it is obvious that a high-k Y2O3 SONOS-typememory after N2 annealing exhibits a larger memory windowof 2.43 V compared with other annealing gases. This is due tomore electrons trapped in the Y2O3 layer. Moreover, the erase


Fig. 5. (a) Program and (b) erase curves (programming condition at VD = 8 V and VG = 8 V for 1 ms) of high-k Y2O3 SOMOS memory devices afterannealing at 700 C in three different gases.

characteristics of the Y2O3 SONOS-type memories preparedunder the three various gases and annealed at 700 C as afunction of pulsewidth are shown in Fig. 5(b). It is clear thatexcellent erase speed of approximately 1 ms can be obtainedfor Y-silicate trapping storage layer memory prepared at a N2

ambient annealing and operated at VD = 8 V and VG = −3 V.The conduction band offset is 2.3 eV between Y2O3 and p-Sisubstrate [24]. During the programming state, the electrons inthe substrate obtain energy from the applied gate and drainvoltages. If the energy is exceeding the potential barrier of3.1 eV, the hot electrons will cross the tunneling oxide to theY2O3 and be trapped. Thus, this leads to a larger Vth value.In contrast, for high-k Y2O3 SONOS-type memory with theerasing state, the generation of hot hole in the substrate wasapplied by a negative gate voltage and a positive drain voltage.If the hot hole in the substrate achieves enough energy to crossthe energy barrier of 4.6 eV, it can reach the Y2O3 film andcause a lower Vth value.

When a cell is read, the gate and drain voltages are appliedto the selected row and column, respectively. This conditioncan lead to two kinds of read disturb on a cell in the erasedstate. If we considered the cell that is read, an unwantedprogramming due to CHE injection can take place, if the drainvoltage is not low enough. In addition, all the cells in theerased state on the selected row are subjected to a low-voltagestress which can induce a tunneling current from the channelto the charge storage layer, resulting again in an unwantedprogramming. Fig. 6 shows the read disturb characteristics ofthe Y2O3 SONOS-type memory devices after three differentannealing gases in the erasing state. In read-disturb-inducederase-state threshold voltage instability measurement, the gateand drain biases were applied, and the source was grounded.A Y-silicate charge trapping layer memory annealed in O2 gasexhibited a larger Vth shift, whereas the sample prepared underthe N2 and N2O gases was almost no read disturb (∼2 mV),after stressing for 103 s. This indicates that almost no currentfor Y2O3 film annealed in N2 and N2O gases will be presentin the tunnel oxide when voltages of 3 and 4 V are appliedto the gate and drain electrodes, respectively. This larger Vth

shift is due to the existence of yttrium silicate with a low Yconcentration.

Two types of program disturbs must be taken into account:the row and column disturbs. Gate disturbs are due to gate

Fig. 6. Read disturb characteristics of the Y2O3 trapping layer memories afterannealing at 700 C in three different gases.

stress applied to a cell while programming other cells on thesame wordline. If a high voltage is applied to the selectedrow, all the other cells of that row must withstand the gatestress without losing their data. Fig. 7(a) shows the gate disturbcharacteristics in the erasing state for high-k Y2O3 SONOS-type memories prepared under the three various annealinggases. We found almost no threshold voltage shift (∼4 mV)for Y2O3 dielectric annealed in N2 and N2O gases under thefollowing conditions: VG = 8 V and VD = VS = 0 V stressedfor 103 s. This suggests that an almost negligible current willbe present in the tunnel oxide when a voltage of 8 V is appliedto the gate electrode. Fig. 7(b) shows the programming draindisturbs in the programming state of Y-silicate flash memorydevices prepared under the three various annealing gases. It isclearly seen that Y-silicate memory after O2 annealing exhibitsa large threshold voltage shift of 0.44 V, stressing for 103 s.This result suggests that holes can be generated via impactionization in the drain and then injected in the Y2O3 witha shallow trap energy level. Moreover, we observed that asmall programming drain disturb margin exists (∆Vth < 0.2 V)for high-k Y2O3 SONOS-type memory device prepared underthe N2 annealing, after programming at a value of VD of8 V after stressing for 103 s. Under the programming drainstress (VD = 8 V), programmed cells can lose charge by holeband-to-band or Fowler–Nordheim tunneling from the drain tothe Y2O3.


Fig. 7. (a) Gate disturb and (b) drain disturb characteristics of the Y2O3 charge trapping layer memories after annealing at 700 C in three different gases.

Fig. 8. Endurance characteristics of the Y2O3 trapping storage layer memo-ries after annealing at 700 C in three different gases.

Fig. 9. Charge loss curves of the high-k Y2O3 SONOS-type memory devicesafter annealing at 700 C in three various gases, measured at RT and 125 C.

Fig. 8 shows the endurance characteristics of the Y2O3

trapping layer memory cell after annealing in three variousgases. The programming and erasing conditions were VG =6 V, VD = 8 V for 1 ms and VG = −3 V, VD = 8 V for 1 ms,respectively. The values of Vth in the program and erase statesfor Y-silicate charge trapping layer memory prepared at a N2

gas annealing did not increase significantly up to 105 P/Ecycles. The trapped electrons from the Y-silicate layer are al-most removed during the erase process. In contrast, the memorywindow underwent a narrowing after 105 cyclic operations forhigh-k Y2O3 SONOS-type memory after O2 annealing. Forprogramming state, a few electrons in the trapping layer are

Fig. 10. Drain current versus gate voltage curves of the two-bit Y2O3 chargetrapping layer memories annealed at 700 C in N2 ambient; forward andreverse reads for programmed bit-1 and bit-2, respectively.

TABLE IOPERATION PRINCIPLES AND BIAS CONDITIONS UTILIZED DURING THE

OPERATION OF THE HIGH-k Y2O3 SONOS-TYPE FLASH MEMORY CELL

AFTER ANNEALING AT 700 C IN N2 AMBIENT

produced during the CHE injection, reducing the value of Vth

due to the presence of a low Y content in the yttrium silicatelayer. For erasing state, this can be explained by the fact thatthe distribution of trapped electrons programmed by CHE doesnot completely match the holes generated by BTBHH andthat each P/E cycle will leave a few electrons in the trappinglayer. Thus, the holes injected during erasing may not havecompletely annihilated all of the trapped electrons, leading


TABLE IICOMPARISON OF ELECTRICAL CHARACTERISTICS OF THE NONVOLATILE MEMORY DEVICE FABRICATED

WITH Y2O3, Si3N4, nc-Si, HfO2, AND ZrO2 AS NANOCRYSTAL OR CHARGE TRAPPING LAYER

to some negative charge remaining in the Y-silicate chargetrapping layer to result in the slight increase in the value of Vth.

Fig. 9 shows the charge loss curves of the high-k Y2O3

SONOS-type memory devices using three different annealinggases, prepared under the fresh cells and measured at 25 Cand 125 C. An yttrium silicate trapping storage layer memoryannealed in N2 gas exhibits a small charge loss of about 4%measured time up to 104 s and at 25 C. This result is attributedto the combined effects of the tight embrace of the Y2O3

film by the sufficiently deep trap energy level. Although thethickness of tunnel oxide is 2 nm, almost no significant lateralor vertical charge migration occurs. Hence, the device exhibitsgood retention characteristics for charge storage. Furthermore,it is found that the Y-silicate charge trapping layer memory afterO2 annealing exhibits a more significant charge loss of about10% during the program state. This suggests that formationof Y-silicate layer with a slightly low Y concentration canenhance the probability of electron tunneling from the Y2O3

to the channel. At the temperature at 125 C, SONOS-typememory prepared under a Y2O3 trapping layer and annealedin N2 gas has a lower charge loss of ∼22% during the programstate compared with other annealing gases. This indicates thatthe yttrium silicate charge trapping layer can tightly catch thetunneling electrons. Therefore, the trapped electrons by thehigh-k Y2O3 SONOS-type memory devices cannot easily es-cape, and the exhibited charge loss percentage is low.

Fig. 10 shows the feasibility of two-bit cell withCHE/BTBHH programming/erasing and forward/reverse read-ing for Y2O3 trapping layer memories annealed at 700 C inN2 ambient. From the Ids–Vgs curves, it is evident that we canemploy forward and reverse reads to detect the informationstored in the programmed bit-1 and bit-2 [25], [26], respec-tively. The read operation was achieved using a reverse-readscheme. “Forward read” and “reverse read” after drain sideare charged by applying VG = 6 V and VD = 8 V for 1 ms,depicting an increase in Vth of about 3.3 and 6 V, respectively.

The ∆Vth difference between the forward and reverse Vth wasfound to be 2.7 V, indicating two-bit operation in a single cell.Table I summarizes the bias conditions for the two-bit operationof high-k Y2O3 SONOS-type memory devices.

The electrical characteristics of the nonvolatile memory de-vice parameters are summarized in Table II, where the datafrom devices using Si3N4 [27], nc-Si [28], HfO2 [29], andZrO2 [11] as nanocrystal or charge trapping layer are shown forcomparison. First, our Y2O3 trapping layer memories exhibitlarger memory windows compared with the other materialsdue to the large trap density of the high-k dielectric materials.Second, with respect to the P/E voltage, we obtained a low-voltage operation because we used a thinner Y2O3 film as acharge trapping layer. Finally, we observed good retention withno vertical or lateral migration as a result of sufficiently deeptrap energy level in the Y2O3 film.

IV. CONCLUSION

In this paper, we propose a novel and simple technique forhigh-density high-k Y2O3 SONOS-type memory fabricated onthe tunneling oxide using sputtering. The AFM, TEM, andXPS analyses indicate the formation of Y-silicate layer afterannealing at 700 C in N2 ambient. It has shown the electricalcharacteristics in terms of 2.43-V memory window, almostnegligible read and gate disturb, long charge retention timedue to deep trap level in the high-k Y2O3 layer, and excellentendurance up to 105 cycles with no memory window narrowing.This high-k Y2O3 film is suitable for the two-bit operation andhas great potential for replacing the ONO stack in conventionalSONOS-type flash memories.

ACKNOWLEDGMENT

The authors would like to thank the staff of the NationalNano Device Laboratory for their technical help.


REFERENCES

[1] J. J. Lee, X. Wang, W. Bai, N. Lu, and D. L. Kwong, “Theoreticaland experimental investigation of Si nanocrystal memory device withHfO2 high-k tunneling dielectric,” IEEE Trans. Electron Devices, vol. 50,no. 10, pp. 2067–2072, Oct. 2003.

[2] B. D. Salvo, C. Gerardi, R. V. Schaijk, S. A. Lombardo, D. Corso,C. Plantamura, T. Serafino, G. Ammendola, M. V. Duuren, P. Goarin,W. Y. Mei, K. V. D. Jeugd, H. Baron, M. Gely, P. Mur, and S. Deleonibus,“Performance and reliability features of advanced nonvolatile memoriesbased on discrete traps (silicon nanocrystals, SONOS),” IEEE Trans.Device Mater. Rel., vol. 4, no. 3, pp. 377–389, Sep. 2004.

[3] R. Ohba, N. Sugiyama, K. Uchida, J. Koga, and A. Toriumi, “NonvolatileSi quantum memory with self-aligned doubly-stacked dots,” IEEE Trans.Electron Devices, vol. 49, no. 8, pp. 1392–1398, Aug. 2002.

[4] J. H. Kim and J. B. Choi, “Long-term electron leakage mechanismsthrough ONO interpoly dielectric in stacked-gate EEPROM cells,” IEEETrans. Electron Devices, vol. 51, no. 12, pp. 2048–2053, Dec. 2004.

[5] P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T. J. King,“FinFET SONOS flash memory for embedded applications,” in IEDMTech. Dig., 2003, pp. 609–613.

[6] T. Sugizaki, M. Kobayashi, M. Ishidao, H. Minakata, M. Yamaguchi,Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bitSONOS type flash memory using a high-k charge trapping layer,” in VLSISymp. Tech. Dig., 2003, pp. 27–28.

[7] M. L. Ostraat, J. W. De Blauwe, M. L. Green, L. D. Bell,M. L. Brongersma, J. Casperson, R. C. Flagan, and H. A. Atwater,“Synthesis and characterization of aerosol silicon nanocrystal nonvolatilefloating-gate memory devices,” Appl. Phys. Lett., vol. 79, no. 3, pp. 433–435, Jul. 2001.

[8] T. S. Chen, K. H. Wu, H. Chung, and C. H. Kao, “Performance improve-ment of SONOS memory by bandgap engineer of charge trapping layer,”IEEE Electron Device Lett., vol. 25, no. 4, pp. 205–207, Apr. 2002.

[9] R. Ohba, Y. Mitani, N. Sugiyama, and S. Fujita, “25 nm planar bulkSONOS-type memory with double tunnel junction,” in IEDM Tech. Dig.,2006, pp. 37.1.1–37.1.4.

[10] H. C. You, T. H. Hsu, F. H. Ko, J. W. Huang, W. L. Yang, and T. F. Lei,“SONOS-type flash memory using an HfO2 as a charge trapping layerdeposited by the sol–gel spin-coating method,” IEEE Electron DeviceLett., vol. 27, no. 8, pp. 653–655, Aug. 2006.

[11] T. H. Hsu, H. C. You, F. H. Ko, and T. F. Lei, “PolySi–SiO2–ZrO2–SiO2–Si flash memory incorporating a sol–gel-derived ZrO2 charge trap-ping layer,” J. Electrochem. Soc., vol. 153, no. 11, pp. G934–G937,Nov. 2006.

[12] Y. Q. Wang, D. Y. Gao, W. S. Hwang, C. Shen, G. Zhang, G. Samudra,Y. C. Yeo, and W. J. Yoo, “Fast erasing and highly reliable MONOStype memory with HfO2 high-k trapping layer and Si3N4/SiO2 tunnelingstack,” in IEDM Tech. Dig., 2006, pp. 37.4.1–37.4.4.

[13] H. Sunamura, T. Ikarashi, A. Morioka, S. Kotsuji, M. Oshida, N. Ikarashi,S. Fujieda, and H. Watanabe, “Suppression of lateral charge redistributionusing advanced impurity trap memory for improving high temperatureretention,” in IEDM Tech. Dig., 2006, pp. 37.5.1–37.5.4.

[14] T. C. Chang, S. T. Yan, P. T. Liu, C. W. Chen, S. H. Lin, andS. M. Sze, “A novel approach of fabricating germanium nanocrystals fornonvolatile memory application,” Electrochem. Solid-State Lett., vol. 7,no. 1, pp. G17–G19, Jan. 2004.

[15] A. Fernandes, B. DeSalvo, T. Baron, J. F. Damlencourt, A. M. Papon,D. Lafond, D. Mariolle, B. Guillaumot, P. Besson, G. Ghibaudo,G. Pananakakis, F. Martin, and S. Haukka, “Memory characteristics ofSi quantum dot devices with SiO2/ALD Al2O3 tunneling dielectrics,” inIEDM Tech. Dig., 2001, pp. 155–158.

[16] S. J. Baik and K. S. Lim, “Characteristics of silicon nanocrystal floatinggate memory using amorphous carbon/SiO2 tunnel barrier,” Appl. Phys.Lett., vol. 81, no. 27, pp. 5186–5188, Dec. 2002.

[17] T. Sugizaki, M. Kobayashi, H. Minakata, M. Yamaguchi, Y. Tamura,Y. Sugiyama, H. Tanaka, T. Nakanishi, and Y. Nara, “New 2-bit/TrMONOS type flash memory using Al2O3 as charge trapping layer,”in Proc. IEEE Non-Volatile Semicond. Memory Workshop, Feb. 2003,pp. 60–61.

[18] J. H. Chen, Y. Q. Wang, W. J. Yoo, Y. C. Yeo, G. Samudra, D. S. Chan,A. Y. Du, and D. L. Kwong, “Nonvolatile flash memory device using Genanocrystals embedded in HfAlO high-k tunneling and control oxides:Device fabrication and electrical performance,” IEEE Trans. ElectronDevices, vol. 51, no. 11, pp. 1840–1848, Nov. 2004.

[19] J. J. Chambers and G. N. Parsons, “Physical and electrical characterizationof ultrathin yttrium silicate insulators on silicon,” J. Appl. Phys., vol. 90,no. 2, pp. 918–933, Jul. 2001.

[20] T. M. Pan and J. D. Lee, “Physical and electrical properties ofyttrium oxide gate dielectrics on Si substrate with NH3 plasma treatment,”J. Electrochem. Soc., vol. 154, no. 8, pp. H698–H703, Aug. 2007.

[21] J. Kwo, M. Hong, A. R. Kortan, K. L. Queeney, Y. J. Chabal,R. L. Opila, Jr., D. A. Muller, S. N. G. Chu, B. J. Sapjeta, T. S. Lay,J. P. Mannaerts, T. Boone, H. W. Krautter, J. J. Krajewski, A. M. Sergnt,and J. M. Rosamilia, “Properties of high k gate dielectrics Gd2O3 andY2O3 for Si,” J. Appl. Phys., vol. 89, no. 7, pp. 3920–3927, Apr. 2001.

[22] B. Lee, T. Moon, T. G. Kim, D. K. Choi, and B. Park, “Dielectric relax-ation of atomic-layer-deposited HfO2 thin films from 1 kHz to 5 GHz,”Appl. Phys. Lett., vol. 87, no. 1, p. 012 901, Jul. 2005.

[23] E. P. Gusev, H.-C. Lu, E. L. Garfunkel, T. Gustafsson, and M. L. Green,“Growth and characterization of ultrathin nitrided silicon oxide films,”IBM J. Res. Develop., vol. 43, no. 3, pp. 265–286, May 1999.

[24] M. H. Cho, D. H. Ko, K. Jeong, S. W. Whangbo, C. N. Whang,S. C. Choi, and S. J. Cho, “Growth stage of crystalline Y2O3 film onSi (100) grown by an ionized cluster beam deposition,” J. Appl. Phys.,vol. 85, no. 5, pp. 2909–2914, Mar. 1999.

[25] C. C. Yeh, T. Wang, W. J. Tsai, T. C. Lu, M. S. Chen, Y. Y. Liao,W. Ting, Y. H. J. Ku, and C. Y. Lu, “A novel PHINES flash memory cellwith low power program/erase, small pitch, two-bits-per-cell for data stor-age applications,” IEEE Trans. Electron Devices, vol. 52, no. 4, pp. 541–546, Apr. 2005.

[26] S. K. Samanta1, P. K. Singh, W. J. Yoo, G. Samudra, Y. C. Yeo,L. K. Bera, and N. Balasubramanian, “Enhancement of memory windowin short channel non-volatile memory devices using double layer tungstennanocrystals,” in IEDM Tech. Dig., 2005, pp. 7.5.1–7.5.4.

[27] S. K. Sung, I. H. Park, C. J. Lee, Y. K. Lee, J. D. Lee, B. G. Park,S. D. Chae, and C. W. Kim, “Fabrication and program/erase charac-teristics of 30-nm SONOS nonvolatile memory devices,” IEEE Trans.Nanotech., vol. 2, no. 4, pp. 258–264, Dec. 2003.

[28] C. Y. Ng, T. P. Chen, M. Yang, J. B. Yang, L. Ding, C. M. Li, A. Du, andA. Trigg, “Impact of programming mechanisms on the performance andreliability of nonvolatile memory devices based on Si nanocrystals,” IEEETrans. Electron Devices, vol. 53, no. 4, pp. 663–667, Apr. 2006.

[29] Y. H. Lin, C. H. Chien, C. T. Lin, C. Y. Chang, and T. F. Lei, “Novel two-bit HfO2 nanocrystal nonvolatile flash memory,” IEEE Trans. ElectronDevices, vol. 53, no. 4, pp. 782–788, Apr. 2006.

Tung-Ming Pan was born in Taipei, Taiwan, R.O.C.,in 1970. He received the B.S. degree from the De-partment of Electronics Engineering, National ChiaoTung University (NCTU), Hsinchu, Taiwan, in 1997,and the Ph.D. degree from the Institute of Electron-ics, NCTU, in 2001.

From 2000 to 2002, he was a Principal Engineerwith the LOGIC Development Department, Tech-nology and Process Development Division, UMC,where he was engaged in developing the 0.1-µmdevice and process. Then, he transferred to the Reli-

ability Engineering, Quality and Reliability Assurance Division, where he wasresponsible for the 0.1-µm device reliability and quality. In 2002, he was aSenior Engineer with the Mixed Signal Team, ELANSAT Technologies Inc.,where he was engaged in designing high-speed analog-to-digital and digital-to-analog converters. Since 2004, he has been a member of the Faculty withthe Department of Electronics Engineering, Chang Gung University, Taoyuan,Taiwan, where he was an Assistant Professor and where he has been anAssociate Professor since 2006. He has published more than 60 technical papersand is the author or coauthor of six patents. His current research areas focus onthe high-k gate dielectric materials, flash memories, thin-film transistors, pHion sensitive field-effect transistors, and device reliability for ultralarge-scaleintegrated devices.

Dr. Pan received the first prize of the Lam Ph.D. Dissertation Award in 2001.

Wen-Wei Yeh was born in Taoyuan, Taiwan, R.O.C.,on August 29, 1983. He received the B.S. degree inelectronics engineering from Feng Chia University,Taichung, Taiwan, in 2005, and the M.S. degree inelectronics engineering from Chang Gung Univer-sity, Taoyuan, in 2007.

He is currently with the Department of Electron-ics Engineering, Chang Gung University. His re-search interests include engineering and physics ofadvanced memory devices (particularly, nanocrys-tal based), high-k dielectric materials for CMOS

devices, and reliability analysis.

high-performance high- sonos-type flash memory

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