high-k/metal gate technology - tokyo institute of … th pa u np pu amcm bk cf es fm md no lr...

High-k/Metal Gate Technology

January 9, 2008 @IIT-Bombay

Hiroshi Iwai

Frontier Reseach Center,Tokyo Institute of Technology

1

B. H. Lee et al., materials today (2006)

Direct tunneling Limit of SiO2Leakage currentLimit of SiO2

High-k startsLeakage current Limit of High-k

MOSFET gate oxide thickness trend

EOT: Equivalent Oxide Thickness to that of SiO22

VLSI text book written 1979 predict that 0.25 micro-meter would be the limit because of direct-tunneling current through the very thin-gate oxide.

VLSI textbookFinally, there appears to be a fundamental limit 10 of approximately quarter micron channel length, where certain physical effects such as the tunneling through the gate oxide andfluctuations in the positions of impurities in the depletion layers begin to make the devices of smaller dimension unworkable.

Direct tunneling leakage was found to be OK! In 1994!

Lg = 10 µm Lg = 5 µm Lg = 1.0 µm Lg = 0.1µm

Gate electrode

Si substrateGate oxide Direct tunneling leakage

current start to flow when the thickness is 3 nm.

MOSFETs with 1.5 nm gate oxide

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.03

0.02

0.01

0.00

0.01

-0.40.0 0.5 1.0 1.5

Vd (V)

Id (m

A / μ

m)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

1.6

1.2

0.8

0.4

0.0

-0.40.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.4

0.3

0.2

0.1

0.0

-0.10.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.08

0.06

0.04

0.02

0.00

-0.020.0 0.5 1.0 1.5

Vd (V)

Scaling Limit in MOSFET

10-5

10-4

10-3

10-2

10-1

100

101

102

1970 1990 2010 2030 2050Year

MPU LgJunction depthGate oxide thickness

Direct-tunneling limit in SiO2

ITRS Roadmap(at introduction)

Wave length of electron

Distance between Si atomsSize

(µm

), V

olta

ge(V

)

Min. V supply

10 nm3 nm

0.3 nm

ULTIMATELIMIT

10-5

10-4

10-3

10-2

10-1

100

101

102

1970 1990 2010 2030 205010-5

10-4

10-3

10-2

10-1

100

101

102

1970 1990 2010 2030 2050Year

MPU LgJunction depthGate oxide thickness

Direct-tunneling limit in SiO2

ITRS Roadmap(at introduction)

Wave length of electron

Distance between Si atomsSize

(µm

), V

olta

ge(V

)

Min. V supply

10 nm3 nm

0.3 nm

ULTIMATELIMIT

By Robert Chau, IWGI 2003

6

High-k Thin Film for Gate InsulatorMOSFET

p-type substrate

n+ channel n+source SiO2

gatedrain

p-type substrate

n+ channel n+source

High-k

gate

drain

2005 2007 2009 2011

Physical Gate Length (nm) 32 25 20 16

Equivalent Oxide Thickness (nm) 1.2 1.1 0.9 0.5, 0.8(DG)

ITRS 20067

Example of old days: ZrO2 MOSFETs (1969-70)

8

9

Too large high-k cause significant short channel effect

SiO2

Too largehigh-k

Gate

DrainSource

Substrate

ε r = 3.9

Gate

DrainSource

Substrate

ε r = 3.9

DrainSource

Substrate

Gateε r = 390

-2 0 2 40

0.01

0.02

0.03

0.04

0.05I d

(mA

)

Vg (V)

Lg =0.04μmVd = 0.1VEOT = 2nm

K = 3.9SiO2

K = 390Too largeHigh-k

gate

ε r = 3.9

Oxidefilm

Magnified100 timesin vertical direction

Vg= 0V, Vd=0.5V

Source Drain

gate

outsideε r = 3.9

oxide

filmε r = 390

Vg= 0V, Vd=0.5VToo largehigh-kSiO2

Penetration of lateral field from Drain through high-k causes significant short channel effects

Choice of High-k

●

● Gas or liquidat 1000 K

●H

○Radio activeHe

● ● ● ● ● ●Li Be B C N O F Ne① ● ● ● ●Na Mg Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① ① ● ● ● ●K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ① ① ① ① ● ●Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe● ③ ① ① ① ① ① ● ● ● ● ① ① ○ ○ ○Cs Ba ★ Hf Ta W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn○ ○ ○ ○ ○ ○ ○ ○Fr Ra ☆ Rf Ha Sg Ns Hs Mt

○La Ce Pr Nd PmSmEu GdTb Dy Ho Er TmYｂ Lu○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr

★

☆

Candidates

● ●Na Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① ● ● ● ●K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ①

○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu AmCm Bk Cf Es Fm Md No Lr

★

☆

②

③

Unstable at Si interfaceSi + MOX M + SiO2①

Si + MOX MSiX + SiO2

Si + MOX M + MSiXOY

HfO2 based dielectrics are selected as the first generation materials, because of their merit in1) band-offset, 2) dielectric constant3) thermal stability

La2O3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer

R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996)

10

6

11

0 V

1.1 V

V > 1 Ve

V > 1 Vh

OxideSi

CB

VB

-6

-4

-2

0

2

4

Ene

rgy

(eV

)

SiO2

4.4

3.5

1.1

2.4

1.8

0.3

3.0

-0.1

2.3

Si3N4Ta2O5

SrTiO3

BaZrO3

ZrO2

Al2O3

Y2O3

La2O3

ZrSiO4HfSiO4

4.9

2.82.3

2.6 3.4

1.51.5

3.43.3

1.4

3.4

0.8

Calculated valueBand Offsets

Si HfO2

1.9

2.1

LaAlO3

J Robertson, J Vac Sci Technol B 18 1785 (2000)Dielectric constantSiO2; 4Si3N4: ~ 7Al2O3: ~ 9

Y2O3; ~10Gd2O3: ~10

HfO2; ~23La2O3: ~27

HfO2 was chosen for the 1st generationLa2O3 is more difficult material to treat

Energy Barrier Offset of La2O3

0 10 20 30 40 50Dielectric Constant

4

2

0

-2

-4

-6

SiO2

Ban

d D

isco

ntin

uity

[eV]

Si

XPS measurement by Prof. T. Hattori, INFOS 2003

12

Historical trend of high-k R& D

1st FET

13

LSIPMOS NMOS CMOS

IC

1960 1970 1980 1990 2000 05

MOSFETGate Stackin production

Gate insulator

Gate electrode

SiO2 SiOxNy

Double Poly-Si (N+/P+)Al N+Poly-Si

Silicide above Poly Si electrode TiSi2 CoSi2WSi2MoSi2 NiSi

Hfbase

DoubleMetal

Ni3Si4MOSFET

DRAM Capacitor

NV Memory

Analog/RF

Al2O3, ZrO2

Stack NO(Si3N4/SiO2)

R&D for high-k

Recent new high-kPure Si Period

NO, AO (Al2O3/SiO2) (O)NO, Si3N4

(O)NO, Ni3Si4Ta2O5 , Al2O3,

Ta2O5 ,

1960: First MOSFET by D. Kahng and M. Atalla

14

Top View

Al Gate

Source

Drain

Si

Si

断面

Al

SiO2

Si

Exceptionally good interface

Overview of Recent High-k gate stack development01 02 03 04 05009998

2D Device simulation for short channel MOSFETs

ZrO2 / HfO2 HfO2 / HfSixOy / HfAlx(Siy)Oz

HfSixOxNy /HfAlx (Siy) Oz with IL (Interfacial Layer)mainstream

Fermi-Level Pinning was recognized

FUSI / (DM) gate electrode

DM (Dual –metal) gate

Problems for LSTP (Low Standby Power) will be somehow manageable with HfNxSixOy andFUSI, for example

IL and Metal gate are desirable for 1)mobility 2)FLP3)poly depletion

Many problems were found1)interfacial layer growth2)phase separation3)mobility degradation4)non-uniformity of the film5)boron penetration, others

k value should not be too highfor suppressing the SHE;k is possibly less than 50

HP (High performance) application is not near

Lanthanides (La2O3 etc. for next generation)Ta2O5 / TiO2

15

Importance of next regeneration materials is re-recognized because of the possible limitation of thinning HfO2 type oxides for further 2-3 generations

Low band offsetfor CB is a problem

Problems for high-k in early 2000s1) Interfacial layer formation2) Micro crystal growth3) Lateral oxidation at gate edge4) Boron penetration

E.P Gusev et al., IEDM Tech. Dig., pp.451-454, 2001

16-2 -1 0 1 20

100

200

300

400

500

Applied voltage (V)

Cap

acita

nce

(pF)

R. T. depo. EOT: 1.35 nm

250ºC depo. EOT: 0.84 nm

Gate electrode: φ110 µm1 MHz

7) Lower mobility

8) Flatband voltage shift9) Large fixed charge, interface states density10) Larger leakage current than expected

Si Substrate

Interfacial Layer

ZrO2

5) Contamination from precursor6) Non-uniformity and defect

HfCl4 + 2H2O(g) → HfO2 + 4HCl(g)

17

Intel’s announcement, January 26, 2007, and IEDM Dec 2007

Hafnium-based high-k material by ALD: EOT= 1nmSpecific gate metals ( Intel’s trade secret)

Different Metals for NMOS and PMOSUse of 193nm dry lithography

From 65 nm to 45 nm Tech.Tr density: 2 times increaseTr switching power: 30% reduction Tr switching speed: 20% improvementS-D leakage power: 5 times reductionGate oxide leakage: 10 times reduction

45nm processors (Core™2 family processors "Penryn") running Windows* Vista*, Linux* etc.

45nm production in the second half of 2007

18

PMOS

Intel's 45nm ManufacturingIntel's is currently developing its 45nm process on 300mm wafers in Hillsboro, Oregon, in D1D, a fab with clean-room space equivalent to 3.5 football fields.

Two new 300mm fabs are being built for the coming 45nm ramp: Fab 32 in Ocotillo, Arizona (production due to start in the second half of 2007) and Fab 28 in Israel (production to start in the first half of 2008).

Construction is underway on Intel's 300mm Fab 32 in Chandler, Ariz., one of three Intel fabs that will produce leading-edge microprocessors on 45nm process technology

Fab 32 under construction in Ocotillo, AZ. 19

Reza Arghavani, Ph.D.,Applied Materials ,IEDM 2007 Short Course

High-k Thin Film for Gate InsulatorMOSFET

p-type substrate

n+ channel n+source SiO2

gatedrain

p-type substrate

n+ channel n+source

High-k

gate

drain

2005 2007 2009 2011

Physical Gate Length (nm) 32 25 20 16

Equivalent Oxide Thickness (nm) 1.2 1.1 0.9 0.5, 0.8(DG)

ITRS 200622

Now, interest is High-k for EOT < 1nm

Many Problems for thinning EOT

SSi Substrate

SiON IL

HfO2

Gate Metal

IL thicknessdifficult to reduce

Mobility degradation

Interfacial SiO2 or silicate layer growth

EOT IncreaseMobility degradation

O diffusiondegrade interfaces

Si diffusion degrades interfaces

Felmi Level Pinningor gate-metal workfunctiocontrol problem

This inteface propertyalso degrades Mobility

Interface: Interface StatesFixed ChargeDipole

23

Typical HfSiON Process Flow

Post Deposition Anneal (PDA)Post Deposition Anneal (PDA)

Plasma NitridationPlasma Nitridation

Post Nitridation AnnealPost Nitridation Anneal

・0.5~0.7nm of SiO2 layer

・MOCVD, HfSiO deposition・Hf concentration（Hf/(Hf+Si)）= 60 %

・Contamination removal & Densification with suppressing phase separation, crystallization, and IL growth

・N incorporation to avoidphase separation, crystallization, andB penetration・Ar/N2 plasma nitridation

・Plasma damage recovery・Stabilization of doped N・High temperature is applicable

HfSiO

HfSiO

HfSiON

HfSiON

HiSiO Deposition (MOCVD)HiSiO Deposition (MOCVD)

Surface PreparationSurface Preparation

Y. Nara, Selete24

Typical IL (Interfacial Layer)

IL:SiO(N)(0.5-0.7nm)

Poly-Si Gate

10 nm Si-sub.

HfSiON(2.0-2.5nm)

Y. Nara, Selete

25

26

Low Gate Leakage Current with La2O3

10-10

10-6

10-2

102

0.5 1.0 1.5

La2O3Lu2O3Dy2O3Pr2O3Gd2O3

EOT (nm)

Reported Data

Cur

rent

Den

sity

(A/c

m2 )

|Vg| = 1 (V)

HfO2NH3+HfO2HfSiONAl2O3+HfO2ZrO2Zr-SilicateNH3+ZrO2Al2O3Zr-Al-Si-OPr2O3Nd2O3Sm2O3Gd2O3Dy2O3La2O3Ta2O5SiO2Nitrided SiO2

Reported DataThis Work

La2O3



SSi Substrate

SiON IL

HfO2

Gate Metal










27

Remote scattering is dominant

Mobility degradation causes for High-k MOSFETs (HfO2, Al2O3 based oxide)

High-κHigh-κ

Poly-Si gate

- - -

-+

source draine-

channel

Fixed charge

Phase separation Crystallization

Remote surface roughness

Remote phonon

+-Interfacial dipole

Hf+4

O-2

S. Saito et al., IEDM 2003, S. Saito et al., ECS Symp. on ULSI Process Integration

30

Which is dominant?RCS (Remote Charge Scattering)?RPS (Remote Phonon scattering)?

M. V. Fischetti, et al., JAP (2001).

Hf+4 O-2O-2

Origin of high-κ :large ionic polarizabitily

Strong electron-phonon interaction

RPS (Remote Phonon scattering)From the comparisonOf simulation and experiments, RCS is much dominant

Saito, ECS Sypm. On ULSIProcess Integration 2004,

L.A. Rangnarsson, IEDM 2003

O. Weber, IEDM 2004

S. Saito, Hitachi 31

Remote surface roughness effect

From S. Saito, Hitachi

32

H HHH

M. L. Green, et al., JAP (2002).

Electrode

HfO2O

Cl

HfCl

Cl

O

HfCl

ClCl

OH

substrate substrate

(1) Induced charge

(2) Induced dipole moment

(3) Disturbances of surface potential

(4) Modulation of charge centroid

J. Li and T. P. Ma, JAP (1987); S. Saito, et al., APL (2004)



SSi Substrate

SiON IL

HfO2

Gate Metal










33

Effect of gate workfunction

N-MOSFET: N-Poly Si gate electrode

Typical Vth = 0.25 ~ 0.6 V

P-MOS FET: P-Poly Si gate electrodeTypical Vth = -0.25 ~ -0.6 V

Vfb difference between N-Poly and P-Poly is 1.15 eV (Ideally)

P-MOSFET with N-Poly gate electrode

Vth -1.4 ~ -1.75 too bigdifficult to be adjusted by channel implantation 34

35

C.Hobbs, VLSI2003

0

1

2

-2 -1 0 1 2

Cap

acita

nce

(µF/

cm2 )

Voltage (V)

p+gaten+gate

HfAlOx nFET (p-well) HfSiOx nFET (p-well)p+gaten+gate

Cap

acita

nce

(µF/

cm2 )

0

1

2

-2 -1 0 1 2Voltage (V)

0

1

2

-2 -1 0 1 2

Cap

acita

nce

(µF/

cm2 )

Voltage (V)

SiONnFET (p-well)

p+gaten+gate

0

1

2

-2 -1 0 1 2

Cap

acita

nce

(µF/

cm2 )

Voltage (V)

p+gaten+gate


Cap

acita

nce

(µF/

cm2 )

0

1

2

-2 -1 0 1 2Voltage (V)

0

1

2

-2 -1 0 1 2

Cap

acita

nce

(µF/

cm2 )

Voltage (V)

SiONnFET (p-well)

p+gaten+gate

0

1

2

-2 -1 0 1 2

Cap

acita

nce

(µF/

cm2 )

Voltage (V)

p+gaten+gate

HfAlOx nFET (p-well)

0

1

2

-2 -1 0 1 2

Cap

acita

nce

(µF/

cm2 )

Voltage (V)

p+gaten+gate


Cap

acita

nce

(µF/

cm2 )

0

1

2

-2 -1 0 1 2Voltage (V)

HfSiOx nFET (p-well)p+gaten+gate

Cap

acita

nce

(µF/

cm2 )

0

1

2

-2 -1 0 1 2Voltage (V)

0

1

2

-2 -1 0 1 2

Cap

acita

nce

(µF/

cm2 )

Voltage (V)

SiONnFET (p-well)

p+gaten+gate

0

1

2

-2 -1 0 1 2

Cap

acita

nce

(µF/

cm2 )

Voltage (V)

SiONnFET (p-well)

p+gaten+gate

K.Shiraishi, VLSI2004

Fermi Level Pinning on HfO2

Difficulty in controlling Vth

Flat-band shift due to Fermi Level Pinning

-1.5-1

-0.50

0.51

1.5

HfAlO

SiON

HfSiO

NSiN

/HfS

iO

HfAlO

SiON

HfSiO

NSiN

/HfS

iO

Vfb

(V)

N-MISFET P-MISFET SiN Cap

Negative shift of VFB on P-MISEFT(HfSiON) ( -0.6 V)SiN cap cannot recover this shift

36K. Nakamura, May 30, 2005 Selete Symposium 2005

HfO2VO

0.2 eV

0.4 eVSi CB

Si VB

EF

interface dipole

poly-SiGate

SiO2

1.1 eV

pinning level

VO

HfO2VOVO

0.2 eV

0.4 eVSi CB

Si VB

EF

interface dipole

poly-SiGate

SiO2

1.1 eV

pinning levelpinning level

VO

poly-SiGate

1.1 eVSi CB

Si VBEF

0.4 eV

VO

HfO2

SiO2

VO

electron transfer

poly-SiGate

1.1 eVSi CB

Si VBEF

0.4 eV

VOVO

HfO2

SiO2

VO

electron transfer

Si CB

Si VBpoly-Si

Gate

1.1 eVEF

0.4 eV

VO

HfO2

SiO2

VO

electrongeneration

Si CB

Si VBpoly-Si

Gate

1.1 eVEF

0.4 eV

VO

HfO2

SiO2

VO

electrongenerationelectrongeneration

H. Takeuchi, et al. : J. Vac. Sci. Technol A, 22 (2004) 1337.

K.Shiraishi, VLSI2004

0.4eV

HfO2

Si

1.2eVVo level

Vo: Oxygenvacancy

Dipole formation Fermi level elevation toward the thinning level

Electron generation at the oxygen vacancy inside HfO2 region

Electron transfer into the poly

Vo formation

Si-Hf bond formation at the interface and O vacancy formation in HfO2

0 1 2 3 4 5 6 7

Si

Si-Hf

Distance from Oxide Surface [nm]

Com

posi

tion

0

0.5

1 HfO2SiO2

0 1 2 3 4 5 6 7

Si

Si-Hf

Distance from Oxide Surface [nm]

Com

posi

tion

0

0.5

1 HfO2SiO2

T. Hattori et al., WOFE 2004, Y. Morisakiet al., IWGI 2001 37R Chau, IWGI 2003

pinned

desired

Ef

Problem

Because of FLP,Vth of MOSFETbecomes too high

Mechanism of Fermi level pinning

Instability of Metal Work Function

Pt Pt

Y.Tsuchiya, SSDM2006

E.Cartier, VLSI2005

Pt, Re, Pd and Ru on HfO2 are instable with O2 and H2L.Pantisano, APL(88),243514(2006)

38

39

Instability of Metal Work Function

Pt~PtW~W Wide controllability with La2O3

K.Ohmori, SSDM2006

40

WN

TiAlN

TiSiN

TaSiN

TaN

NiSi

WSi2W

Ni

Pt

Ru

RuO2

MoN

MoTaCN

Ir

PtTa

IrO2HfN

WSi

ZrN

MoSi2CoSi2

TiN

TiSiRu50Ta50

TaTiTa

Ti

HfAl

3.5

3.75

4

4.25

4.5

4.75

5

5.25

5.5

Metal

Wor

k Fu

nctio

n (e

V)Large Discrepancy in Reported Values for Work Function of Similar Metals by Different groups

P. Majhi, Sematech, ECS-ISTC March 2005

Metals for gate electrode

for n-type for p-type

MetalsSemi-metalsNon metals

Noble gasesTransition metals

Periodic Table

Y. Akasaka, Selete 41

Reza Arghavani, Ph.D.,Applied Materials ,IEDM 2007 Short C

Work Function Tuning Using Dipole Approach


Iwai Lab’s results for La2O3 and HfO2/La2O3

46

Hygroscopic Properties of La2O3

Ln2O3

n-Si(100)

Ln2O3 + H2O → Ln2O3・H2O

Ln2O3・H2O → 2(LnOOH)

LnOOH + H2O → Ln(OH)3

Ln(OH)3

n-Si(100)

Ln2O3

n-Si(100)

Ln2O3 + H2O → Ln2O3・H2O

Ln2O3・H2O → 2(LnOOH)

LnOOH + H2O → Ln(OH)3

Ln(OH)3

n-Si(100)

Ln2O3

n-Si(100)

Ln2(CO3)3Ln2O3

n-Si(100)Ln2O3 + 2CO2→ Ln2(CO3)3

Ln2O3

n-Si(100)

Ln2(CO3)3Ln2O3

n-Si(100)Ln2O3 + 2CO2→ Ln2(CO3)3

After 30 hours in clean room (temperature & humidity controlled)47

Absorption of moisture and CO2

The oxides become hydroxide and carbonate in H2O and CO2ambient.

carbonatehydroxide

48

Ln2O3

n-Si(100)

Ln2O3

Ln2(CO3)3Ln2(OH)3 Ln2O3

n-Si(100)

n-Si(100)

n-Si(100)

Ln2O3 + H2O → Ln2O3・H2OLn2O3 + CO2→ Ln2O2(CO3)

Ln2O3 + H2O → 2(LnOOH)

※Ln：Lanthanide2Ln(OH) + H2O → 3Ln2(OH)3

Experimental apparatusTemperature: ~20oCHumidity: 80%Humidification time:

0 ~120 hrs

ThermometerHygrometer

Samples

Ultra pure water

acryl(PMMA)or

glass(PYREX)

*PMMA : CH2C(CH)3COOCH3

glass(PYREX)

acryl(PMMA)

49

50

Film Protection against Moisture

1

2

3

4

5120 hours w /o Al electrode

120 hours w ith A l electrode

moisture

n-Si(100)

Al electrode

High-k film

with electrode

n-Si(100)High-k film

～～～

Moiture absorption can be supressed by Al electrode

Humidity=80%For 120 hr

0

0.5

1

1.5

2

-2 -1 0 1

Cap

acita

nce

[µF/

cm2 ]

Voltage [V]

Sm2O

3 / n-Si(100)

RTA : N2 600oC/5min

Fresh 120hrs(with electrode)

120hrs(without electrode)Need to minimize the time

to from gate metal after PDA

Experimental Procedure

Back Pressure:10-8 PaDuringDeposition:10-7 PaDeposition rate:0.1 to 1 nm/min

51

Top gate electrode:dot thickness~150nm

La2O3SiliconBottom electrode

E-beam evaporation in ultra-high vacuum (10-7 Pa)at with substrate heater

Annealing in IR lamp heater in N2 or O2 ambient

Simple & Pure material examination

Deposition Temp. = 250oC, Tphy = 10 nm, Annealed

in O2 400oC 5min

5 nm

La 2O 3

Si-sub.

Al

52

53

Low Gate Leakage Current with La2O3

10-10

10-6

10-2

102

0.5 1.0 1.5

La2O3Lu2O3Dy2O3Pr2O3Gd2O3

EOT (nm)

Reported Data

Cur

rent

Den

sity

(A/c

m2 )

|Vg| = 1 (V)

HfO2NH3+HfO2HfSiONAl2O3+HfO2ZrO2Zr-SilicateNH3+ZrO2Al2O3Zr-Al-Si-OPr2O3Nd2O3Sm2O3Gd2O3Dy2O3La2O3Ta2O5SiO2Nitrided SiO2

Reported DataThis Work

La2O3

Pt/La2O3/Pt MIM Capacitor

100kHz10kHz1kHz

Cap

acita

nce

dens

ity (f

F/µm

2 )

0

5

10

15

20

25

30

Voltage (V)-2 -1 0 1 2

25.6fF/µm2

Pt

Pt

La2O3

54Voltage (V)0 1 2 3 4 5

10-910-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

FG anneal@500oC

Cur

rent

den

sity

(A/c

m2 )

FG anneal@300oC

thickness=8.3nm, k=21

K. Kakushima et al. Si Nanoelec. Workshop 2006

La2O3 : Hear endurance is good

0CET (nm)

TaTiOK. C. Chiang, VLSI’05

A/H/Nb/H/AS.J.Kim, VLSI’04

HfTbOS.Kim, VLSI’03

A/T/AY.L.Tu, VLSI’03

A/H/A/H/AH.Hu, IEDM’03

HfO2/SiO2S.J.Kim, VLSI’05

La2O3This Work

1 2 3 4 5 6 7

Cur

rent

den

sity

(A/c

m2 )

10-9

10-8

10-7

10-6

10-5

10-4 40 20 13 10 8 7 6Capacitance density (fF/µm2)

K. Kakushima et al. Si Nanoelec. Workshop 2006 55

PDA

PMA

PDA/PMA

PDA

PMA

PMA

PDA/PMA

PMA

PDA/PMAPDA

0.0

1.0

2.0

3.0

4.0

5.0

-2.5 -1.5 -0.5 0.5 1.5 2.5Voltage(V)

C(µ

F/cm

2 )WTi

RuAl

Threshold voltage (Vth) can be adjusted using Metal Wokfunction

PDA and PMA at 300 oC

No Fermi Level Pinning with La2O3

56K. Kakushima et al. Si Nanoelec. Workshop 2006

La2O3 Gated MOSFET Fabrication

SPM, HF Cleaning Source/Drain pre-formed Substrate

SPM, DHF cleanning

La2O3 deposition

(PDA)

Al gate deposition and patterning

(PMA)

La2O3 etching for S/D contacts

Al lift-off for S/D pads

High-k film Deposition

57

Etching Al, High-k

Lift-off Al

58

Post Metallization Annealing (PMA) of Al gated La2O3 MOS Capacitor

1.00-1.0Voltage (V)

1.50.5-0.5-2.0 -1.5

2.5

2.0

1.5

1.0

0.5

0

C (µ

F/cm

2 )

PMAPDA

30 sec

1 min5 min

10 min

-0.5

0.5

-1.5

-1.0

0

1.0

(30sec)

(1min) (5min)

(10min)

4002000 500300100Annealing duration (sec)

600

Tphy(La2O3) = 4.5 (nm)

PMAPDA

(30sec) (1min) (5min) (10min)

∆V

FB(id

eal V

FB–

VFB

) (V

)

Al2O3

From the TEM observation,the Al2O3 thickness of the 10minutes PMA sample was measured to be 2.2 nm

Al2O3 (2.2nm)

Si

Al

La2O3

PMA@10min

VFB shift to positive direction (negative charge)

Large EOT increment due to Al2O3 formation

Y. Kuroki, et al., ECS 208th

59

Electrical Characteristics of La2O3 n-MOSFET

0 1 2-1-2

0.3

0.25

0.2

0.15

0.1

0.05

0.00

100

10-1

10-2

10-3

10-4

10-5

10-6

10-7

10-8

Gate voltage (V)

Dra

in c

urre

nt (m

A/µ

m) D

rain current (mA

/µm)Vd=100mV

L/W=10µm/54µm

S=87.4 mV

Vd (V)

Id (µ

A/µm

)

20 1 1.50.50

10203040506070

W/L (µm)54/10

300oC PDAEOT 1.7nm

Vg=-0.25 ~ 1.5 V

Process- La2O3 300 oC deposition- PDA N2 300 oC 10 min

Al/La2O3/p-Si/Al

Good electrical characteristics can be obtained.K. Kakushima et al. Si Nanoelec. Workshop 2006

Effective Mobility of La2O3MOSFET

High effective mobility of 312 cm2/Vscan be obtained with La2O3

0 0.2 0.4 0.6 0.8 1.00

100

200

300

400

Effective electric field (MV/cm)

Effe

ctiv

e m

obili

ty (c

m2 /V

s)Peak µeff= 312 cm2/Vs

N2 PDA 300 oC 10min

µeff @ 0.8MV/cm = 280 cm2/Vs

EOT=1.7nmL/W=10µm/54µm

K. Kakushima et al. Si Nanoelec. Workshop 200660

1/f noise in saturation region

10-22

10-21

10-20

10-19

10-18

10-17

101 102 103 104

Vd=1.0V, V

g@I

d=100µA

S ID (A

2 /Hz)

Frequency (Hz)

La2O3

SiO2

f1

WxL = 54µm x 10µm10-22

10-21

10-20

10-19

10-18

10-17

101 102 103 104

Vd=1.0V, V

g@I

d=100µA

S ID (A

2 /Hz)

Frequency (Hz)

La2O3

SiO2

f1

WxL = 54µm x 10µm

61

Interfacial State Density

0

100

200

300

400

500

1.0E+10 1.0E+11 1.0E+12 1.0E+13Dit (cm2e/V)

Peak

Ueff

(cm2 /V

s)

La2O3

O2 PDAN2 PDA

SiO2

0

100

200

300

400

500

1.0E+10 1.0E+11 1.0E+12 1.0E+13Dit (cm2e/V)

Peak

Ueff

(cm2 /V

s)

0

100

200

300

400

500

1.0E+10 1.0E+11 1.0E+12 1.0E+13Dit (cm2e/V)

Peak

Ueff

(cm2 /V

s)

La2O3

O2 PDAN2 PDAO2 PDAN2 PDA

SiO2PDA 300 oC

PDA 400 oCPDA 500 oC

Dit (cm-2eV-1)

0.0E+00

5.0E-09

1.0E-08

1.5E-08

2.0E-08

2.5E-08

3.0E-08

3.5E-08

4.0E-08

-4 -3 -2 -1

Vbase (V)

Icp (A

)

L/W (µm)10/54

f=100kHz

PDA300

PDA400

PDA500

Interface state density increases at higher temperature annealing

62K. Kakushima et al. Si Nanoelec. Workshop 2006

Effective Mobility of La2O3 MOSFET on PDA Temperature

0

100

200

300

400

0 0.25 0.5 0.75 1 1.25 1.5Eeff (MV/cm)

U eff (

cm2 /V

s)

SiO2(11nm)PDA300PDA400PDA500PDA600

263 cm2/Vs312 cm2/Vs

240 cm2/Vs

155 cm2/Vs

Al/La2O3/p-Si(100)/Al

Lg = 10umWg = 54um

0

100

200

300

400

0 0.25 0.5 0.75 1 1.25 1.5Eeff (MV/cm)

U eff (

cm2 /V

s)

SiO2(11nm)PDA300PDA400PDA500PDA600

263 cm2/Vs312 cm2/Vs

240 cm2/Vs

155 cm2/Vs

Al/La2O3/p-Si(100)/Al

Lg = 10umWg = 54um

Higher PDA temperature degrades the mobilityK. Kakushima et al. Si Nanoelec. Workshop 2006 63

La2O3 Gate Insulator for High Temperature Process

64

High temperature annealing above 500oC

SiOx based interfacial layer formation- Increase in EOT- Higher Dit

Interfacial Layer Suppression using buffer layer

148150152154156

Binding Energy (eV)

As-depo.

Si-2s600ºC La- Silicate

SiO2

Nor

mal

ized

inte

nsity

(a

.u.)

150152154156

TOA=60°

XPS analysis of La2O3/Si

148

La2O3

Si SiSc2O3

ScSiO

La2O3

Free Energy (kJ/mol)Sc2O3 ΔG= -1901 + 0.287 * TY2O3 ΔG= -1895 + 0.281 * TLa2O3 ΔG=-1785 + 0.277 * T K. Kakushima et al. Si Nanoelec. Workshop 2006

65

-2 -1 0 1

2.0

1.5

1.0

0.5

0

2.5

Cap

acita

nce

dens

ity (µ

F/cm

2 )

Gate voltage (V)

La2O3 (5.5nm)EOT=1.22nm

La2O3/Sc2O3 (2.1nm/2.1nm)EOT=1.03nm

RTA 900oC 2sec in N2

0

10-6

10-5

10-4

10-3

10-2

10-1

10-0

Cur

rent

den

sity

(A/c

m2 )

10-7

10-8

0.5 1.0 1.5 2.0

RTA 900oC 2secN2

La2O 3(5.5nm)

La2O 3/Sc 2O 3

(2.1nm/2.1nm)

Gate voltage (V)

Sc2O3 Buffer Layer for High Temperature Process

High temperature stability can be obtained with Sc2O3 buffer layer K. Kakushima et al. Si Nanoelec. Workshop 2006

Leakage current suppression without degrading the CV curve

Submitted Symp. On VLSI, Yesterday

Gate DielectricResearchDevelop.Qual./Pre-Prod.Conti.Improv.

Oxynitride

Hf(Zr)-base

RE high-k(La2O3,…)

(LaAlO3)

(LaAlO3)

ITRS2003

Ternary

Epitaxial

2004hp90

2010hp45

2007hp65

2008

YearTech. node

Thinning EOT toward 0.5-0.7 nm

Keeping good mobility with thinning IL

Searching new materials: La2O3 based

ITRS 200367

Thank you!

68

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