IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 8, AUGUST 1995 1419

High Efficiency Microwave Power AlGaAsDnGaAs PHEMT’s Fabricated by Dry Etch Single Gate Recess

C. S. Wu, Senior Member, IEEE, F . Ren, Senior Member, IEEE, S. J . Pearton, Senior Member, IEEE, M . Hu, C. K. Pao, Member, IEEE, and R. F. Wang

Abstract-An optimized pseudomorphic high electron mobility transistor (PHEMT) epitaxial structure processed with a novel single gate recess technique is shown to achieve 850 mW of output power (760 mW . mm-l saturated power density) with 50% power added efficiency at X-band when operated at a CW and nearly class A condition. The multi-finger devices (14 x 80 pm) retain high extrinsic transconductances (380-420 mS . mm-I), with exceptional breakdown voltage (>U V). The combination of optimized epi layer structure design and uniform gate recess using a damage-free, etch-stop, dry plasma processing step produces consistently and uniformly high f~ values (80 GHz at VDS = 1 V, 35 GHz at VDS = 7 V) even at low IDS (100 mA . mm-l).

I. INTRODUCTION

ECENTLY, pseudomorphic high electron mobility tran- R sistors (PHEMT’s) have demonstrated superior perfor- mance at microwave and millimeter wave frequency ranges [1]-[lo]. Due to a broad spectrum of applications and an increasing interest in systems insertion, the demand for large quantities of PHEMT devices is increasing. The development of a PHEMT manufacturing technology is therefore of prime interest to meet this demand from advanced microwave and millimeter wave systems. To achieve a high yield and high performance technology, there are two important areas which must be optimized; one is the device epitaxial structure and the other is the processing [l], [2]. The high linearity of PHEMT’s produces low output distortion, low harmonic levels, and intermodulation distortion and high saturated output power, all of which are particularly important for C-band and Ku-band applications.

For microwave frequencies, GaAs MESFET’s are well- established but PHEMT’s may replace them in some appli- cations since they are capable of identical or greater output power with higher gain and efficiency. How quickly this occur will be determined by how quickly PHEMT manufacturing technology matures to the point that large gate width devices can be made with acceptable yield. There is a high degree of motivation for development of power PHEMT’s for lower frequency applications such as phase array radar to alleviate

Manuscript received June 9, 1994; revised January 13, 1995. The review of this paper was arranged by Associate Editor P. M. Solomon.

C. S. Wu, M. Hu, C. K. Pao, and R. F. Wang are with Hughes Aircraft Company, GaAs Operations, Microelectronics Division, Torrance, CA 90509 USA.

F. Ren is with AT&T Bell Laboratories, Murray Hill, NJ 07974 USA. S. J. Pearton is with the University of Florida, Gainesville, FL 3261 1 USA. IEEE Log Number 9412474.

array thermal loading and reduced prime power requirements. Shanfield et al. [6] reported 0.97 W output power with 10 dB gain and 70% power-added efficiency (PAE) at 10 GHz and the same power with 6.8 dB gain and 48% PAE at 18 GHz from a PHEMT.

In this paper we report an optimized epitaxial layer de- sign and dry etch gate recess process which produces high output power while retaining good dc and RF performance for PHEMT’s. The uniformity of device performance is much improved for dry etched wafers relative to wet chemically etched devices due to the high selectivity for removing the GaAs cap layer from the underlying AlGaAs Schottky contact layer.

11. EXPERIMENTAL

The device epitaxial layer structure grown by Molecular Beam Epitaxy is designed with a fully depleted GaAs cap layer, and is shown in Table I. While fully depleted caps have been shown to lead to a fall-off of f~ at high drain-source voltages (VDS) [I] , it is necessary to achieve a high breakdown voltage (VBD). A double-sided planar doping approach was employed to provide sufficient charge to the InGaAs channel. The double-sided atomic delta-doped layers provided a sheet charge density of - 3 x 1012cm-2 and 300 K electron mobility of - 5500 cm2 V-’ . s-l. To achieve a high breakdown voltage we used an undoped AlGaAs Schottky contact layer for reduced tunneling current. A conducting GaAs cap layer leads to low VBD because of electric field crowding on the drain side adjacent to the gate fingers. An alternative approach to achieving high breakdown voltage is to use a double gate recess, but this requires two gate lithography steps and two etch steps. We have previously found that double-sided doped devices have slightly higher noise figures than conventional single-sided structures [I], but exhibit superior uniformity, power, and yield because of the higher sheet charge and lower sensitivity to variations in gate recess depth. Implant isolation using multiple energy O+ ions was used to define the active device area. Ohmic contacts of NiJAuGelAglAu were deposited by e-beam evaporation and patterned by conventional lift-off processing [ 1 11. Prior to metal deposition the wafers were cleaned by 0 2 plasma exposure in a barrel reactor and NH~OH:HPO rinsing to ensure smooth contact edges and definition and lack of spiking due to the presence of residual native oxide on the GaAs surface. This cleaning procedure allows use of a wide op-

0018-9383/95$04.00 0 1995 IEEE

1420 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 8, AUGUST 1995

TABLE I EPITAXIAL LAYER STRU(JTcTRE FOR P " r

50

TARGET DEPTH (A) 100

Fig. 1. ions in GaAs.

Calculated projected ion ranges and straggles for low energy C+

timal alloying temperature window (440-54OoC), producing a contact resistance of 0.1 0-mm. These contacts show no change in resistance over 1000 hrs of stress time at elevated temperature.

E-beam lithography was used to write gate openings of 0.25- 0.3 pm. Gate widths were 1.12 mm, composed of 14 x 80 pm fingers for each cell. Prior to loading in the dry etch reactor, the 3"4 wafers were again cleaned in an NH40H:H20 solution with mega-sonic agitation in order to aid penetration of this liquid into the small gate openings. It is necessary to remove the GaAs native oxide prior to the dry etch step since remnant oxide can lead to an incubation time before the actual etching begins [12]. Since the etch rate for GaAs under our conditions is - 2200 A . min-l, and the etch depth is only - 300 A, the time required is small, so uncontrolled incubation times are undesirable. In addition, any extension of the etch time can lead to e-beam resist mask erosion and degradation of the subsequent T-shape gate, or to undercutting of the e-beam resist.

Dry etching was performed in either the reactive ion etch or Electron Cyclotron Resonance etch modes in Plasma Therm SL 720 or 770 systems. The process pressure was 5 mTorr with CC12F2 flow rate of 25 standard cubic centimeters per minute. The RF-induced dc bias at the sample position was -30 V, which is below the atomic displacement threshold for 111-V semiconductors [ 131. Therefore etching under these conditions will not create any ion-induced damage. There are two other ways in which dry etching can disrupt the

near-surface of semiconductors. The first is alteration of the stoichiometry, for example, by preferential loss of one of the lattice elements or deposition of etch-related residues on the surface, i.e., formation of AlF3 on AlGaAs exposed to CClzF2 or BC13/SF6 discharges. Indeed, the latter is the etch stop mechanism for selective removal of GaAs from AlGaAs using these plasma chemistries [ 141. Under our conditions this selectivity is >600: 1. Auger Electron Spectrometry showed the exposed AlGaAs surface was composed of a thin (- 25 A) mixture of native oxide and AlF3, and the AlGaAs beneath this region was stoichiometric. A simple post-etch clean in an 0 2

barrel reactor, NH40H:H20 solution and finally H20 rinsing completely removed the fluorine-related residues, and left a clean stoichiometric surface for TiRAu gate metal deposition by e-beam evaporation [ 151.

The other mechanism by which the AlGaAs may be dis- rupted is by direct implantation of ions such as C+, from the plasma. A Transport of Ions in Matter (TRIM) calculation [ 161 of the projected range and longitudinal and lateral straggles of implanted C+ ions is shown in Fig. 1. Note that these values are only a few As, and a calculated implanted C+ ion profile is given in Fig. 2. The heavier chlorine, fluorine, or molecular ions implanted into the surface will have even shallower profiles. For ion energies below - 25 eV, none of the energy is lost to vacancy production, only to ionizing electrons and phonon production. Channeling of the implanted ions can increase the penetration depth, but there is essentially no defect production at low ion energies. At higher biases (2 -100 V) damage in the form of crystal point defects is created, and leads to a reduction in the near-surface doping density since these defects usually act as deep level traps [13]. The depth of this damage can be greater than that expected from calculations of the ion range and is ascribed to the creation of defects at the surface which diffuse rapidly into the bulk to cause carrier compensation. Finally, atomic hydrogen may be present in plasmas because of water vapor in the reactor or resist erosion and this can lead to hydrogen passivation in the near-surface region even when hydrogen is not a specific part of the plasma chemistry [17]. In the current work we found that the combination of short etch time, load-locked reactor chamber, and low ion energies produced damage-free gate recessing. Test samples of n- type GaAs cm-3 ) processed by either wet or dry etch removal of - 2000 A of material and then cleaned as for the PHEMT devices showed identical Schottky barrier heights and ideality factors for e-beam deposited TiPtAu gate contacts .

After the dry etch gate recess step for PHEMT's, T-shaped e-beam deposited TiPtAu metallization was defined by lift-off to produce the 0.25 pm gate length device. Plasma-enhanced chemically vapor deposited SiN, was used for passivation [18] and was found to produce minimal change in breakdown voltage and other dc drain I-V characteristics over a broad range of ammonia flow rates [19]. The Si3N4 thickness was 1000 A, which slightly degrades the device f~ (5%) due to increased gate capacitance associated with the presence of the high dielectric constant material surrounding the gate finger region.

WU et al.: HIGH EFFICIENCY MICROWAVE POWER PHEMT'S FABRICATED B Y DRY ETCH SINGLE GATE RECESS

L(mA/mm)* f3lo-650 102 eV 1 keV

( ~ ) ~ ~ ( m S / m m ) 380-420 ION ENERGY (eV)

____

1421

8m-950 > I 2 5 0

420-450 44C-480

Fig. 2. Depth distribution of 20 eV C+ ions implanted into GaAs as determined from a Transport of Ions in Matter (TRIM) simulation. This is a worst-case scenario since it assumes there is no etching of the material, and therefore it applies to the situation of an over-etch of GaAs from an underlying AlGaAs layer which is not volatile in a CC12F2 discharge.

1 0-2

1 0-5

h s ln -

10-10

10-14

- - - - -

n = 1.31 0B = 0.86 eV

0.00 0.150 1.500

vGS (v) Fig. 3. Forward I-V characteristic from a dry-etched gate recessed power PHEMT device.

111. RESULTS AND DISCUSSION Table I1 shows a comparison of Schottky gate characteristics

between dry etched and wet etched gate recessed PHEMT's. The superior performance of the dry etched devices is due to the superior profile control and higher selectivity for removal of the GaAs cap layer from the AlGaAs layer underneath. The forward I-V characteristics from a dry-etched device are shown in Fig. 3. The values of 4~ and n for wet- etched (NH40H:HzOz:HzO solution) devices are skewed by the presence of more significant low voltage leakage current in these PHEMT's. This may be due to the presence of residual GaAs at the interface which is not removed by wet etching. This leakage alters the slope of the I-V curve and leads to lower apparent 4~ and higher n values. We do not mean to imply that the listed values in Table I1 are anything other than strong evidence of the superiority of the dry gate recess

* I, is the PHEMT epi material's s d o n current which is m e a s e from WO ohmic metal pads with 2 . 5 ~ spacing after ohmic confs~t is formcd. The h includes current wmpoaents from botb n+ GaAs cap and lnGaAS chaoml layers.

** 1- is approximately the full channel c w n t of PHEMT devices measured at V, = +0.7 V.

process. The uniformity of IDSS (saturation drain current at VGS of 0 V) and pinch-off voltage were typically f 7 % for dry etched 3"d wafers whereas wet etched double gate recess wafers have 520% variation in these parameters. Typical dry recess profiles have been shown previously. [12] The amount of undercut can be controlled by the etch duration and pressure.

Fig. 4 shows typical ID - VDS characteristics for a 14 finger power PHEMT. The breakdown voltage (BVDS) for these devices is in the range 18-20 V, with extrinsic transconductances of 380-420 mS . mm-' . The breakdown is defined as the voltage at which there is a sharp increase in 10s. Table 111 shows a comparison of the dc performance of the PHEMT's optimized for high breakdown voltage in this work (first column) with the performance of PHEMT's with epi structures designed for various low-noise and millimeter power applications (second and third columns). Note that the dc performance of the power PHEMT's is not compromised much relative to the other classes of devices. This is of particular importance for multi-functional PHEMT devices and monolithic microwave integrated circuit products, in which one may require good power and noise performance.

The S-parameters of the PHEMT devices were measured using an HP 8510 vector network analyzer. The calibration was completed with impedance standards from Cascade Microtech. The measured data were used to calculate H21 and maximum available gain (MAG) or maximum stable gain (MSG), and both f~ and fMAX were estimated by extrapolation of the measurement to 40 GHz. Fig. 5 shows f~ as a function of VDS for a gate voltage of -0.8 V and low IDS of 100

1422 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 8, AUGUST 1995

$ 20

2 " 2

B - - :: $ 1 5 -

10

0 2 4 6 8 10

VDS

Fig. 4. width power PHEMT.

I D - VDS characteristic for a 0.25 pm gate length, 1.12 mm gate

0 - -

0 0

-

Vm=5V

' I ' I ' 1 ' 1 1 '

0 60

0

0 -

-

v G s = 4 . 8 v -

VDS (v)

Fig. 5. fT as a function of VDS for a PHEMT at VG = -0.8 V

mA . mm-'. The f~ values are highly bias-dependent since the structure is designed to provide both high breakdown and high speed. Note that the devices retain high f~ values of 50 GHz and 35-40 GHz at VDS = 5 or 7 V, respectively. These high f~ values at high VDS allow the devices to be operated out to higher frequencies (up to 20 GHz) for power applications requiring large biases. The MAGMSG for the power PHEMT's measured at VDS of 3-5 V was 18-20 dB at 10 GHz and 14-15 dB at 18 GHz, respectively. Fig. 6 shows the frequency dependence of MAGMSG at VDS = 5 V for different gate voltages. The MAG at 10 GHz is shown as a function of gate voltage in Fig. 7 for a VDS of 5 V. Note that there is fairly constant gain available over a wide range of gate voltage, another desirable feature for power operation.

Freq (GHz)

Fig. 6. PHEMT at different gate voltages.

Maximum available gain as a function of frequency for a power

-vGs (V) 4 vp.

Fig. 7. for a power PHEMT. The VDS was 5 V.

Maximum available gain at 10 GHz as a function at gate voltage

S-parameter data for the multiple-finger PHEMT's (22 x 50 pm in this case) are shown in Fig. 8. From these data the equivalent circuit of the devices was extracted and is shown in Fig. 9. This linear transistor model contains 13 equivalent circuit elements.

In order to measure the maximum output power and the associated efficiency, the devices were mounted on a brass carrier with conductive epoxy and a well-characterized inter- continental fixture was used as the test jig. The measurement was performed with a simple X-band power test set-up. The source and load impedance matching were optimized with two double-probe tuners, and a band-pass filter was incorporated with the output power detector to ensure a correct power reading at the fundamental frequency. Table IV shows output power and power-added efficiency as a function of input power at 9 GHz for a 14 x 80 pm device with VDS = 8 V. We achieved 865 mW of saturated output power (corresponding

WU er al.: HIGH EFFICIENCY MICROWAVE POWER PHEMT’S FABRICATED BY DRY ETCH SINGLE GATE RECESS 1423

0 PHEW I l l j u n k

s r i . 0

1 0

I n f

0

F r e q u e n c y 0.5 t o 2 0 . 0 GHz

Fig. 8. Measured S parameters for a PHEMT.

Linear FET Model

Rg =l.OOhm

Rd = 0.7 Ohm

R. I 0.34 Ohm

Lp = O m n H

Ld I 0.0135 nH Ls =O.NUnH

Cgs= 1.08 pF

Cd.3-w

Cde= 0.05 PF

RI =0.10Ohm

Rds= 99.4 Ohm

G m = “ S

T =26pS

PHEMT025uMl.lOmm(~),Vd=7VMdVg=0.7V(113Idas).allX110*

Fig. 9. Equivalent circuit for power PHEMT derived from S-parameter data.

to a power density of 760 mW mm-’) with 50% PAE and 9.25 dB associated gain at 9 GHz from this 1.12 mm PHEMT. These results are comparable to those reported by the Raytheon group [6], and demonstrate the capability of PHEMT’s for power microwave applications and the monolithic integration of low noise and power PHEMT’s using the same epitaxial layer design.

IV. CONCLUSIONS An optimized pseudomorphic HEMT structure processed

with a single recess gate technique produces devices with both high output power and good dc and RF performance. The device epitaxial structure is designed with a fully depleted GaAs cap layer and the gate recess was performed with a highly uniform damage-free dry etch process. The power PHEMT’s exhibit high ~ T ’ S (40-50 GHz) at high drain-source voltage and low drain-source current, an essential requirement for high power operation in the C- to Ku-band range.

TABLE IV OUTPUT POWER (POUT) AND POWER-ADDED EFFICIENCY (PAE)

AS A FUNCTION OF INPUT POWER ( P I N ) AT 9 GHZ FOR A 14 x 80 pm PHEMT. THE DRAIN-SOURCE VOLTAGE WAS 8 V

qN(&m) P m ( d B m ) p a ( % ) 50

29.3 20

43 29.0 18

15 30 27.2

20 25.3 13

ACKNOWLEDGMENT

The authors thank Drs. D. C. Wang, C. P. Wen, and T. A. Midford for technical guidance, and A. M. Gomez, M. J. Circle, R. D. Larson, A. Grohs, and J. R. Lothian for process assistance. We appreciate the support of Dr. H. C . Bowers in this work.

REFERENCES

[I] See e.g., C. S. Wu, G. L. Lan, C. K. Pao, S. X. Bar, and M. Hu, “Pseudomorphic HEMT devices for microwave and millimeter wave applications,” in Mat. Res. Soc. Symp. Proc., vol. 300, 1993, pp. 41-54.

[2] P. C. Chao, A. W. Swanson, A. Brown, U. Mishra, F. Ali, and C. Yuen, “HEMT Devices and Applications,” in HEMT’s and HBT’s, F. Ali and A. Gupta, Eds.

[3] P. M. Smith, et al., “InGaAs PHEMT’s for mm-wave power applica- tions,” IEEE MZT-S Dig., pp. 927-930, May 1988.

[4] H. Q. Tsemg, B. Kim, P. Saunier, H. D. Shih, and M. A. Khatibzadeh, “mm wave power transistor and circuits,” Microwave J., pp. 125-135, Apr. 1989.

[5 ] T. H. Chen, et al., “A 0.1 W W-Band PHEMT MMIC power amplifier,” in G d s IC Symp. Dig., 1992, pp. 71-74.

[6] S. Shanfield, et al., “IW, very high efficiency, IO and 18 GHz PHEMT’s fabricated by dry first recess etching,” IEEE M7T-S Dig. pp. 639-641, June 1992.

[7] K. L. Lan, et al., “High power, V-band PHEMT,” IEEE Electron Device Lett., vol. 12, pp. 213-214, 1991.

[8] C. K. Pao, et al., “V-band high efficiency monolithic PHEMT power am- plifiers,’’ IEEE Microwave and Guided Wave Lett., vol. 2, pp. 394-396, 1992.

[9] J. C. Huang, er al., “An AlGaAdInGaAs PHEMT for X- and Ku-band power applications,” [ I l l , IEEE MZT-S Dig. pp. 713-716, 1991.

[IO] P. M. Smith, P. C. Chao, J. M. Ballingall, and A. W. Swanson, “Mi- crowave and mm-wave power application using PHEMTs,” Microwave J., pp. 71-86, May 1990.

[ l l ] C. S. Wu, K. K. Yu, M. Hu, and H. Kanber, “Optimization of ohmic contacts for reliable heterostructure GaAs materials,” J. Electron Mat. vol. 19, pp. 1265-1271, 1990.

[I21 F. Ren, et al., “0.25 pm PHEMT’s processed with damage-free dry etch gate recess process,” IEEE Trans. Electron Devices, vol. 39, pp. 2701-2706, Dec. 1992.

[I31 S. J. Pearton, et al., “Plasma etching of 111-V semiconductor thin films,” Mat. Chem. Phys. vol. 32, pp. 215-234, 1992.

[14] K. L. Seaward, N. J. Moll, D. J. Coulman, and W. F. Stickle, “An analytical study of etch and etch-stop reactions for GaAs on AlGaAs in CClzFz plasma,” J. Appl., vol. 61, pp. 2358-2363, 1987.

[15] F. Ren, et al., “Dry etching bilayer and trilevel resist systems for submicron gate length GaAs-based HEMT’s for power and digital applications,” J. Vac. Sci. Technol., vol. B10, pp. 2949-2953, 1992.

[I61 The TRIM code is described in J. F. Ziegler, J. P. Biersack, and U. Littmark, The Stopping and Range of Ions in Solids, vol. 1. NY: Pergamon Press, 1984.

[I71 S. J. Pearton, J. W. Corbett, and M. Stavola, Hydrogen in Crysralline Semiconductors. Heidelberg: Springer-Verlag, 1992.

[18] E. Y. Chang, G. T. Cizubar, and K. P. Pande, “Passivation of GaAs FET’s with PECVD S i N , films of different stress states,” IEEE Trans. Electron Devices, vol. 35, pp. 1412-1418, 1988.

[19] C. S. Wu, et al., “High yield PHEMT manufacturing technology development,” in Proc. 1993 U.S. Conj Gds Manu. Technol., 1993, pp. 4142.

Boston: Artech House, 1991.

1424 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 8, AUGUST 1995

C. S. Wu (M’88SM’93) received the M.S. degree in physics from National Tsing Hua University, Taiwan, in 1976, and the Ph.D. degree in electrical engineering from the University of California, San Diego, La Jolla, CA, in 1984.

After he obtained the Ph.D. degree, he joined AT&T Bell Laboratories at Murray Hill, NJ, where he was a member of the technical staff responsible for the research and development of self-aligned gate GaAs MESFET and HEMT devices and pro- cessing for high speed digital circuits. In 1987, he

was the project leader in the DARPA GaAs pilot line program. In December 1987, he joined GaAs Operations, Hughes Aircraft Company, where he is currently a section head in charge of the research and development of advanced heterostructure microwave and optical devices and processes. His work has led to state-of-the-art microwavehillimeter wave pseudomorphic HEMT (PHEMT) devices and MMIC amplifiers, X-band power heterojunction bipolar transistor (HBT) devices and amplifiers, and high radiation hard GaAs based MQW LWIR detectors. He is currently leading an interdepartmental team for the development of MMIC PHEMT manufacturing technology. He is the principal technical investigator of advanced technology in the MIMIC Phase 2 program. He has published more than 60 technical papers on semiconductor devices, processing, and circuits, and holds eight patents. Dr. Wu is a member of the Bohmische Physical Society, the Materials

Research Society, and SPIE.

S. J. Pearton (A’91-SM’93) performed the work leading to the Ph.D. degree in physics at the Australian Atomic Energy Commission.

He was a postdoctoral research associate at the Lawrence Berkeley Labora- tory, Berkeley, CA. Since 1984, he has been a member of the technical staff at AT&T Bell Laboratories, working in the area of ion implantation, rapid thermal annealing, GaAs-on-Si, hydrogenation, and dry etching. He is the author of over 300 journal articles and has edited five conference proceedings.

M. Hu, photograph and biography not available at the time of publication.

C. K. Pa0 (S’75-M’7&S’8@4’82-M’82-M’85), photograph and biography not available at the time of publication.

F. Ren (SM’93) received the Ph.D. degree in in- organic chemistry from the Polytechnic University, Brooklyn, NY.

He joined AT&T Bell Laboratories in 1986 as a member of the technical staff. He has worked in the areas of ion implentation, dry etching, pa- sivation, and metallization. He is the author of over 180 journal articles and has edited two conference proceedings.

R. F. Wang, photograph and biography not available at the time of publication.