hezi saar, sr. staff product marketing manager · 2018-01-17 · hezi saar, sr. staff product...

Hezi Saar, Sr. Staff Product Marketing ManagerSynopsys

Driving 4K High-Resolution Embedded Displays in New Applications with MIPI DSI℠ and VESA DSC (Synopsys & Arm)

©2017MIPIAlliance,Inc.

Agenda• Risingdemandforhighresolutiondisplays

• Arm®Mali®-CetusDisplayprocessor

• Synopsys®DesignWare®MIPIDSI℠HostControllerwithVESADSCEncoder

• Synopsys&ArmsolutionSynopsys&Arm

2


BandwidthDemandIncreasesforEmbeddedDisplays

• Mobile:– MorepowerfulGPU,higherresolutioncameras,

richercontentwithhighresolutionandbettervisualqualitydrivesthedemandformobiledeviceshavingabetterdisplays.

• VR/AR:– Virtualrealityapplicationrequiresdisplayswith

notonlyhighresolutionbuthighrefreshrate• Automotive:

– Dashboard/infotainment/mirrorlesssystemdisplayswithcustomizedhighresolutionsanddetailsdemandsbandwidthincreases

Synopsys&Arm

Meetsthedemandsofvivid,detailedandimmersivevisualexperience

3


ArmMaliDisplayOverview

Synopsys&Arm

4


ArmMaliDisplayinArmMultimediaSubsystem

Synopsys&Arm

Supportsallmajordisplayindustrystandards:MIPI,HDMI,VESA,CEA-861,ITU-R

Lowpowerreal-timeperformance:Singlepasscomposition,Arm FrameBufferCompression(AFBC),OptimizedSMMUintegration

FeatureRich:Composition,scaling,rotationgammacorrection,colourmanagement,co-processorinterface,dual-display

Optimizedsoftwaresupport:AndroidDDKLinuxKMSArmMaliMultimediaSuite

5


ArmMaliDisplayprocessors- DrivingDisplayTechnologies

Firstarchitecturewasdesignedfor1080p60,1440p60,1600p60mobile/tabletdisplaysNewarchitectureneededtoaddress:• Higherperformancerequirements(upto4K120fps)drivenbyVR• QuadscalingandmorelayersforAndroidN+multi-windowusecase• Powerandqualityoptimizationsforgrowingvarietyofpanelandsystems• CompositionfornewdisruptiveUHDcontent(HDR10,HLG)

Synopsys&Arm

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ArmMali-CetusArchitectureOverview

Synopsys&Arm

7


BetterAndroidWindowCompositionCapabilities• Supportformulti-windowsessionsinAndroidN

– OptimizedHWCSolver• 8compositionlayerswhendrivingasingle

display– 4layersperdisplayoutputfordualdisplay

• 4scaledlayerswhendrivingasingledisplay– 2scaledlayersperdisplayoutputwhendrivingadual

display• Simultaneouslayer+pixelalphablending

– Idealforwindowanimations• FullyflexibleandsoftwareprogrammableZorder

Synopsys&Arm

UISpare

App1 App2

Video1

Video2Pop-up

Statuspulldown

Navigation

8


FlexibleUseofDisplayProcessorResources• SoftwareLayerSplitandLayerMerge

• Softwarelayersplitandinternallayersplitofdisplaylayerswith2scalingenginestooptimizedemandingdownscalingusecases

• SidebySideProcessing

• Side-by-sideprocessingforlowvoltageoperationat4Kp60-120fps

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Performance,AreaComparisonAdditionalfunctionalityinCetus• 8compositionlayers(vs4inDP650)• Side-by-sideprocessing• Scalingsplit• Uncompressedrotationremoved

fromtherealtimepath• HigherAFBCdecoderthroughput• ReductionofMMUlatency

Synopsys&Arm

2x

4x

0

5

DP650+SMMU-500 Cetus+SMMU-Tethra

DieArea

Display SMMUTSMC16FF+LVTC167.5-track,9-metallayers

1.02x

10


DisplayOutputUnitBackendSubsystem

Synopsys&Arm

VBP VBP

VFPVFP

HFPHBP HFPHBP

DISPLAYOUTPUTLINK1

DISPLAYOUTPUTLINK0

1:2DisplaySplit

Display Output Unit (DOU)

Image Processing subsystem

Backend subsystem

Link 1Gamma, Dither,

RGB2YCbCr

Line Split,YCbCr4:2:0

FrameTiming,CMode

DOU 0

CU layer

Side-by-Side Split

Link 0

TEEXT / TETRIG

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Synopsys&ArmDisplaySolution

Synopsys&Arm

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Today’sPremiumSmartphone• Smartphoneapplication– WQHD+

Synopsys&Arm

SynopsysMIPIDSIHostController+D-PHY

℠

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AR/VRandFuturePremiumSmartphone• SmartphoneVRapplication– 4K+

Synopsys&Arm

SynopsysMIPIDSI+DSCHostControllerandD-PHY

VESADSCv1.1Encoder

4datalanes1clocklane

Mali-CetusDisplay

MIPIDSIHostController

v1.2

MIPID-PHYV1.2

VESADSCv1.1Encoder

Step33:1compression

2streamsat~4.44Gbps

Step14320x2160/90Hz/30bpp1streamat~26.6Gbps

[email protected]

2160x4320p90

Ecosystem

Armapplicationprocessor

Display

Driver


v1.2

MIPID-PHYV1.2

4datalanes1clocklane

Display

Driver

Step22streamsat~13.3Gbps

SameCLKforbothDPhystoavoiddrift

sync

454Mhz pixelclock

EmbeddedDisplay

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VESADisplayStreamCompression(DSC)EnablingUHDmobiledisplays• Visuallylosslesscompression

– Optimizedforcompressionfactorbetween2xand3x• Intra-frameConstantBitRate(CBR)encoder• Support8,10and12bitspercomponent• RGBandYCbCr 4:4:4• BasedonDeltaPulseCodeModulation(DPCM)

withanIndexedColorHistory(ICH)• Requiresasinglelineofpixelstorage&ratebuffer

Synopsys&Arm

ApplicationProcessor DSIHost&

DSCEncoder

MIPID-PHY

DisplayDriverIC

MIPIDSI&D-PHY

High-DefinitionDisplay

DPU

DSCDecoder

MIPIDSITransportLanes

VisuallyLossless

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DSCwithProvenMIPISpecifications

Synopsys&Arm

Resolution [email protected] [email protected]

Nocompression

2xcompression

3xcompression

Nocompression

2xcompression

3xcompression

FHD(1080x1920) 3.58Gbps 3lanes 2lanes 1lane 2lanes 1lane 1lane

WQHD(1440x2560) 6.37Gbps 6or8lanes 3lanes 2lanes 3lanes 2lanes 1lane

WQXGA(1600x2560) 7.08Gbps 6or8lanes 3lanes 2lanes 3lanes 2lanes 2lanes

UHD(2160x3840) 14.33Gbps N/A 6or8lanes 4lanes 6or8lanes 3lanes 2lanes

WQUXGA(2400x3840) 15.93Gbps N/A 6or8lanes 4lanes 8lanes 4lanes 3lanes

5K(2880x5120) 25.49Gbps N/A N/A 8lanes N/A 6or8lanes 4lanes

8K(4320x8192) 61.16Gbps N/A N/A N/A N/A N/A N/A

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SynopsysMIPIDSIHostControllerwithVESADSC1.1Fullyintegrated,cost-efficientsolutiontoenablesupportingultra-highresolutionsMIPIdisplays

• CompleteDesignWare MIPIDSIHostControllerwithVESADisplayStreamCompressionencoderandMIPID-PHYeasilyintegratesintoapplicationprocessorswithlessrisk

• Integrated MIPIdisplayIPreducesmemorysizeanddatatransmissionbandwidthtolowerpowerconsumption,areaaswellasEMI

• VESADSCencoderallowshigherrefreshratesbeyond60Hzfordrasticallyfasterresponsivenessandfluidityinultra-high-resolutionquadHDor4Kdisplays

Synopsys&Arm

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IntegratingMIPIDSI+VESADSC

Synopsys&Arm

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FrameBuffer

DualDSIWithoutDSCMIPID-PHY

Lanes

SDRAM SDRAM SDRAM

ApplicationProcessor


DisplayDriverIC

MIPID-PHY

MIPID-PHYMIPIDSIHostController

MIPID-PHY MIPIDSIDeviceController

MIPIDSIDeviceControllerMIPID-PHY

19


RemoveDSI/D-PHYwithIntegratedDSI/DSCIPSavePower,Area&Cost

• Remove– MIPID-PHYTx +DSICtrl

– MIPID-PHYRx+DSICtrl

MIPID-PHYLanes

SDRAM SDRAM SDRAM

FrameBuffer


MIPIDSIHost&DSCEncoderIP

DisplayDriverIC

MIPID-PHY




VESADSCDecoder

20


RemoveSDRAMswithIntegratedDSI/DSCIP

• Remove– SDRAM

MIPID-PHYLanes

SDRAM SDRAM SDRAM

FrameBuffer



DisplayDriverIC

MIPID-PHY




VESADSCDecoder

SavePower,Area&Cost

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SavePower,AreaandCostwithScalableArchitecture

• Lesspower

• Smallersystem• Lowercost

MIPID-PHYLanes

SDRAM

FrameBuffer



DisplayDriverIC

MIPID-PHY MIPID-PHY MIPIDSIDeviceController

VESADSCDecoder

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EnablingChallengingCOGConnectivity

Synopsys&Arm

• Chip-on-Glass(COG)offersathinprofile,integrateddisplay– Atthesametimehaslimitationsinsupportinghigh-switchingfrequencies

• VESADSCEncoderIPreducesdatatransmissionbandwidth• Allowsuseofexistinglowerswitching-speedsforhigher-resolutiondisplays

MIPIDSITransportLanes~0.9Gbps/lane



DisplayDriverIC

WQXGA

MIPID-PHY MIPID-PHY

x2VESADSCEncoder3.5Gbps

1600x2560x60fps7Gbps

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ReducingNumberofPinswithD-PHYv1.2

Synopsys&Arm

• D-PHYv1.2isgettingadoptedwidelywhichenable2.5Gbps/lane

• VESADSCEncoderIPreducesdatatransmissionbandwidth• Allowdrasticreductionin#ofpinsandpowerconsumption

• D-PHYv1.2capabledesignenablessystemflexibility

MIPIDSITransportLanes~2.3Gbps/lane



DisplayDriverIC

WQXGA

MIPID-PHY MIPID-PHY

x3VESADSCEncoder2.33Gbps

1datalane

24


Summary

Synopsys&Arm

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Arm/SynopsysProvideDetailedIntegrationGuidelines• Interfaceconnectivity,clockandresetcontrol• PixeldatatransferinMIPIDSIVideoModeforbothsingleand

duallink• VariablerefreshrateinMIPIDSIVideoMode• SynopsyseDPI interfaceandMIPICommandModeoperation• PixeldatatransferinMIPIDSICommandModeforbothsingle

andduallink• Dynamicresolutionchange• Partialupdate• VESADisplayStreamCompression(DSC)encoderintegration• Powercontrol

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Synopsys&ArmExample:ArmMaliDPUandSynopsysDSIHostControllerutilizingDPIinterface

HSYNCL00VSYNCL00

DATAENL00PXLDATARL00[9:0]PXLDATAGL00[9:0]PXLDATABL00[9:0]

DISPUSERL00[31:0]DISPREADYL00

FRAMESTARTL00

TEEXT0TETRIG0

DPIDATAENformatdependentconnectivity

DPIHSYNCDPIVSYNC

EDPIHALT

DPIPIXDATA

SynopsysDSIHostController

1'b01'b0

unusedunused

HSYNCL10VSYNCL10

DATAENL10PXLDATARL10[9:0]PXLDATAGL10[9:0]PXLDATABL10[9:0]

DISPREADYL10 1'b1unusedunusedunusedunusedunusedunused

PXLCLK0

ACLK

RESETn

ARMMali-CetusDPU

DPIPCLK

APBC

LK

LANEB

YTECLK

AXI/APBClockPLL

PRESETn

PixelClockPLL

LaneByteClockPLL

PPUwithResetController


Synopsys&ArmDisplaySolution• ArmandSynopsysensure

completeandoptimizedend-to-enddisplaysolutions

• ArmandSynopsysreducethecomplexitiesofporting&integrationbetweenappsprocessorandPHYs

• Jointapplicationnoteavailabletoourpartnersuponrequestprovidingconfigurationandintegrationguidelines

Synopsys&Arm

ApplicationProcessorSoC DisplayInterface

HDMI2.xControllerHDCP

DSCEncoder

MIPIDSIController

MIPID-PHYTX

HDMITX/WirelessArmMali

Display+

AssertiveDisplay

ExternalPanelSoC

HDMI/DPRXPHY TCON

HDMI/VESADPRX

ControllerHDCP

DDIC

DSCDecoder

EmbeddedPanelSoC

MIPID-PHY/VESAeDP RX

DDIC

DSCDecoder TCON

MIPIDSI/VESAeDP RX

Controller

TouchScreen

Controller

SupportedbySynopsys

PartiallySupportedbySynopsys

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hezi saar, sr. staff product marketing manager · 2018-01-17 · hezi saar, sr. staff product...

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