hb20p space evaluation final report

Property of ums. Distribution to third parties prohibited without written consent.

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Document Reference NE.32S.04781

Issue A

DOCUMENT PAPIER NON TENU A JOUR - DOCUMENT ELECTRONIQUE APPLICABLE

HARD COPY NOT UPDATED - ELECTRONIC DOCUMENT APPLICABLE IMPRIME LE / PRINTED ON : 05/09/03 13:33

European Space Agency ESTEC contract N°15907/01/NL/PA Centre Nationale d’Etudes Spatiales contract N° 721/00/8443/00

HB20P Space Evaluation Final Report

Revision of : 19 of June 2003

Author : G. Pataut / Auxemery

Data processing file reference : w: \ specif\32s\Ne\Ne04781.doc

Reason for change : Creation

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Last revision approved by:

Space Project Responsible : P. Auxemery

Production Manager : B. Delmas

Orsay Reliability Manager : G. Pataut

Quality Manager : M. Bonnet

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Approval for distribution: JP. Nivoliers


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Issue A

1. Scope.............................................................................................................................................. 4

2. Reference documents .................................................................................................................... 4

3. HB20P technology ........................................................................................................................ 5

3.1. General description............................................................................................................................. 5

3.2. Audit..................................................................................................................................................... 5

3.3. PID........................................................................................................................................................ 5

3.4. Capability............................................................................................................................................. 5

3.5. Construction analysis.......................................................................................................................... 6

4. qualification vehicles .................................................................................................................... 7

4.1. Test characterisation vehicle (TCV) ................................................................................................. 7

4.2. Dynamic evaluation circuit (DEC) .................................................................................................... 7

4.3. Representative integrated circuit (RIC) ........................................................................................... 8

5. ageing test plan ............................................................................................................................. 9

6. biasing and monitoring system................................................................................................... 11

7. manufacturing, inspection and assembly ............................................................................... 12

8. ageing test results..................................................................................................................... 13

8.1. Storage test ........................................................................................................................................ 13 8.1.1. Description............................................................................................................................................13 8.1.2. Test file K520711 (275°C) ...................................................................................................................13 8.1.3. Test file K320711 (300°C) ...................................................................................................................14

8.2. TCV DC Life tests ............................................................................................................................. 15 8.2.1. Description ...................................................................................................................................................15 8.2.2. Test file U2168B40 (HTRB)........................................................................................................................15 8.2.3. Test file U2166D04 (60°C) ..........................................................................................................................16 8.2.4. Test file U2167D06 (80°C) ..........................................................................................................................17

8.3. DEC step stress tests ......................................................................................................................... 18 8.3.1. Description ...................................................................................................................................................18 8.3.2. Test file U2165D05 (J stress).......................................................................................................................18 8.3.3. Test file U2164D05 (V stress)......................................................................................................................19

8.4. RF step stress tests ............................................................................................................................ 20 8.4.1. Description ...................................................................................................................................................20 8.4.2. Test file U2162D05 (Jmax)..........................................................................................................................20 8.4.3. Test file U2163D05 (Vmax).........................................................................................................................21

8.5. RIC Life test ..................................................................................................................................... 22 8.5.1. Description ...................................................................................................................................................22


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Issue A

8.5.2. Test file U2161D06 (25°C) .........................................................................................................................22 8.5.3. Failure analysis.............................................................................................................................................23

8.6. Electrostatic Discharge (ESD) test ................................................................................................. 24 8.6.1 Introduction ...................................................................................................................................................24 8.6.2 Main results and comments ...........................................................................................................................24 8.6.3 Conclusion.....................................................................................................................................................25

8.7. Radiations test U2169R00 ................................................................................................................ 26

9. Ageing test analysis and interpretation...................................................................................... 27

9.1 Passive components: .......................................................................................................................... 27

9.2 Active components:............................................................................................................................ 28

10. Conclusion of reliability testing................................................................................................ 31

11. USER RECOMMENDATION ................................................................................................. 32

12. Space evaluation conclusion .................................................................................................... 33


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Issue A

1. SCOPE

This document describes the results of the evaluation test program designed for the Space Evaluation of the process HB20P. The purpose of this program is to assess the reliability and the capability domain of the HB20P process.

This program consists in design, manufacturing and testing under stress conditions, three test vehicles types. These vehicles are namely TCV (Technological Characterisation Vehicle), DEC (Dynamic Electrical Circuit) and RIC (Representative Integrated Circuit).

2. REFERENCE DOCUMENTS • PID Process HB20P_O&HB20P_R

Reference document: RD.20S.6700.1

• Process Sequence HB20P Reference document: SP.13S.01981.1

• Acceptance criteria for I3 test - HB20P Reference document: SP.20S.6705.1

• Acceptance criteria for RF test - HB20P Reference document: SP.20S.6706.1

• Process flow - HB20P Reference document: SP.20S.6702.1

• SPC parameters - HB20P Reference document: SP.20S.6703.1

• Reliability and Qualification Reference document: IG 09.03 Issue B

• Technological characterization vehicle (TCV) for process HB20P Technical note: PHA2901 Issue B

• Dynamic Evaluation Circuit (DEC) for process HB20P Technical note: PHA4999 Issue B

• Representative Integrated Circuit (RIC) for process HB20P Technical note: PHA3901 Issue B

• Evaluation test plan for process HB20P_R Reference document: NE32S.XXX Issue A

• Design Manual HB20P Reference document: DB.13S.00071 Issue A


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Issue A

3. HB20P TECHNOLOGY

3.1. General description

Process HB20P_R is based on a 2µm emitter width heterojunction bipolar transistor (HBT) technology. The major features of this process are the following: • HBT MOCVD active layer with embedded etch stop • 2µm emitter width • 250pF/mm2 silicon nitride MIM capacitors • Evaporated gold used for interconnects, lines... • 100µm wafer thickness • Air-bridges and via-holes HB20P_R has been characterised and modelled up to 25GHz. The result of this work forms the HB20P_R Design manual (reference number: DB13S00071 A) and associated CAD libraries, which are used by both UMS internal designers and foundry customers. Front-side wafer processing is carried out at the Ulm site of UMS. At the Orsay site, the wafer backside processing and the component testing are carried out. The description of the process is given in the HB20P_R Process Flow SP.20S.6702.1.

3.2. Audit

The agencies (CNES/ESA/CELAR) have carried out an audit in June 2002, at ULM. Findings and observations have been pointed out and corrective actions have been done by UMS and submitted to the agencies.

3.3. PID

The HB20P_R technology is described in the H20P_R PID (Process Identification document. reference number: RD.20S.6700.1). This document contains the list of all the necessary documents for the manufacturing of HB20P_R wafers. (Description of process, acceptance criteria, process flow, SPC parameters, Epitaxial specification, ...)

3.4. Capability

The HB20P_R process is dedicated for the manufacturing of amplifiers up to Ku_Band. 10 W X-Band amplifier has been realized and is available with the reference CHA7010 in the UMS catalogue product.


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Issue A

3.5. Construction analysis Construction analyses are regularly done by UMS during front-side manufacturing following the internal UMS procedure “Cross section analysis HB20P_O and HB20P_R. In addition constructions analysis have been done on 4 chips from 2 wafers used for this programme. The work was subcontracted to TRT (Thales Research and Technologies). The following analyse have been done: - Optical and SEM observation - Cross-section - Dry etching on cross-section

In parallel, CELAR (French MOD laboratory) has also done construction analysis on chips from wafer used for the space evaluation.

Thermal drain

Emitter contact Base contact Collector contact

Transistor cross section


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Issue A

4. QUALIFICATION VEHICLES

4.1. Test characterisation vehicle (TCV)

The TCV has been designed to DC evaluate the reliability of the GaAs foundry process HB20P. This pattern features elementary representative components from the HB20P design library, as described in the document (Technological characterisation vehicle (TCV) for process HB20P Technical note: PHA2901 Issue B)

4.2. Dynamic evaluation circuit (DEC) The DEC is a prematched transistor designed for on wafer measurement in power operating mode. The DEC is assembled in a microwave (bmh) package. A detailed DEC description is given in document: DYNAMIC EVALUATION CIRCUIT (DEC) FOR PROCESS HB20P Technical note PhA4999


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Issue A

4.3. Representative integrated circuit (RIC) The RIC is a 2 stages high power amplifier in X-band. This circuit has been designed by THALES/UMS. The detail specification of this circuit is given in document: REPRESENTATIVE INTEGRATED CIRCUIT (RIC) FOR PROCESS HB20P Detail specification PhA3901


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Issue A

5. AGEING TEST PLAN

The following tests that have been done are summarised here below:

20TCVMicrowave HBT

Tj=300°C

20TCVMicrowave HBT

Tj=275°C

Storage A1 A2

10TCVVbe=0V Vce=10VPassives at max

Tj=200°C

10TCVVce=7V

Jce=66kA/cm²Tj=286°C Ta=60°C

DC life-test B1 B2 B3

10TCVVce=7V

Jce=66kA/cm²Tj=255°C Ta=60°C

10DECVce=8V

Jce=15kA/cm² to 75kA/cm²Ta=25°C

10DECVce=8V to 12VJce=33kA/cm²

Ta=25°C

DC step stress C1 C2

4DECVce=10V

Jce=33kA/cm² (Imax)Ta=25°C

4DECVce=8V

Jce=60kA/cm²Ta=25°C

RF step stress D1 D2

20RICTj=236°CVCE=8V

Jce=33kA/cm²

DC life-test E

3RICConstruction analysis

Construction F

10 TCV

Radiation G

3 RIC

ESD H

2 wafers TCV and microwace HBT measurements at :0, 24, 48, 168, 500, 1000, 2000h or 50% of failure

TCV measurements at : 0, 24, 48, 168, 500, 1000, 2000h

5 current steps of 15kA/cm²9 voltage steps of 0.5Vstep duration: 168h

RF power: 0dB, 1dB, 3dB, 5dB, 7dB gain compressionStep duration 168h

DC + RF measurements at : 0, 24, 48, 168, 500, 1000, 2000, 3000, 4000h

Subcontracted by UMS

Done by CNES

Subcontracted to SERMA TECHNOLOGY


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Issue A

The different bias points assessed by this evaluation programme are reported below on the

Ice-Vce characteristic of the HB20P transistor:

Vce

Ice 120kA/cm² 100kA/cm² 80kA/cm² 60kA/cm² 40kA/cm² 20kA/cm² 0kA/cm²

RIC Tj=200°C

TCV HBT Tj=TBD

0 4 8 12 16

TCV HBT Tj=250°C Tj=275°C

DEC HBT Ta=25°C

DEC HBT Ta=25°C

TCV Varactor Tj=250°C Tj=275°C


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Issue A

6. BIASING AND MONITORING SYSTEM

All DC life-tests were performed using a system, which provides independent voltage supplies (Vbe and Vce), for each device. In addition, all currents and voltages for all devices were controlled and monitored during the ageing tests.

This system also enables the definition of alarms and/or limits for all parameters; device biasing can be automatically cut off when limits are reached, thus avoiding component destruction. A description of the system architecture is given below.

° °

°°

Biasing modules(24 i n drawer)

6 DIL24 sockets i n biasing cardDRAWER

TEST CHAMBER

MONITORING SYSTEM (PC)

RS432

- Monitoring of Ibe, Vbe, Vce- Variation tracking parameters

Life-test system


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Issue A

7. MANUFACTURING, INSPECTION AND ASSEMBLY The test vehicles are implemented into two masks-set named “TITAPIAZ” and “DUNE”. “TITAPIAZ” contains DEC and TCV. “DUNE” contains RIC. One “TIAPIAZ” wafer contains 580 potential TCV and 400 potential DEC. One “DUNE” wafer contains 50 potential RIC. 2 wafers of TITAPIAZ were used for storage test: K320711 K520711

2 wafers of TITAPIAZ were tested for DC life-test:

K320713 (substrate supplier 1) K320714 (substrate supplier 2)

6 wafers of DUNE were tested: K341011, K341012, K341013 (substrate supplier 1) K341014, K341015, K340116 (substrate supplier 2)

The following operations has been done:

Wafer Lot manufacturing PCM OK

On wafer test vehicle measurement

Electrical sorting

Dicing, 100% visual inspection, picking

Assembly in package Subcontracted to Edgetek for

DEC and TCV Done at UMS for RIC

+ part numbering

Precap inspection UMS quality + CNES

Initial measurement in package

Aging test lot definition


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Issue A

8. AGEING TEST RESULTS

8.1. Storage test

8.1.1. Description

Storages are done at high temperature to evaluate the stability of the metallurgical levels of the Heterojunction Bipolar Transistor process; so, the metal diffusion mechanisms are evidenced. Two storages were implemented at 275°C and 300°C to assess the activation of the mechanisms with respect to the temperature.

8.1.2. Test file K520711 (275°C)

The storage at 275°C was done with the wafer 1R53 of the lot Titapiaz K52071 for 3000h. The complete results are presented in the "HB20P_Space Annexes" document and summarized in the table here after:

Criteria Initial value Cell Parameter Symbol Unit min MAX drift % min MAX

δ final drift %

TLMCC Square resistance

R [] col Ω / [] 10 30 ± 20% 10,7 10,89 < ± 5

TLMCC Contact resistance

Rc col Ω . mm - 0,3 (1) 0,024 0,035 < 0,075

TLMBC Square resistance

R [] bas Ω / [] 150 250 ± 20% 220 232 < ± 5

TLMBC Contact resistance

Rc bas Ω . mm - 0,3 (1) 0,12 0,15 < 0,21

RTaN Square resistance

R [] TaN Ω / [] 26 34 ± 20% 29,7 31,4 < +3

RHrW Square resistance

R [] HrW Ω / [] 800 1200 ± 20% 998 1073 < +3

HBT Current gain

Beta - 25 100 ± 20% 64,7 73,3 < ± 2

HBT Emitter resistance

Re Ω 6 12 ± 20% 11,5 13,7 < ± 3

HBT Collector resistance

Rc Ω 0 10 ± 20% 6,6 7 > -16

HBT Saturated Vce voltage

Vcesat Volts 0,1 0,3 ± 20% 0,13 0,15 > -5

BC diode Ideality factor

n - - 2 ± 20% 1,77 1,84 < ± 5

Inductor Self resistance

Rl Ω 10 20 ± 20% 15,1 16,3 < 52

Capacitor Capacitance

Ccap pF / mm² 220 280 ± 20% 243 258 < ± 1

(1) no drift defined; under maximum value required

For the TLMCC, some sites at the edge of the wafer are not taken into account as measurement artefacts affect them - not seen on previous results with PCM storages. No valid reason has been found for the inductance increase, which was not observed on the HTRB test at 33kA/cm² and an ambient temperature of 200°C.

So, the behaviour of the active and passive elements is considered satisfactory after this storage of 3000h at 275°C.


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Issue A

8.1.3. Test file K320711 (300°C)

The storage at 300°C was done with the wafer 1R18 of the lot Titapiaz K32071 for 3000h. The complete results are presented in the "HB20P_Space Annexes" document and summarized in the table here after :


δ final drift %


R [] col Ω / [] 10 30 ± 20% 17,4 17,9 < ± 8


Rc col Ω . mm - 0,3 (1) 0,03 0,034 < 0,2


R [] bas Ω / [] 150 250 ± 20% 199 214 < ± 7


Rc bas Ω . mm - 0,3 (1) 0,13 0,16 < 0,24


R [] TaN Ω / [] 26 34 ± 20% 28,5 33,2 > -6,4


R [] HrW Ω / [] 800 1200 ± 20% 1023 1075 < +2

HBT Current gain

Beta - 25 100 ± 20% 65 77 < +9,5


Re Ω 6 12 ± 20% 7,1 8,2 -3 / +10


Rc Ω 0 10 ± 20% 8,5 9 -4 / +11


Vcesat Volts 0,1 0,3 ± 20% 0,1 0,11 > -4


n - - 2 ± 20% 1,65 1,79 < ± 6


Rl Ω 10 20 ± 20% 16 19,5 < 53


Ccap pF / mm² 220 280 ± 20% 253 268 < +1


The ohmic contact of the TLMBC is normally accelerated by temperature as a metal diffusion mechanism, so activation energy of 1,8eV was established taken into account the 275°C storage and a drift criterion of +20%.

The ohmic contact on the TLMCC is also accelerated by temperature even if an abnormal increase appeared after 500h. With a drift criterion of +15%, activation energy of 1,94eV is found which is also typical for a metal diffusion mechanism.

A 50% drift is observed for the inductance as for the 275°C storage with no visual impact on the inductance integrity even with polarized light.

So, the behaviour of the active and passive elements is considered satisfactory after this storage of 3000h at 300°C.


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Issue A

8.2. TCV DC Life tests

8.2.1. Description

The DC life tests on TCV assessed, in accelerated conditions (J=66kA/cm²), the functionality of the transistor at two temperatures.

Functionality of the transistor in blocked condition (Vbe=0) is assessed by HTRB (High Temperature Reversed Bias) test, while the passive components are stressed at one or two times their maximum values.

8.2.2. Test file U2168B40 (HTRB) The HTRB test at 200°C was done with 10 parts equally shared between the wafer 3R87

(Supplier 1) and the wafer 4R5 (Supplier 2) of the lot Titapiaz K32071 for 2000h. The HBT parts were biased at Vce = 10Volts with Vbe = 0Volt while the passive elements were biased at their maximum values. The complete results are presented in the "HB20P_Space Annexes" document and summarized in the table here after:


δ final drift %


R [] col Ω / [] 10 30 ± 20% 15,67 17,44 < ± 1


Rc col Ω . mm - 0,3 (1) 0,017 0,030 < 0,035


R [] bas Ω / [] 150 250 ± 20% 200 213 < ± 1


Rc bas Ω . mm - 0,3 (1) 0,1 0,15 < 0,16


R [] TaN Ω / [] 26 34 ± 20% 28,2 29,5 < ± 1


R [] HrW Ω / [] 800 1200 ± 20% 954 1092 < ± 2

HBT Current gain

Beta - 25 100 ± 20% 40,2 74,3 < ± 6


Re Ω 6 12 ± 20% 7,5 9,7 < ± 3,5


Rc Ω 0 10 ± 20% 3,9 4,6 < ± 6,5


Vcesat Volts 0,1 0,3 ± 20% 0,11 0,14 > -5


n - - 2 ± 20% 1,63 1,77 < ± 7,5


Rl Ω 10 20 ± 20% 14,3 14,7 < +4


Ccap pF / mm² 220 280 ± 20% 246 266 < ± 1


All the drifts are low whatever the active or the passive elements. Only one TaN resistor failed after 168h due to a current overload on the BILT system. No difference was observed between parts whatever the wafer origin Supplier 1 or Supplier 2.

So, the behaviour of the active and passive elements is considered satisfactory after this High Temperature Reversed Bias test at 200°C.


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Issue A

8.2.3. Test file U2166D04 (60°C)

The DC Life test at an ambient temperature of 60°C was done with 10 TCV parts equally shared between the wafer 3R87 (Supplier 1) and the wafer 4R5 (Supplier 2) of the lot Titapiaz K32071 for 2000h. The active parts (Tj = 255°C°) were biased at Vce = 7Volts and Ice = 40mA (J = 66kA/cm²) while the passive elements were biased at two times their maximum values. The complete results are presented in the "HB20P_Space Annexes" document and summarised in the table here after:


δ final drift %


R [] col Ω / [] 10 30 ± 20% 15,8 17,4 < ± 1


Rc col Ω . mm - 0,3 (1) 0,02 0,03 < 0,031


R [] bas Ω / [] 150 250 ± 20% 201 210 < ± 1


Rc bas Ω . mm - 0,3 (1) 0,08 0,16 < 0,16


R [] TaN Ω / [] 26 34 ± 20% 27,9 29,7 < ± 1


R [] HrW Ω / [] 800 1200 ± 20% 976 1044 < ± 1

HBT Current gain

Beta - 25 100 ± 20% 50,8 72,1 +4 / -22


Re Ω 6 12 ± 20% 7,4 9,7 < 18,4


Rc Ω 0 10 ± 20% 3,9 4,4 > -9


Vcesat Volts 0,1 0,3 ± 20% 0,10 0,14 -2 / +5,8


n - - 2 ± 20% 1,66 1,77 -2 / +5,5


Rl Ω 10 20 ± 20% 14,2 14,6 < ± 1


Ccap pF / mm² 220 280 ± 20% 255 266 < ± 1


For the Beta results in the table above, only the drift values are taken into account. And from the cumulative percentage of failed parts over time, a Median Time to Failure (t50%) of 18 715h with a shape parameter σ = 1,8 is calculated using the Lognormal distribution.

Nearly no drift is observed for the passive components at two times the maximum current, so that the previous reliability results obtained with other UMS processes are confirmed.

So, the behaviour of the active and passive elements is considered satisfactory after this DC Life test at an ambient temperature of 60°C.


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Issue A

8.2.4. Test file U2167D06 (80°C)

The DC Life test at an ambient temperature of 80°C was done with 10 TCV parts equally shared between the wafer 3R87 (Supplier 1) and the wafer 4R5 (Supplier 2) of the lot Titapiaz K32071 for 2000h. The active parts (Tj = 286°C) were biased at Vce = 7Volts and Ice = 40mA (J = 66kA/cm²) while the passive elements were biased at their maximum values. The complete results are presented in the "HB20P_Space Annexes" document and summarized in the table here after:


δ final drift %


R [] col Ω / [] 10 30 ± 20% 15,7 17,3 < ± 1


Rc col Ω . mm - 0,3 (1) 0,024 0,029 < 0,028


R [] bas Ω / [] 150 250 ± 20% 199 214 < ± 1


Rc bas Ω . mm - 0,3 (1) 0,09 0,14 < 0,13


R [] TaN Ω / [] 26 34 ± 20% 28 29,7 < ± 1


R [] HrW Ω / [] 800 1200 ± 20% 946 1049 < ± 1

HBT Current gain

Beta - 25 100 ± 20% 48 73 -6 / +10


Re Ω 6 12 ± 20% 7,7 9,8 < +25


Rc Ω 0 10 ± 20% 3,9 4,3 > -13


Vcesat Volts 0,1 0,3 ± 20% 0,11 0,14 < 10,5


n - - 2 ± 20% 1,69 1,76 < ± 2


Rl Ω 10 20 ± 20% 14,2 14,6 < + 1


Ccap pF / mm² 220 280 ± 20% 252 271 < ± 1


The four Re drifts over 20% concerned Supplier 1 parts which have a lower initial Re by 2Ohms, so that it comes a Median Time to Failure (t50%) of 2696h with a shape parameter σ = 0,512. Two of them are also related to Beta failures leading to a t50% of 3559h with a shape parameter σ = 0,655. Taken into account the DC test file at Ta = 60°C, an activation energy of 1,36eV is evidenced for the Beta failures with a drift criterion of ± 20%.

Nearly no drift is observed for the passive components biased at their maximum current, so that the previous reliability results obtained with other UMS processes are confirmed.

So, the behaviour of the active and passive elements is considered satisfactory after this DC Life test at an ambient temperature of 80°C.


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Issue A

8.3. DEC step stress tests

8.3.1. Description

The DEC step stress tests are done to assess the maximum current density Jce at the nominal Vce voltage (8Volts) and the maximum voltage Vce at the nominal current density (33kA/cm²). The RF behaviour is checked with RF step stress tests (next paragraph) based on the threshold values Jce_max and Vce_max determined by these DC step stress tests.

8.3.2. Test file U2165D05 (J stress) This DC step stress test at ambient temperature 25°C was done with 10 DEC parts equally

shared between the wafer 3R87 (Supplier 1) and the wafer 4R5 (Supplier 2) of the lot Titapiaz K32071. The transistors were biased at Vce = 8 Volts while the Jce current density was increased from 15kA/cm² to 75kA/cm² each 168h. The complete results are presented in the "HB20P_Space Annexes" document and summarized in the table hereafter:

Criteria Initial value δ Drift % or dB Test Parameter Symbol Unit min MAX drift min MAX 15kA /

cm² 30kA /

cm² 45kA /

cm² 60kA /

cm²

δ final drift

Static Base-Emitter Voltage

Vbe Volt 1,3 1,6 ± 20% 1,46 1,49 -0,134 0,068

-0,201 0

-0,402 0,410

-0,402 2,46

-81 3,63

Static Emitter Resistance

Re Ω 0,3 2,5 ± 20% 0,76 1,28 -2,34 1,71

-3,91 2,63

-5,47 0

-5,79 1,32

-30 11

Static Collector Resistance

Rc Ω 0,8 2 ± 20% 1,8 1,9 -0,55 0,56

-2,11 2,16

-5,79 -2,78

-4,97 -2,63

-52 -4,3

Static Current Gain

Beta - 20 100 ± 20% 55 67 -0,4 11

5,3 17

-7,9 16

-14 12

-92 3698

RF Collector-Emitter Current

Ice mA 20 200 ± 20% 115 127 -2,68 6.61

5,65 17

-9,14 17,5

-15,8 4,12

-92 39

RF Output Power

Pout dBm - 28 1dBm 20,9 23,1 -0,12 0,62

0,27 1,6

-0,62 1,68

-1,6 0,63

-23 -1,85

RF Associated Gain

Gass dB 4 - 1dB 3,8 6,7 -0,8 0,7

-0,8 0,8

-1,1 0,5

-2,4 0,1

-10 -1,9

The Re values lower on Supplier 1 parts drifted less than the Supplier 2 parts inducing the

decrease of the Vbe values. Less important, the same behaviour was observed on Rc and Vbc parameters, so that 4 Supplier 2 parts out of 5 are dead after the step 60kA/cm². The reference device was broken during the interim measurements but the reference device of the U2164D05 test assured the reproducibility of the measurements. The Beta drifts after the step 60kA/cm² confirmed this maximum current density. In the RF measurements, the Ice drifts are also out of specification at the final step of 75kA/cm² while the Pout and Gain drifts (min and MAX values) are both out of criteria at this final step. Two Supplier 1 and one Supplier 2 parts are less affected as already seen above with the DC parameters. From that DC step stress test, a maximum current density of 60kA/cm² is deduced when the devices are biased at the nominal Vce voltage (8Volts).


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Issue A

8.3.3. Test file U2164D05 (V stress)

This DC step stress test at ambient temperature 25°C was done with 10 DEC parts equally shared between the wafer 3R87 (Supplier 1) and the wafer 4R5 (Supplier 2) of the lot Titapiaz K32071. The transistors were biased at Jce = 33kA/cm² while the Vce voltage was increased from 8Volts to 12Volts each 168h. The complete results are presented in the "HB20P_Space Annexes" document and summarized in the table hereafter:

Criteria Initial value δ Drift % or dB Test Parameter Symbol Unit min MAX drift min MAX 8Volts 9Volts 10Volts 11Volts

δ final drift


Vbe Volt 1,3 1,6 ± 20% 1,46 1,49 -0,20 -0,07

-0,27 0

-0,20 0,14

-0,27 0,34

-74 0,14


Re Ω 0,3 2,5 ± 20% 0,76 1,22 -3,8 -1,3

-4,2 2,6

-5 -0,9

-4,96 6,3

-92 6,4


Rc Ω 0,8 2 ± 20% 1,79 1,87 -2,2 -1,1

-3,8 -2,2

-4,3 -2,8

-4,8 -2,2

-150 -2,8

Static Current Gain

Beta - 20 100 ± 20% 56 69,5 -1,2 14,5

2,1 16

-5,8 17,5

-53 20

-100 -


Ice mA 20 200 ± 20% 112 123 4,4 14,1

-0,4 17,4

-5,2 17,3

-32 20

-100 32

RF Output Power

Pout dBm - 28 1dBm 21,1 22,8 0,3 1,2

0,1 1,48

-0,45 1,78

-2,77 2,15

-3,7 0,33

RF Associated Gain

Gass dB 4 - 1dB 4,3 8,2 -0.97 0,74

-0,97 0,62

-0,77 0,54

-0,93 0,36

-1,08 0,08

After the step 11 Volts, two Re values on Supplier 1 parts lower than the Supplier 2 parts started to drift inducing the decrease of the Vbe values. At the same time, the Rc values also drifted but with few differences between the Supplier 1 and Supplier 2 parts.

The Beta drifts clearly start with the device N°10 after 10 Volts if device N°33 is not taken into account because of its early failure after 8,5 Volts during the step stress in relation with a BILT problem. In the RF measurements, the Ice drift is also out of specification after the 10 Volts step for the device N°10 while the Pout decrease is under the limit at the same step. Other drifts are observed after 11 Volts. The same two Supplier 1 parts are dead as already seen above with the DC parameters after 11 Volts and a third device after the 11,5 Volts step. Gain drift is lower comparing to output power drift because the output power is correlated to Ice current. From this DC steps stress test, a maximum collector-emitter voltage Vce=10 Volts is deduced when the devices are biased at the nominal current density (33kA/cm²).


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8.4. RF step stress tests

8.4.1. Description

These step stress tests are done to assess the RF behaviour under high compression level of DEC circuits biased either at the previous maximum current density Jcemax and the nominal collector-emitter voltage Vce=8Volts, or at the previous maximum collector-emitter voltage Vcemax and the nominal current density Jce=33kA/cm². The RF conditions started from linear up to 1dB, 3dB, 5dB and 7dB gain compression level for 168h at each step.

8.4.2. Test file U2162D05 (Jmax)

This RF step stress test at ambient temperature 25°C and a frequency of 10,7GHz was done with 4 DEC parts equally shared between the wafer 3R87 (Supplier 1) and the wafer 4R5 (Supplier 2) of the lot Titapiaz K32071. The transistors were biased at Jce = 50kA/cm² with a nominal collector-emitter voltage Vce=8Volts while the RF input power was increased from linear gain condition up to 7dB gain compression level each 168h; It was not possible to bias the DEC at Jcemax = 60kA/cm² with RF signal and with enough gain compression. The complete results are presented in the "HB20P_Space Annexes" document and summarized in the table here after:

Criteria Initial value δ Drift % or dB Test Parameter Symbol Unit min MAX drift min MAX linear 1dB 3dB 5dB

δ final drift


Vbe Volt 1,3 1,6 ± 20% 1,47 1,49 -0,4 0,07

0,07 0,34

-0,27 -0,07

- -


Re Ω 0,3 2,5 ± 20% 0,77 1,21 -5,2 -3,85

-5 -2,6

-5,9 -3,3

- -


Rc Ω 0,8 2 ± 20% 1,78 1,84 -4,9 -2,2

-6,5 -4,5

-3,3 -2,25

- -

Static Current Gain

Beta - 20 100 ± 20% 55,4 66,7 -5,3 14

-3,9 5,3

-5 -3,3

- -


Ice mA 20 200 ± 20% 113 121 -5,97 12,8

-4,74 8,15

-7,7 -5,43

- -

RF Output Power

Pout dBm - 28 1dBm 21,3 22,8 -0,15 1,06

-0,18 0,85

-0,23 0,17

- -

RF Associated Gain

Gass dB 4 - 1dB 6,2 8,07 0,27 0,74

0,33 0,71

0,39 0,84

- -

The DC parameters Re, Rc, Vbe have low drifts even if the behaviour is different between

Supplier 1 parts which failed after 1dB gain compression level (the lowest Re values) and Supplier 2 parts which failed after 3dB gain compression level.

The Beta drifts started to be positive for Supplier 1 parts before failure after 1dB gain compression level while the Beta drifts are low for Supplier 2 parts with Re values around 1,1 to 1,2Ohms.

The kinetic seen on Beta parameter is also found on the RF parameters: the collector current Ice and the output power Pout. The gain and output power drifts are less than 1dB for the two Supplier 2 parts up to 3dB gain compression level.

From this RF step stress test, a maximum gain compression level of 3dB is deduced when

the devices with Re over 1Ohm are biased at the nominal collector-emitter voltage Vce=8Volts with a current density maximum of 50kA/cm².


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8.4.3. Test file U2163D05 (Vmax)

This RF step stress test at ambient temperature 25°C and a frequency of 10,7GHz was done with 4 DEC parts equally shared between the wafer 3R87 (Supplier 1) and the wafer 4R5 (Supplier 2) of the lot Titapiaz K32071. The transistors were biased at Vcemax = 10 Volts with a nominal current density Jce=33kA/cm² while the RF input power was increased from linear gain condition up to 7dB gain compression level each 168h. The complete results are presented in the "HB20P_Space Annexes" document and summarized in the table hereafter:

Criteria Initial value δ Drift % or dB Test Parameter Symbol Unit min MAX drift min MAX linear 1dB 3dB 5dB

δ final drift


Vbe Volt 1,3 1,6 ± 20% 1,47 1,49 0 0,2

0,13 0,34

0,06 0,07

0 0,134

0,26 0,27


Re Ω 0,3 2,5 ± 20% 0,77 1,2 -5 -2,6

-4,2 -2,6

-3,3 -1,7

-3,3 -2,6

-3,3 -2,6


Rc Ω 0,8 2 ± 20% 1,8 1,84 -3,26 -2,73

-3,8 -2,8

-3,3 -2,8

-3,3 -2,8

-7,8 -7,2

Static Current Gain

Beta - 20 100 ± 20% 56 66 8 15,3

13,2 13,8

11,8 12,7

11 12

10,8 11,4


Ice mA 20 200 ± 20% 115 122 7,9 12,7

6,6 13,9

5,6 6,9

5,4 6,4

4,9 6

RF Output Power

Pout dBm - 28 1dBm 21,3 22,8 0,73 1,13

0,8 1,26

0,64 0,72

0,71 0,81

0,67 0,78

RF Associated Gain

Gass dB 4 - 1dB 5 7,7 0,21 1,28

0,3 1,41

1,39 1,42

1,27 1,29

1,23 1,25

Like in the DC step stress test in current, the two Supplier 1 devices failed before the two Supplier 2 parts in the 1dB step for one device and in the 3dB step for the other. The Re difference between parts (+50% for Supplier 2 devices) evidenced here again that an emitter resistance over 1Ohm is important to sustain a high power level. The two Supplier 2 parts have successfully finished the RF step stress test after 7dB compression level without exceeding a Beta drift of +15,3%. The Beta kinetic is also found on the collector-emitter current Ice and the output power Pout with less than 1dB drift up to 7dB compression level for the parts N°38 and N°40. For the gain curve, the measurement artefact took place between the initial measurements (step -1) and first interim measurements (step 0) but then considering drifts up to 7dB compression level, they are less than 0,25dB.

From this RF step stress test, a maximum gain compression level of 7dB is deduced when the devices with Re over 1Ohm are biased at the nominal current density of 33kA/cm² with a maximum collector-emitter voltage Vce=10Volts.


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8.5. RIC Life test

8.5.1. Description This DC life test was carried out on a Representative Integrated Circuit (RIC) at nominal operating bias condition: a High Power Amplifier of 37dBm output power and 13dB gain when biased at Vce=8Volts with a collector-emitter current Ice=2,3A. The objective is to determine the failure rate of a MMIC of typical use for HB20P_R at Jce=33kA/cm² and nominal voltage Vce.

8.5.2. Test file U2161D06 (25°C)

This DC life test at ambient temperature 25°C was done with 20 RIC parts equally shared between the wafer 3R91 (Supplier 1) and the wafer 4R32 (Supplier 2) of the lot Dune K34101. The complete results are presented in the "HB20P_Space Annexes" document and summarized in the table here after:

Criteria Initial value Test Parameter Symbol Unit min MAX drift min MAX

δ drift


Ice A 1,5 3 ± 20% 1,66 1,93 -6,9 3,9

RF Output Power at 10GHz

Pout dBm 36 - 1dBm 36,71 38,25 -2,0 -0,33

RF Associated Gain

Gass dB 11 - 1dB 12,7 14,2 -1,14 -0,33

The drifts do not take into account the failed devices during the life test that are 3 Supplier 1 devices and 4 Supplier 2 devices. The repartition of the drifts and failures during the life test is presented in the table below:

DUT Wafer origin

Event time ( hours )

Conditions of the occurrence δ Pout drift

Failure mode

J7 Supplier 1 103 Temperature alarm on the BILT system - accidental J8 Supplier 1 960 Rapid Ice increase up to short-circuit - mode 1 J9 Supplier 1 173 DC power measurement artefact - accidental J16 Supplier 2 4000 Low degradation of Pout and gain -1,14 dB mode 2 J19 Supplier 2 2558 Failure after monitored Ice decrease - mode 2 J22 Supplier 2 342 Catastrophic failure during life time - mode 1 J24 Supplier 2 134 Catastrophic failure during life time mode 1 J26 Supplier 2 3000 Degradation of Pout and gain before failure -2 dB mode 2 J28 Supplier 2 24 DC power measurement artefact - accidental T12 Control device 960 DC power measurement artefact - accidental

Apart from the fact that some problems occurred due to the difficulties on one side to do DC high power measurements on HBT circuits and on another side to implement a life test of 20 HPA dissipating 18,5W each, two failure modes were evidenced as presented in the next paragraph. The failure mode 1 corresponds to a catastrophic failure mode characterized by a strong increase of the Ice current followed by the device destruction. The second mode 2 is more related to a degradation of the performances sometimes leading to the device destruction.


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8.5.3. Failure analysis The overall six failures of the RIC life test could be analysed by fitting the cumulative percentage of failures versus time with a Lognormal distribution having a Median Time to Failure (t50%) of 19 785h and a scale parameter σ=1,293 as presented on the graph left below.

But as already seen the 3 earliest failures (mode 1) are very different of the last 3 other failures (mode 2). A separate fitting for "mode1" and "mode2" of the cumulative percentage of failures versus time with a Lognormal distribution gives a Median Time to Failure (t50%) of 31 970h for "mode1" with a scale parameter σ=1,473 and a Median Time to Failure (t50%) of 9176h for "mode2" and a scale parameter σ=0,35 as presented on the graph right above.

A failure analysis performed on two parts with "mode1" mechanism showed some non-brazed areas under the failed HPA's leading to a locally higher junction temperature responsible for the burst of the Ice current. This is well correlated with two facts: the failures are randomly distributed with a large-scale parameter σ=1,473 and the failures "mode1" came earlier between 100h and 1000h. More than the HB20P_R technology, the assembly looks involved in the "mode1" thermally induced mechanism.

Failure analysis performed on parts with “mode 2”, the more deterministic (σ=0,35) mechanism, did not evidence transistor process difficulties because Base-emitter alignment is good and ledge passivation well done. This failure mechanism looks also thermally activated (non-brazed areas evidenced) but failures occurred in the same time range than TCV failures (U2166D04) taking into account a Black coefficient m = 1,9 previously evidenced. Then, a Median Time to Failure (t50%) of 588 478h (67 years) is obtained at Tj = 175°C with an activation energy of 1,36eV.


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8.6. Electrostatic Discharge (ESD) test

8.6.1 Introduction ESD test has been subcontracted to “SERMA TECHNOLOGIES St Egréve France”. Serma technology is an independent laboratory that operates in conformance to requirements specification in the standards ISO9002 and EN45001. ESD test has been performed on three MMIC’s modules according to the Human Body Model. The aim was to determine their sensitivity through different voltage steps and I-V measurements during the experiment progress.

8.6.2 Main results and comments

The three modules returned the following results for three pin configurations choose as the most sensitive (Input access versus bias supplies Collector or Base, Output access versus ground and Collector bias supply versus Base bias supply): Ref. Module

Pin Applied Stress Voltage Level Voltage Level inducing Failure

In vs Vc & Vb 50V to 300V with 50V steps, 400V, 500V, 1kV 1kV Vc vs Vb Same as above then 1.5kV to 4kV with 0.5kV

steps None

V20

Out vs Gnd Same as for Vc None

In vs Vc & Vb 500V to 1kV with 100V steps, 1.5kV 1.5kV Vc vs Vb Same as above then 2kV to 4kV with 0.5kV

steps None

P20

Out vs Gnd 500V 500V

In vs Vc & Vb 100V to 1.2kV with 100V steps 1.2kV Vc vs Vb 100V to 1.2kV with 100V steps then 1.5kV to

4kV with 0.5kV steps None

G20

Out vs Gnd 100V to 400V with 100V steps 400V

Bipolar Transistor: No failure was measured with Vc pin when stressed up to 4kV Input pin: Failure is measured with input pin between 1kV and 1.5kV for the three devices, they withstand between 500V (V20 module) and 1.1kV (G20 module), by considering the last voltage level without I-V evolution Output pin: The first stressed module (V20) returned no failure after 4kV, but this result was not confirmed with P20 module where 50V as the first stress voltage induced a failure. Modules G20 confirmed the result from P20 with a failure returned after 40V, since no evolution was measured after 300V.


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8.6.3 Conclusion

The test has been carried out on 3 RICs. Input capacitance in the RF port failed after 1kV and output capacitance failed at 400V (class 1). The transistor has not failed after 4kV (class 3) applied on the base or on the collector. Those results are better than those in general given for GaAs devices and are in agreement with those obtained previously on FET processes.

Susceptibility of Electronic Components to ESD Device type ESD susceptibility (Volts) VMOS 20 – 1200 Mosfet,GaAsfet, EPROM 100 – 300 JFET 150 – 7000 OP-AMP 190 – 2500 Schottky diodes 300 – 2500 Film Resistors 300 – 3000 Schottky TTL 1000 - 2500


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8.7. Radiations test U2169R00

Radiation tests are done to assess the sensitivity of the HB20P process to burn out caused by heavy ions. The tests were carried out in the Institut de Physique Nucléaire (Orsay – France) in February 2003 (1). The approach decided was to test one component in the worse conditions (Particle with the highest energy, fluence of 107 particles/cm², bias Vce = 10 V and Vbe = 0V) and, in case of failure, reduce the energy (type of ions) and/or the voltage on other components. In case no failure is observed, confirm the behaviour with a second part in the same conditions. The first step was done using Iodine (127I, LET (Si) = 60 MeV/mg/cm²), which is the most energetic particle available in the facility. No failure occurred at 200 MeV. The test was repeated at 256 MeV and again no failure occurred. This sequence was repeated on a second TCV without failures. Those results confirm the hardness of the process in blocked conditions (Vbe = 0), which is believed to be a worst case.

(1)This test originally planned in November 2002 was postponed due to a failure of the equipment (Tandem Van de Graff).


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9. AGEING TEST ANALYSIS AND INTERPRETATION

9.1 Passive components:

Passive components were already tested in the frame of HP07, PH15 and PH25 space evaluation. The results presented in this reliability programme confirm those previously obtained.

TaN resistor:

Test conditions are reported here below

Temperature 200°C 80°C 60°C Current Imax=0.45mA/µm

Imax

Imax

2xImax

This component was tested up to 2xImax 250°C in the frame of PH25 space

evaluation without any failure. HRW resistor:


Temperature 200°C 80°C 60°C Current Imax=0.4mA/µm

Imax

Imax

2xImax

This component was tested up to 3xImax 200°C in the frame of PH25 space

evaluation without any failure. Capacitor:


Temperature 200°C 80°C 60°C Voltage Vmax=15V

Vmax

Vmax

2xVmax

No failure as in the HP07 Space Evaluation


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Inductor:


Temperature 200°C 80°C 60°C Current Imax=11mA/µm

Imax

Imax

1,5xImax

Drifts on the inductor resistance have been observed in storage at high temperature

275°C and 300°C but no failure was observed in the other DC life tests; these results are coherent with the previous ones obtained in the HP07 Space Evaluation (200°C; 1,3Imax).

9.2 Active components:

Diode base collector (Varactor):


Temperature 200°C 80°C 60°C Voltage -8V -8V -8V

No failure (Breakdown > 24Volts)

Transistor: • Storage test at 275°C and 300°C

No drift on Beta. Drifts are observed on base and collector resistance due to metal diffusion. Activation energies of 1,8eV for base contact and 1,94eV for collector contact have been determined. • HTRB at 200°C, VCE=10V and Vbe=0V

No drift for active and passive components at their maximum values. • DC life-test


Temperature 255°C 286°C Voltage Imax= 33kA/cm²

7V - 66kA/cm²

7V - 66kA/cm²

Drifts of Beta current gain are observed correlated with the lowest Re values. From

the Beta failure mechanism, activation energy of 1,36eV was deduced. The bias supply situated on the graph below shows that this point is in the vicinity of the thermal runaway area.


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Issue A

0

0,01

0,02

0,03

0,04

0,05

0,06

0,07

0,08

0 2 4 6 8 10 12 14

CollectorV(1)

CollectorV(2)

CollectorV(3)

CollectorV(4)

CollectorV(5)

CollectorV(6)

CollectorV(7)

CollectorV(8)

CollectorV(9)

CollectorV(10)

CollectorV(11)

CollectorV(12)

• DC step stress test

- DC current step stress : Upper limit current density of Jce = 60kA/cm² at Vce=8V. - DC voltage step stress : Upper limit voltage of Vce = 10 V at Jce=33kA/cm²

DC step stress tests have shown that the limit in current is mainly determine by thermal runaway area.

DEC TITAPIAZN°32

0,0E+00

1,0E-01

2,0E-01

3,0E-01

4,0E-01

5,0E-01

6,0E-01

0,0 2,0 4,0 6,0 8,0 10,0 12,0 14,0

VCE (Volt)

Ice

A

0,0

20,0

40,0

60,0

80,0

100,0

120,0

140,0

160,0

Jce

kA/c

m²

1µA1mA2mA3mA4mA5mA6mA7mA8mA9mA10mA11mA12mA

DEC TITAPIAZN°32

0,0E+00

1,0E-01

2,0E-01

3,0E-01

4,0E-01

5,0E-01

6,0E-01

0,0 2,0 4,0 6,0 8,0 10,0 12,0 14,0

VCE (Volt)

Ice

A

0,0

20,0

40,0

60,0

80,0

100,0

120,0

140,0

160,0

Jce

kA/c

m²

1µA1mA2mA3mA4mA5mA6mA7mA8mA9mA10mA11mA12mA

Thermal run away area


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• RF step stress test - Test N°1 Vce=8V Ice=180mA (Jce=50kA/cm²) ¾ 2 parts with low Re (6,5Ohms for 1x2x30µm) are functional up to 1dB gain compression ¾ 2 parts with high Re (9,3 Ohms for 1x2x30µm) are functional up to 3dB gain

compression. - Test N°2 Vce=10V Ice=120mA (Jce=33kA/cm²) ¾ 2 parts with low Re (6,5Ohms for 1x2x30µm) are functional up to 1dB gain compression ¾ 2 parts with high Re (9,3 Ohms for 1x2x30µm) are functional up to 7dB gain

compression

DEC TITAPIAZ

N°32

0,0E+00

1,0E-01

2,0E-01

3,0E-01

4,0E-01

5,0E-01

6,0E-01

0,0 2,0 4,0 6,0 8,0 10,0 12,0 14,0

VCE (Volt)

Ice A

0,0

20,0

40,0

60,0

80,0

100,0

120,0

140,0

160,0

Jce kA/cm²

1µA

1mA

2mA

3mA

4mA

5mA

6mA

7mA

8mA

9mA

10mA

11mA

12mA

DEC

0,0E+00

1,0E-01

2,0E-01

3,0E-01

4,0E-01

5,0E-01

6,0E-01

0,0 2,0 4,0 6,0 8,0 10,0 12,0 14,0

VCE (Volt)

Ice

A

0,0

20,0

40,0

60,0

80,0

100,0

120,0

140,0

160,0

Jce

kA/c

m²

1µA

1mA

2mA

3mA

4mA

5mA

6mA

7mA

8mA

9mA

10mA

11mA

12mA

Thermal run away area

Highest Re

RF step stress

The RF step stress tests have shown that transistors with emitter resistances of 9Ω can operate up to 7dB of gain compression level when Vce = 10V at the maximal design value for Jce=33kA/cm².

• ESD sensitivity

The test was successful up to 4kV (Class 3) applied on the base or on the collector. Class 1 was reached for RF Input and Output ports. These results are better than those in general given for GaAs devices and are in agreement with the tests previously implemented on FET processes.


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10. CONCLUSION OF RELIABILITY TESTING

In order to achieve the very demanding reliability objectives for power applications at X-Band, the complete HB20P_R process has been thoroughly optimised during the past years. Over 100 power transistors have been stressed at accelerated conditions (Elevated junction temperature and current densities). Tests up to 10 000 hours have been done at UMS plant.

Based on these results CNES and ESA have decided to launch the space evaluation of the GaAs MMIC process HB20P_R. The goal was to well known the margin of the process and to determine the failure mechanisms and associated activation energies. Wear out mechanism:

Two metal contact diffusions have been pointed out on storages: Collector contact and Base contact. Activation energies of 1,94eV for Collector contact and 1,8eV for Base contact have been deduced. So that a worse case value for the Median Time to Failure (t50%) is found above 110 years at Tj = 175°C.

From the DC accelerated tests, the failure mechanism on Beta parameter was evidenced with an activation energy of 1,36eV inducing a Median Time to Failure (t50%) above 440 years at Tj = 175°C when biased at two times the maximum Jce current density.

Current gain degradation is linked to current density and follows the black law with an m factor of 1,9 (previously checked).

ESD tests were implemented showing that HB20P transistors are not more sensitive than other GaAs components. The results are similar to those previously obtained on FET processes.

Maximum ratings:

The results on the passive elements have confirmed the previous results obtained in the frame of the Space Evaluation of UMS HP07, PH15 and PH25 processes. The DC and RF life tests showed that the limits presented in the design manual are conservative in terms of reliability. ¾ The DC step stress tests have evidenced that thermal runaway limits the operating area to a

current density of 60kA/cm² and to a voltage of 10Volts. ¾ The RF step stress test confirmed that the HB20P transistor with an emitter resistance of 9Ω

(for 1 finger of 2x30µm²) can operate up to 7dB of gain compression level at Vce=10V and Jce=33kA/cm².

High reliability:

4000 hours of tests have been done on an X-Band high power amplifier. This circuit was designed to operate in pulse mode at Vce=8V and Jce=33kA/cm² in large signal, with a maximum dissipated power of 10W. In this programme it has been put in CW conditions with a dissipated power of 18,5W and a junction temperature of 235°C. Several parts failed during the test, but mainly due to a bad assembly (voids in the solder between the chip and the carrier). However 11 parts reached 4000 hours without any drift and a Median Time to Failure (t50%) of 67 years is obtained at Tj = 175°C with an activation energy of 1,36eV.


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11. USER RECOMMENDATIONS It has been demonstrated that HB20P UMS process is a high reliable process. However it is recommended that devices operate in safe operating area of voltage, current and temperature. For passive components, MIM capacitor, inductor, line and metallic resistor, it is recommended to not exceed the maximum ratings defined in the design manual. For the active components, the maximum recommended operating conditions are 9V of collector emitter voltage and 33kA/cm² of collector emitter current density (1).

(1) 20mA for one emitter finger of 30µm length.

For those bias conditions the thermal stability of the transistor is ensure by the intrinsic emitter resistance and transistor can operate at least up to 7dB of gain compression. Nevertheless this is strongly dependant of the transistor output load. At transistor level, it is indeed recommended that the peak RF voltage swing never exceed 25V during all operating conditions.

Worst Load line

Better Load line

VCE

ICE

9 V

33kA/cm²

25V max

Whatever operating conditions, it is also recommended to not exceed 175°C of transistor junction temperature. Following those recommendations, device lifetime should fulfilled space and military requirements. Exceeding those values of current, voltage and temperature should decrease device lifetime, but device will not necessary burn out suddenly. Lowering voltage, current and temperature will increase device lifetime.

It has also been demonstrated that devices from the HB20P are less sensitive to ESD than GaAs FET devices. Nevertheless, the same rules shall be applied (see UMS Handling and mounting Recommendations)


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12. SPACE EVALUATION CONCLUSION

UMS HB20P_R is the first GaInP/GaAs HBT process suitable for high power application that has been space evaluated.

This evaluation was carried out under ESA and CNES contracts with the participation of CELAR DGA technical laboratory (French ministry of defence).

Three test vehicles designed by UMS were used including an X-Band HPA of 8W of output power. Ageing accelerated tests in temperature, current, voltage and RF signal were carried out in order to determine the main failure mechanisms and associated activation energies. A lifetime test up to 4000 hours was also carried out. The electrical behaviour of HB20P transistor versus ESD and radiation was investigated.

Detailed technological and failure analysis were carried out by Thales Research Laboratory and CELAR. A technological audit was done in June 2002 at ULM by ESA, CNES and CELAR.

HB20P Reliability, Manufacturing and Quality results are compliant with UMS targets.

hb20p space evaluation final report

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