hawawini yaun darwish malhotra fir

7/28/2019 Hawawini Yaun Darwish Malhotra Fir

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Boxcar FIR Filter

Shadi Hawawini

Pearl Yuan

Amr Darwish

Karun Malhotra

Advisor: Dr. ParentMay 8, 2006


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Agenda

Abstract

Introduction

Why Simple Theory

Background Information

Summary of Results

Project (Experimental) Details Results

Cost Analysis

Conclusions


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Abstract

We designed a 4-bit Finite Impulse Response(FIR) Filter that operates at 200 MHz

Impulse Response - A set of FIR coefficients,which represent all possible frequencies.

Tap - A coefficient/delay pair. The number of FIRtaps is an indication of the amount of memoryrequired to implement the filter.


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Introduction

One of the most fundamental elements for a DSP

system is an FIR Filter.

There is no feedback, which results in a finite outputvalue of zero.

The filter is mathematically expressed using the

following difference equation:

P

i

i inxbny0

)()(


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FIR Block Diagram

The FIR Filter consist of three main components:

1) A D Flip-Flop to implement a simple delay.

2) A Multiplier to implement the coefficients, which in our casewe are using a Boxcar filter, meaning all coefficients are 1.

3) A Full adder to sum the nodes at the end of each Tap.


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Longest Path Calculations

PHL

5ns

18 .28ns

CELL BIT# WN Load W P Load Ln Load Lp Load Cg or Cin of load N M WN WP

(cm) (cm) (cm) (cm) F cm cmxor2 1 6.00E-05 6.00E-05 2.0000E-14 6 6 4.26E-04 7.38E-04

xor2 2 4.26E-04 7.38E-04 6.00E-05 6.00E-05 1.9536E-14 6 6 4.21E-04 7.28E-04

NAND2 (Slave) 3 4.21E-04 7.28E-04 6.00E-05 6.00E-05 1.9267E-14 1 2 3.51E-04 3.15E-04

Driver Mux (Slave) 4 3.51E-04 3.15E-04 6.00E-05 6.00E-05 1.1185E-14 1 3 1.57E-04 1.57E-04

NAND2 (Master) 5 1.57E-04 1.57E-04 6.00E-05 6.00E-05 5.2613E-15 1 2 3.06E-04 2.76E-04

Driver Mux (Master) 6 3.06E-04 2.76E-04 6.00E-05 6.00E-05 9.7671E-15 2 2 2.27E-04 4.03E-04














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Schematic


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Layout


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Successful DRC check


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Successful Extraction Report


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Successful LVS Report


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Successful LVS Report cont.


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Simulations


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Simulation


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Simulation


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Post Extraction


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Post Extraction cont.


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Propagation Delay Waveform


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Propagation Delay


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Cost Analysis

Estimated time spent on each phase of the

project:

Verifying Logic = 2 weeks

Verifying Timing = N/A

Layout = 15 hours

Post Extracted Timing = 5 hours


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Lessons Learned

A project of this nature requires ample time

to complete it, before its deadline.

Verify logic of individual components.

Extra care needed when designing the

layout.


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Summary

Because FIR Filters are such an importantelement of DSP design, it was beneficial to

do a project like this to strengthenunderstanding of the concept

A low cost, easy to implement Boxcar FIR

filter was designed and tested Due to the nature of DSP, FIR filters of

some form will always be needed.


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Acknowledgements

Dr. Parent, for teaching us not to

overcomplicate our designs.

hawawini yaun darwish malhotra fir

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