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EE 3770: Logic and Digital Design

Instructor: Dr. Yong Y. Li

Spring 2012

Class Hours:LEC MWF 12:00-12:52 pm EGH 0308DIC Tu 12:00-12:52 pm EGU 0308

LAB L1 Th 1:00-2:52 pm EGH 0310LAB L2 Th 3:00-4:52 pm EGH 0310

Office:EGH 0320Phone 342-1238e-mail li@uwplatt.edu

Office Hours:M 9:00-10:00 11:00-12:00 1:00-3:00W 9:00-10:00 11:00-12:00 1:00-3:00F 9:00-10:00 11:00-12:00

1 Textbooks1. Fundamentals of Logic Design 6th Edition by Ruth

2. Digital Design by Vahid

2 Catalog DataNumber system, Boolean algebra, Design of Combinational and sequential logic circuits.

3 Course outline:Introduction (1 Class)Number systems and Conversion (2 Classes)Boolean Algebra (3 Classes)

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Minterm and Maxterm (2 Classes)Karnaugh Map (2 Class)Combinational Circuit Design (2 Classes)Multi-level Gate Circuits (2 Classes)Multiplexers, Decodes (2 Classes)Introduction to VHDL (3 Classes)Latches and Flip-Flops (3 Classes)Registers and Counters (2 Classes)Analysis of Clocked Sequential Circuits (2 Classes)Derivation of State Graphs and Tables (3 Classes)VHDL for Digital System Design (3 Classes)Sequential Circuit Design Topic (3 Classes)

4 Grading PolicyThis course includes homework, Lab assignments, three midterms, a project and a nal exam.Distribution is as follows:

Homework Assignments 15%Firmware Project 15%Lab Assignments 20%Three Tests 30%Final Exam 20%

Final Score:A = 90-100B = 80-89C = 70-79D = 60-69F = below 60

5 Homework, Lab, Design Project and Test PoliciesHomework: I consider homework to be an important part of the learning process. Assignments

will be made on schedule. Submission dates for homework assignments are specied. Latesubmissions will not be accepted.

It is suggested that the student work other problems from the texts, to further prepare forexams.

Lab: All lab assignments are individual small project assignments.

For each lab, a checkoff appointment will be made for each student.

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During the lab checkoff time, each student should turn in his/her lab report whichincludes

Late lab assignments penalty will be 15% per working day up to 45% maximum. You must complete all of the lab assignments to pass this course.

Project: The nal project must be a state machine design. It includes

Proposal

Progress report

Oral presentation and formal report.

You must complete your project to pass this course.

Test: Dates for all midterm examinations and the nal examinations are posted. It is yourresponsibility to take the examinations at the indicated times. Makeup examinations willbe reluctantly offered only for situations of severe medical and personal problems.

6 Computer Usage:1. OrCAD/SDTIII is used for schematics capture and wiring connection references.

2. Altera QUARTUS II is used for schematics capture, simulations, Hardware DescriptionLanguage (VHDL), and design implementation.

3. Programming Design using Altera DE-1 Board

7 Estimated Contents

Engineering Science: 3 credits

Engineering Design: 1 credits

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EE 3770 Logic and Digital DesignInstructor: Dr. Yong Y. Li

Spring 2012

Date Week Subject AssignmentJan. 23 1 IntroductionJan. 24 1 Discussion Jan. 25 1 Number System and ConversionJan. 27 1 Number System and ConversionJan. 30 2 Addition, Subtraction, ComplimentJan. 31 2 Discussion Feb. 1 2 BCD, Gray Code Due HW #1Feb. 3 2 Boolean AlgebraFeb. 6 3 Boolean Algebra,

Feb. 7 3 Discussion Feb. 8 3 Truth table, Minterm, Maxterm Due HW #2 Feb. 10 3 Karnaugh MapFeb. 13 4 Karnaugh Map, Using NAND GateFeb. 15 4 Using NOR Gate, Different Implementations Due HW #3 Feb. 16 4 Due Lab #1Feb. 17 4 Introduction to MSIFeb. 20 5 Mid-Term #1Feb. 22 5 Introduction to MuitiplexerFeb. 23 5 Due Lab #2Feb. 24 5 Introduction to Decoder

Feb. 27 6 Timing, HazardFeb. 29 6 Buffer, Encoder, ROM Due HW #4Mar. 1 6 Due Lab #3Mar. 2 6 Adder, Lab ImplementationMar. 5 7 Programmable Logic DevicesMar. 8 7 Mid-Term #2 Due HW #5 Mar. 7 7 Due Lab #4Mar. 9 7 Introduction to VHDLMar. 12 8 Introduction VHDLMar. 13 8 Discussion Mar. 14 8 VHDL Dataow

Mar. 16 8 VHDL StructureMar. 19 9 No Class Mar. 21 9 Spring BreakMar. 23 9 No Class

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EE 3770 Logic and Digital DesignInstructor: Dr. Yong Y. Li

Spring 2012

Date Week Subject AssignmentMar. 26 10 Conditional concurrent Signal AssignmentMar. 27 10 Discussion Mar. 28 10 Latch, Flip-op Due HW #6 Mar. 30 10 Flip-FlopsApr. 2 11 VHDL Sequential CircuitApr. 3 11 Flip-Flops ApplicationsApr. 4 11 Discussion Apr. 6 11 April Break Apr. 9 12 Analysis of Clocked Sequential Circuits

Apr. 11 12 State Machine Due HW #7 Apr. 12 12 Due Lab #5Apr. 13 12 State Machine Application Example Due Project ProposalApr. 16 13 State Machine ImplementationApr. 17 13 Discussion Apr. 18 13 State Machine Design Example Due HW #8 Apr. 20 13 Sequential Circuit VHDLApr. 23 14 State MachineApr. 24 14 Discussion Apr. 25 14 Midterm # 3Apr. 27 14 Design Example Due Progress Report

Apr. 30 15 State SimplicationMay 1 15 Discussion May 2 15 Equivalent StateMay 4 15 SM ChartMay 7 16 Summary of Design ProcedureMay 9 16 Final project preparationMay 10 16 Final Project DemonstrationMay 11 16 ReviewMay 14 17 Final Exam. for 12:00 MWF ClassMonday 1:00-2:52 pm.

EGH 0308

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Dr. Yong Y. LiOffice: EGH 0320 Tel: (608)342-1238 e-mail: li@uwplatt.edu

January 23 May 11, Spring 2012

MO TU WE TH FR8:008:309:00 Office Office Office9:30 Hour Hour EE 4720 Hour

10:00 EE 4720 EE 4720 LAB EE 472010:30 EGH 0307 EGH 0307 EGH 0310 EGH 030711:00 Office Office Office11:30 Hour Hour Hour12:00 EE 3770 DIS 3770 EE 3770 EE Dept. EE 377012:30 EGH 0308 EGH 0308 EGH 0308 Meeting EGH 03081:00 EE 37701:30 Office Office L12:00 Hours Hours EGH 03102:303:00 EE 37703:30 L24:00 EGH 03104:305:005:30

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