handout #1: the xilinx ise foundation softwaremarko/complab_s_rup13/handouts.pdf · handout #1: the...

Computer Structure lab http://www.eng.tau.ac.il/~marko

Handout #1: The Xilinx ISE Foundation Software

The assignment in this lab is to practice design entry (schematic and HDL) and

simulation using the Project Navigator.

First part of the design is fully given to you. The second part requires new design

with similar specifications. In order to be prepared for the lab please read the tutorial of

the Xilinx ISE Foundation software under the link of the lab.

1.1 Important links:

1. The following link contains explanation about the FPGA chip we are going to

work on: http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf

1.2 Detailed Instructions:

1.2.1 Part I

The simple project decoder presented in the introductory meeting is given to you.

You may view it in order to see what your design should look. Start the design manager

and open the project. The project consists of a counter (designed using VHDL), a D flip

flop and AND-gate. Top level of the design is defined as schematic type. Parts of the

project are the 'decoder_t.vhd and counter4_t.vhd files, with the simulator environment

definitions (input signals with their waveforms). Start the ISIM simulator using the given

files. Check the performed simulation, add more signals to waveforms for observation. At

the end create new project, like or very similar to the one that was given to you.

1.2.2 Part II

Create a new project with the following properties:

Family: Spartan 3,

Device: XC3S1000,

Package: FT256,

Speed:-4,

Top-Level: Schematic,

Synthesis Tool: XST,

Simulator: ISIM (VHDL, Verilog),

Preferred Language: VHDL.

Implement the following design:

Inputs: clk, go, reset

Outputs: RA[3:0], RB[3:0]

Hardware: counters, registers; control logic

Functionality: your design should include two counters and two registers. First is 4-bit

positive counter named POINTER, second – a 16-bit negative counter named INFO.

Notice that a positive counter should start at 0 and count upwards, while a negative

counter starts at FFFF and counts downwards. �� signal initiates the counters, but

they begin and count only when signal GO is presented.

Your design should include two 4-bit registers. They sample the data from the counter

INFO as follows: REGA sample INFO [5:2] whenever the number represented by

POINTER [3:0] is smaller than 8 and REGB should sample INFO [9:6] whenever the

number represented by POINTER [3:0] is larger then 7. Design’s outputs are the

registers outputs.

Create VHDL Test Bench file with the following parameters:

Clk = 100/100 ns, Propagation Delay time = 2 ns,

Simulate the design when RESET is asserted at the beginning as positive pulse for at list

2 clock periods and after that the GO signal for number of pulses, that is enough to

observe correctness of the data sampled by the registers. Check the reaction when RESET

is asserted in the middle of the simulation.

1.3 Lab assignment:

Please do not submit your work Consult the correctness of your design with the

Instructor.

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

AA

BB

CC

DD

D(3:0)

clk

cnt_ce

cnt_rst

CDQ

FD

clk

AND2

D(3)

D(2)

pulseCF

pulseDO

counter4

clk

ce

rst

cnt(3:0)

counter4.vhd Wed Jul 04 09:36:46 2012

Page 1

1 library IEEE;

2 use IEEE.STD_LOGIC_1164.ALL;

3 use IEEE.STD_LOGIC_ARITH.ALL;

4 use IEEE.STD_LOGIC_UNSIGNED.ALL;

5

6 -- Uncomment the following lines to use the declarations that are

7 -- provided for instantiating Xilinx primitive components.

8 --library UNISIM;

9 --use UNISIM.VComponents.all;

10

11 entity counter4 is

12 Port ( clk : in std_logic;

13 ce : in std_logic;

14 rst : in std_logic;

15 cnt : out std_logic_vector(3 downto 0));

16 end counter4;

17

18 architecture Behavioral of counter4 is

19 signal cnt_s: std_logic_vector(3 downto 0);

20 begin

21

22 process(clk, ce)

23

24 begin

25 if (rst = '1') then cnt_s <= "0000";

26 elsif (ce = '0') then cnt_s <= cnt_s;

27 elsif (clk'event and clk = '1') then cnt_s <= cnt_s + 1;

28 else cnt_s <= cnt_s;

29

30 end if;

31 end process;

32

33

34 cnt <= cnt_s;

35

36

37 end Behavioral;

38

decoder_t.vhd Wed Jul 04 09:38:39 2012

Page 1

1 -- Vhdl test bench created from schematic D:\projects\a_dlx\decoder_v14\decoder.sch -

Tue Jul 03 12:57:04 2012

2 --

3 -- Notes:

4 -- 1) This testbench template has been automatically generated using types

5 -- std_logic and std_logic_vector for the ports of the unit under test.

6 -- Xilinx recommends that these types always be used for the top-level

7 -- I/O of a design in order to guarantee that the testbench will bind

8 -- correctly to the timing (post-route) simulation model.

9 -- 2) To use this template as your testbench, change the filename to any

10 -- name of your choice with the extension .vhd, and use the "Source->Add"

11 -- menu in Project Navigator to import the testbench. Then

12 -- edit the user defined section below, adding code to generate the

13 -- stimulus for your design.

14 --

15 LIBRARY ieee;

16 USE ieee.std_logic_1164.ALL;

17 USE ieee.numeric_std.ALL;

18 LIBRARY UNISIM;

19 USE UNISIM.Vcomponents.ALL;

20 ENTITY decoder_decoder_sch_tb IS

21 END decoder_decoder_sch_tb;

22 ARCHITECTURE behavioral OF decoder_decoder_sch_tb IS

23

24 COMPONENT decoder

25 PORT( clk : IN STD_LOGIC;

26 cnt_ce : IN STD_LOGIC;

27 cnt_rst : IN STD_LOGIC;

28 pulseCF : OUT STD_LOGIC;

29 pulseDO : OUT STD_LOGIC

30 );

31

32 END COMPONENT;

33

34 SIGNAL clk : STD_LOGIC;

35 SIGNAL cnt_ce : STD_LOGIC := '0';

36 SIGNAL cnt_rst : STD_LOGIC := '1';

37 SIGNAL pulseCF : STD_LOGIC;

38 SIGNAL pulseDO : STD_LOGIC;

39

40

41 BEGIN

42

43 UUT: decoder PORT MAP(

44 clk => clk,

45 cnt_ce => cnt_ce,

46 cnt_rst => cnt_rst,

47 pulseCF => pulseCF,

48 pulseDO => pulseDO

49

50 );

51

52 -- *** Test Bench - User Defined Section ***

53

54 CLK_process :process

55 begin

56 CLK <= '0';

decoder_t.vhd Wed Jul 04 09:38:39 2012

Page 2

57 wait for 100 ns;

58 CLK <= '1';

59 wait for 100 ns;

60 end process;

61

62 tb : PROCESS

63 BEGIN

64 WAIT FOR 202 ns;

65 cnt_rst <= '0';

66 cnt_ce <= '1';

67 WAIT FOR 200*10 ns;

68 WAIT; -- will wait forever

69 END PROCESS;

70 -- *** End Test Bench - User Defined Section ***

71

72 END;

73

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conter4_t.vhd Wed Jul 04 09:37:57 2012

Page 1

1 --------------------------------------------------------------------------------

2 -- Company:

3 -- Engineer:

4 --

5 -- Create Date: 10:48:58 07/03/2012

6 -- Design Name:

7 -- Module Name: D:/projects/a_dlx/decoder_v14/conter4_t.vhd

8 -- Project Name: decoder_v14

9 -- Target Device:

10 -- Tool versions:

11 -- Description:

12 --

13 -- VHDL Test Bench Created by ISE for module: counter4

14 --

15 -- Dependencies:

16 --

17 -- Revision:

18 -- Revision 0.01 - File Created

19 -- Additional Comments:

20 --

21 -- Notes:

22 -- This testbench has been automatically generated using types std_logic and

23 -- std_logic_vector for the ports of the unit under test. Xilinx recommends

24 -- that these types always be used for the top-level I/O of a design in order

25 -- to guarantee that the testbench will bind correctly to the post-implementation

26 -- simulation model.

27 --------------------------------------------------------------------------------

28 LIBRARY ieee;


30

31 -- Uncomment the following library declaration if using

32 -- arithmetic functions with Signed or Unsigned values

33 --USE ieee.numeric_std.ALL;

34

35 ENTITY conter4_t IS

36 END conter4_t;

37

38 ARCHITECTURE behavior OF conter4_t IS

39

40 -- Component Declaration for the Unit Under Test (UUT)

41

42 COMPONENT counter4

43 PORT(

44 clk : IN std_logic;

45 ce : IN std_logic;

46 rst : IN std_logic;

47 cnt : OUT std_logic_vector(3 downto 0)

48 );

49 END COMPONENT;

50

51

52 --Inputs

53 signal clk : std_logic := '0';

54 signal ce : std_logic := '0';

55 signal rst : std_logic := '0';

56

57 --Outputs

conter4_t.vhd Wed Jul 04 09:37:57 2012

Page 2

58 signal cnt : std_logic_vector(3 downto 0);

59

60 -- Clock period definitions

61 constant clk_period : time := 200 ns;

62

63 BEGIN

64

65 -- Instantiate the Unit Under Test (UUT)

66 uut: counter4 PORT MAP (

67 clk => clk,

68 ce => ce,

69 rst => rst,

70 cnt => cnt

71 );

72

73 -- Clock process definitions

74 clk_process :process

75 begin

76 clk <= '1';

77 wait for clk_period/2;

78 clk <= '0';

79 wait for clk_period/2;

80 end process;

81

82

83 -- Stimulus process

84 stim_proc: process

85 begin

86

87 -- hold reset state for 2 clock periods.

88 rst <= '1';

89 ce <= '0';

90 wait for 2 ns;

91 wait for clk_period;

92 rst <= '0';

93 ce <= '1';

94 wait for clk_period*20;

95 rst <= '1';

96 wait for clk_period;

97 rst <= '0';

98 wait for clk_period*8;

99 -- insert additional stimulus here

100

101 wait; -- will wait forever

102 end process;

103

104 END;

105


Handout #2: The RESA-2’s Parallel Bus

Consider a CPU that wants to communicate over the RESA-2 bus as a master

device. The CPU is connected to the RESA-2 bus via a simple bus interface. The simple

bus interface is placed on the FPGA between the CPU and to the RESA-2 bus.

Communication between the CPU and the bus interface is implemented by 3 registers and

3 control signals. The functionality of the registers is as follows:

R_DI: a data-in register through which data is fed to the CPU

R_DO: a data-out register through which data is sent from the CPU

R_AD: an address register that is written by the CPU

The control signals are as follows:

rd_req: the signal is sent by the CPU to the bus interface. This signal indicates that the

CPU wishes to initiate a read transaction.

wd_req: the signal is sent by the CPU to the bus interface. This signal indicates that the

CPU wishes to initiate a write transaction.

done: the signal is sent by the bus interface to the CPU. This signal indicates the

completion of a transaction.

For example, a read transaction is implemented as follows: When the CPU wishes

to read data from a slave, it writes the address (combined addresses of the slave and the

data item) to the address register R_AD and sets the rd_req signal to “1” for one clock

cycle. The bus interface, handles the request, and initiates a read transaction over the

RESA-2 bus. When data is fetched, it is stored by the bus interface in the data-in register

R_DI, and the done signal is set to “1” for one clock cycle.

2.1 Pre-Lab Assignment

1. Describe how a write transaction takes place.

2. Draw the datapath, registers and drivers of the bus interface.

3. Design the control logic of the bus interface. Write the equations for: register

clock enable signals, the output enable signals of drivers and all the RESA-2 bus

signals.

4. Draw the timing diagram of all the signals described above in the bus interface for

read transaction and write transaction

2.2 Lab Assignment

Project “Buses” is in your Lab working directory and contains 3 symbols: a CPU, a Slave

and Buf Interface. The CPU initiates read or write transactions to the Slave, depending on

the input control signals R_instr and W_instr..The Buf Interface macro is empty and your

task is to design it.

1. Design the Bus Interface symbol (design entry). Submit a printout of your

schematics and VHDL designs.

2. Simulate the project “Buses” using ready Buses_t.vhd file. The input waveforms

are: clk with 200ns period, propagation delay 2 ns, reset active high during the

first two clock periods, single pulse step_en in periods of 2000(4000) ns. Before

the simulation constant OPERATION have to be set with value of the desired

operation. Submit a printout of your simulation for a read and write transaction

including register and buffer control signals.

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

AA

BB

CC

DD

cpu

RESET

CLK

step_en

DONE

DI(31:0)

busy

rd_req

wr_req

sts(3:0)

READD(31:0)DO(31:0)

AO(31:0)

R_instr

W_instr

bus_inf

AO(31:0)

DO(31:0)

rd_req

wr_req

ACK_N

D(31:0)

A(31:0)

DI(31:0)

DONE

WR_N

AS_N

busy

in_init

CLK

RESET

READD(31:0)

STS(3:0)

step_en

SLAVE

slave_set

clk

WR_N

AS_N

A(31:0)

D(31:0)

ACK_N

in_init

R_instr

W_instr

cpu.vhd Wed Jul 04 09:39:56 2012

Page 1

1 library IEEE;


3 use IEEE.STD_LOGIC_ARITH.ALL;

4 use IEEE.STD_LOGIC_UNSIGNED.ALL;

5

6 -- Uncomment the following lines to use the declarations that are

7 -- provided for instantiating Xilinx primitive components.

8 --library UNISIM;


10

11

12 entity cpu is

13

14 Port ( RESET : in std_logic;

15 CLK : in std_logic;

16 step_en : in std_logic;

17 R_instr : in std_logic;

18 W_instr : in std_logic;

19 sts : out std_logic_vector(3 downto 0);

20 READD: out std_logic_vector(31 downto 0);

21 DI : in std_logic_vector(31 downto 0);

22 DO : out std_logic_vector(31 downto 0);

23 AO : out std_logic_vector(31 downto 0);

24 busy : out std_logic;

25 rd_req : out std_logic;

26 wr_req : out std_logic;

27 DONE : in std_logic);

28 end cpu;

29

30 architecture Behavioral of cpu is

31

32

33 signal state:std_logic_vector(3 downto 0);

34 signal adrw:std_logic_vector(4 downto 0); --write adr

35 signal adrr:std_logic_vector(4 downto 0); --read adr

36

37 signal SDO:std_logic_vector(31 downto 0);

38 signal SAO:std_logic_vector(31 downto 0);

39

40 constant start: std_logic_vector(3 downto 0):="0000";

41 constant read1: std_logic_vector(3 downto 0):="1011";



44 constant write1: std_logic_vector(3 downto 0):="0001";



47 constant waitre: std_logic_vector(3 downto 0):="1010";

48 --constant wait3: std_logic_vector(3 downto 0):="1000";

49 --constant wait4: std_logic_vector(3 downto 0):="1001";

50

51 begin

52 process(clk)

53 begin

54 if RESET = '1' then

55

56 state <= start;

57 adrw <= "00001";

cpu.vhd Wed Jul 04 09:39:56 2012

Page 2

58 adrr <= "00001";

59 SDO<= X"20120000";

60 READD <= X"00000000";

61

62 elsif clk'event and (clk = '1') then

63

64 case state is

65 when start =>

66 If(step_en = '0') then state <= start;

67 else

68 If (W_instr = '1') then

69 state <= write1;

70 SAO <= "000000000000000000000000000" & adrw;

71 adrw <=adrw+2;

72

73 elsIf (R_instr = '1') then

74 state <= read1;

75 SAO <= "000000000000000000000000000" & adrr;

76 adrr <= adrr+2;

77 else state <= start;

78

79 end if;

80 end if;

81 ----------------------------------------------------

82 when read1 => state <= read2;

83 when read2 =>

84 if (done = '1') then state <= read3;READD <= DI;

85 else state <= read2;

86 end if;

87 when read3 => state <= start;

88 --adrr <=adrr+3;

89

90 -----------------------------------------------------

91 when write1 => state <= write2;

92 when write2 =>

93 if (done = '1')then state <= write3;

94 else state <= write2;

95 end if;

96 when write3 =>

97 SDO <= SDO + 70;

98 If (R_instr = '0') then state <= start;

99 else state <= waitre;

100 end if;

101 when waitre => state <= read1;

102

103 when others => null;

104 end case;

105

106

107 end if;

108

109 end process;

110

111

112

113 rd_req <= '1' when state = read1 else '0';

114 wr_req <= '1' when state = write1 else '0';

cpu.vhd Wed Jul 04 09:39:56 2012

Page 3

115

116

117 AO <= SAO when (state = read1 or state = write1)

118 else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";

119 DO <= SDO when state = write1

120 else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";

121 busy <= '0' when state = start else '1';

122 sts <= state;

123 end Behavioral;

124

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

AA

BB

CC

DD

clk

AI(20:0)

INV

WR_N

RD(31:0)

D(31:0)

RD(15:0)

RD(31:16)

AND2

WR_N

INV

CDQ

FD

AI(31:0)

CDQ

FD

QT

CLR

C

FTC

ACK_N

A(31:0)

buf32

INN(31:0)OUTT(31:0)

AND2B1

QT

CLR

C

FTC

clk

AND2

FDC

C

CLR

DQ

FDC

C

CLR

DQ

FDC

C

CLR

DQ

FDC

C

CLR

DQ

OR2

AND2

clk

GND

ACK_N

INV

OR2

clk

clk

ram_set

clk

we

DI(31:0)

ADD(20:0)

DO(31:0)

AI(25)

AI(24)

AI(23)

AI(22)

AI(21)

OR6

AS_N

NAND2B1

in_init

OR2

ACK_N

D(15:0)

bufe16

Enable

D_IN(15:0)D_OUT(15:0)

D(31:16)

bufe16

Enable

D_IN(15:0)D_OUT(15:0)

bufe16.vhd Wed Jul 04 09:42:35 2012

Page 1

1 ----------------------------------------------------------------------------------

2 -- Company:

3 -- Engineer:

4 --

5 -- Create Date: 11:12:31 07/03/2012

6 -- Design Name:

7 -- Module Name: bufe16 - Behavioral

8 -- Project Name:

9 -- Target Devices:

10 -- Tool versions:

11 -- Description:

12 --

13 -- Dependencies:

14 --

15 -- Revision:

16 -- Revision 0.01 - File Created

17 -- Additional Comments:

18 --

19 ----------------------------------------------------------------------------------

20 library IEEE;


22

23 -- Uncomment the following library declaration if using

24 -- arithmetic functions with Signed or Unsigned values

25 --use IEEE.NUMERIC_STD.ALL;

26

27 -- Uncomment the following library declaration if instantiating

28 -- any Xilinx primitives in this code.

29 --library UNISIM;


31

32 entity bufe16 is

33 Port ( Enable : in STD_LOGIC;

34 D_IN : in STD_LOGIC_VECTOR (15 downto 0);

35 D_OUT : out STD_LOGIC_VECTOR (15 downto 0));

36 end bufe16;

37

38 architecture Behavioral of bufe16 is

39

40 begin

41

42 D_OUT <= D_IN when (Enable = '1') else "ZZZZZZZZZZZZZZZZ";

43

44 end Behavioral;

45

46

buses_t.vhd Wed Jul 04 09:47:32 2012

Page 1

1 -- Vhdl test bench created from schematic D:\projects\a_dlx\buses\logic_set.sch - Tue

Jul 03 16:29:17 2012

2 --

3 -- Notes:

4 -- 1) This testbench template has been automatically generated using types

5 -- std_logic and std_logic_vector for the ports of the unit under test.

6 -- Xilinx recommends that these types always be used for the top-level

7 -- I/O of a design in order to guarantee that the testbench will bind

8 -- correctly to the timing (post-route) simulation model.

9 -- 2) To use this template as your testbench, change the filename to any

10 -- name of your choice with the extension .vhd, and use the "Source->Add"

11 -- menu in Project Navigator to import the testbench. Then

12 -- edit the user defined section below, adding code to generate the

13 -- stimulus for your design.

14 --

15 LIBRARY ieee;


17 USE ieee.numeric_std.ALL;

18 LIBRARY UNISIM;

19 USE UNISIM.Vcomponents.ALL;

20 ENTITY logic_set_logic_set_sch_tb IS

21 END logic_set_logic_set_sch_tb;

22 ARCHITECTURE behavioral OF logic_set_logic_set_sch_tb IS

23

24 COMPONENT logic_set

25 PORT( RESET : IN STD_LOGIC;

26 READD : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

27 STS : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);

28 CLK : IN STD_LOGIC;

29 step_en : IN STD_LOGIC;

30 W_instr : IN STD_LOGIC;

31 R_instr : IN STD_LOGIC);

32 END COMPONENT;

33

34 SIGNAL RESET : STD_LOGIC;

35 SIGNAL READD : STD_LOGIC_VECTOR (31 DOWNTO 0);

36 SIGNAL STS : STD_LOGIC_VECTOR (3 DOWNTO 0);

37 SIGNAL CLK : STD_LOGIC;

38 SIGNAL step_en : STD_LOGIC;

39 SIGNAL W_instr : STD_LOGIC;

40 SIGNAL R_instr : STD_LOGIC;

41

42 signal temp : std_logic := '0';

43 CONSTANT OPERATION : STD_LOGIC_VECTOR (1 DOWNTO 0) := "01" ;

44 -- set value of the constant OPERATION to define the desired transaction:

45 -- 00: NO OPERATION, 01: READ, 10: WRITE, 11 READ AFTER WRITE

46 BEGIN

47

48 UUT: logic_set PORT MAP(

49 RESET => RESET,

50 READD => READD,

51 STS => STS,

52 CLK => CLK,

53 step_en => step_en,

54 W_instr => W_instr,

55 R_instr => R_instr

56 );

buses_t.vhd Wed Jul 04 09:47:32 2012

Page 2

57

58 -- *** Test Bench - User Defined Section ***

59 CLK_process :process

60 begin

61 CLK <= '1';

62 wait for 100 ns;

63 CLK <= '0';

64 wait for 100 ns;

65 end process;

66

67

68 tb : PROCESS

69 BEGIN

70 IF temp = '0' then

71 R_instr <= OPERATION(0);

72 W_instr <= OPERATION(1);

73 step_en <= '0';

74 RESET <= '1';

75 temp <= '1';

76 WAIT for 2ns;

77 WAIT for 200 ns;

78 else

79 step_en <= '1';

80 RESET <= '0';

81 WAIT for 200 ns;

82 step_en <= '0';

83 IF OPERATION(1 DOWNTO 0) = "11"

84 THEN WAIT for 4000 ns;

85 ELSE WAIT for 2000 ns;

86 END IF;

87 end if;

88

89 --WAIT; will wait forever

90 END PROCESS;

91 -- *** End Test Bench - User Defined Section ***

92

93 END;

94

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Handout #3: A simple slave device

3.1 Guidelines for the whole Lab

Generally in the lab we are working on two projects. The first, project home_v14,

can be downloaded from the Lab site. This project can be used in the same way, at home

and in the lab, and all the designs and simulations have to be done within that project.

The second, source_v14, is given to you in your lab working directory. This project can

be used only on the Lab's computers. Project is designed with a schematic top level and

consists of two schematic pages.

On page N2 there are the I/O Control Logic symbols and the Pin LOC

property definitions. No design work to be made on page N2. Place all your design

work on page N1.In your design do not use tri-state buffers (i.e. drivers or "ZZZZ"

equations), in order to avoid outputs conflict. Use MUX instead. In case you have

ignored those remarks, it’s to your full financial responsibility, when damage to the

hardware occurs!!

On page N1 there are all the signals you will need in order to connect the design

to the parallel RESA-2 bus. Use labels, not wires for these connections. Note that some

input signals are connected to VCC. In order to use them you will need to remove the

VCC element.

In order to personalize your work, you can rename the projects directory, but it's

strictly forbidden to rename any directory or file within it.

3.2 Design

You will find on page N1 the simple master device for this assignment: a 32-bit

binary counter connected to 32x32 bit RAM.

1. Understand in details the schematic and functionality of the device.

2. Make address partitioning, single and 32 word blocks, according to the regulations

described in the RESA b2 monitor user guide.

3. Using the project home_v14 as a design environment design a simple component

ID_NUM with a single 8 bit constant output ID[7:0] of your group number and a

slave device, capable of allowing reading information from four 32bit inputs

according to your address partitioning. 4. Create the slave_t.vhd (VHDL test bench file) for your slave device and check it

using ISIM

5. Use function add copy of source to transfer your designs from home_v14 project to

project sources_v14. Place your components on the sheet and connect them to the

master device and I/O Logic bus.

6. Execute “Generate programming file” for your design in order to receive '.bit' file.

7. Run and debug your design using the Hardware monitor of the RESA Program.

8. Print and explain your designs, simulations, labels and monitoring results (data

snapshots) for three sequential steps.

Warnings and reminders:

1. For this exercise you will use the RESA Program. The RESA is connected to the

PC and all the operations should be done via the RESA monitor program.

2. Do not use drivers ("ZZZZ" equations) in your design!!! Conflicting drivers (due

to design errors) can cause hardware damages. Instead of drivers use

corresponding multiplexers.

3. All flip-flops, registers, RAM and counters in your design should share the same

clock. Elements differ in their clock enable signals.

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

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Handout #4 Build-in Self Monitoring

4.1 Pre-Lab Assignment

Consider the application from the previous assignment: a 32-bit binary counter

connected to 32x32 bit RAM. Counter, after reset, on enable counts forward 8 steps, on

next enable -16 steps and continue with this count scheme 8/16. Thus in every step 8 or

16 RAM cells are filled with corresponding counter values. Our goal is to start sampling

the state of the counter starting with the rising edge of the clock that occurs after the

rising edge of the step enable signal. The sampling should stop when the counter is

“stuck”. To perform this you can use the signal called in_init, generated by the

application. The in_init is set to ‘0’ when the counter starts to count and set to ‘1’ when

the counter is “stuck”(the counter’s is “stuck” when the end value in the 5 LSB is 0x8 or

0x10).

1. (5 pts.) Which control signals should the application transmit to the Monitor

Slave (including the Logic Analyzer)? Differentiate between signals that are

monitored by the Logic Analyzer, and signals that aid the Monitor Slave and

the Logic Analyzer to functioning properly.

2. (10 pts.) Write the equations for the following signals:

(a) Write enable (LA_WE) signal of the Logic Analyzer’s RAM.

(b) Count enable (CNT_CE) signal of the Logic Analyzer’s counter.

(c) Clock enable (STS_CE) of the Status Register.

(d) The reset signal of the Logic Analyzer’s counter.

(e) The Select signal of the MUX that selects the address input of the Logic

Analyzer’s RAM

3. (25 pts.) Using the Slave design from the previous handout prepare symbol

Monitor, capable to support read transactions from the Status register,

ID_NUM and the Logic Analyzer’s RAM and two external inputs; Prepare

list of graphic labels with corresponding inputs of the Logic Analyzer’s RAM.

Submit a hand written design.

4.2 Lab Assignment

1. Using the XILINX Design Manager create your Monitor.

2. Create the Monitor_t.vhd file for your slave device and check it using ISIM.

3. Transfer your design to project sources_v14, connect it to the I/O Logic and

implement it in order to produce '.bit' file.

4. Configure RESA-2 with your design. Monitor the states of the counter and other

control signals.

5. Submit printouts of your design, simulation waveforms, Label report and

monitoring results including graph waveforms. 6. Analysis. Submit, with respect to your previously submitted printouts, your answers

to the following questions. Explain your answers.

a. How many samples are made by Logic Analyzer?

b. In how many clock cycles was the Master active?

c. How many Registers (in the RAM32x32) have changed their values?

Warning: You will need your Monitor slave design for all your future lab

assignments. Spend some extra time making sure it is well designed.

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Handout #5: A Read Machine and A Write Machine

5.1 Pre-lab Assignment

1. (20 pts) Design symbols of a Write Machine and a Read Machine. Submit hand-

written designs.

2. (5 pts) Write the equation of the stop signal. Pay attention that you should

capture all the necessary information during the Monitoring.

3. (5 pts) Suppose that we wish to monitor the activity of a Write Machine using the

Logic Analyzer module. We would like to start sampling when the step_en signal

rises, and end the sampling two cycles after the Write Machine returns to the

“wait” state. What changes do you suppose should be made? Submit a hand

written design or equations.

4. (5 pts) Is it possible to design a modified Read Machine that has the same

functionality but does not have the “load” state?

5. (5 pts) Can you get rid of the “terminate” state in the Write Machine without

changing the functionality?

5.2 Post-lab Assignment

(60 pts)

1. Prepare designs of a Write Machine and a Read Machine and simulate them.

2. Using project sources_v14 prepare design with the Monitor Slave (with the Logic

Analyzer) and the Write Machine symbol and implement it.

3. Prepare a label file for the RESA program and monitor your design of the Write

Machine

4. Repeat steps 2 and 3 for the Read Machine

5. Submit: printouts of design, simulation and monitoring results of: (a) the state

transitions; (b) the bus activity of the machines; and (c) the accessed memory (In

the Read Machine, this means that the register of the Read Machine is monitored

as well as the main memory address. In the Write Machine the main memory

address is monitored as well as the constant data to be written).


Handout #6: A Load/Store Machine

6.1 Assignment #1

Design of the Load/Store Machine:

1. (5 pts.) Address translation. The main memory address space to which the

Load/Store Machine can both read and write is 0x00000000-0x01FFFFF.

Suppose we are interested in giving the Load/Store Machine the illusion of a 16-

bit main memory address space with the addresses 0x0000-0xFFFF. Show how

the Address Translation Module can support this illusion. Refer to the PC register

and the address used for memory accesses.

2. (25 pts.) Assume that due to the library, we always want to have 32 registers in

the GPR, although we only really need 31 registers. There are two ways to

implement the register R0 in the GPR. In one way, write access to R0 are disabled

to keep it with a zero. In the second way, read accesses to R0 are pulled down to

output a zero. Compare these two methods and explain which method is

cheaper/faster.

3. (10 pts.) Design the Memory Access Control module. Outline the differences

between this module and the Read and Write Machines.

4. (40 pts.) Complete the Load/Store Machine design. Your design should be as

simple as possible. Do not try to make a design that will be easy to use as a basis

for the DLX! That will complicate your design.

(a) (25 pts.) Prepare designs of the blocks in the data path (PC environment,

GPR environment, IR environment, etc.). Each design should be organized

as follows: list of inputs and outputs, definition of functionality (equations

describing relations between outputs and inputs), and drawing (you may

use counters, decoders, etc. as building blocks of your designs).

(b) (10 pts.) Prepare a table listing all the control signals, their meanings, their

equations and the ports they are connected to.

(c) (5 pts.) Submit printouts of your VHDL design and schematics.

5. (20 pts.) Prepare test vectors for the control of the Load/Store Machine. Submit a

list of paths, input values for each path, and expected output values for each path.

Guidelines: (a) Name all signals and modules using only capital letters. Do not

use non-letters in the names except for underscores. (b) When the Load/Store

Machine fetches an instruction which is not a load or a store instruction it halts by

entering a “halt” state. (c) We suggest adding an output signal signifying the state of

the control to simplify testing of your design.

6.2 Assignment #2

Simulation of the Load/Store Machine:

1. Create control_t.vhd file using the test vectors you designed for the control of

the Load/Store machine. Simulate the control of the Load/Store Machine using

ISIM and vhd test bench file you created. Submit printouts of your

simulation showing that the outputs are as expected. Annotate the printouts by

hand written explanations (which path is tested, what is seen, etc.).

2. Using the I/O SIMUL module and ISIM simulate your design to verify all the RTL

instructions. Submit printouts of simulations of tests annotated with explanations.

3. Submit printouts of executions of whole instructions demonstrating the

correctness of your design. Annotate the simulations with explanations.

Remark: The last two items can be shown in the same simulation. If you choose to do so,

make sure not to omit any of the required data and explanations. The initial contents of

the I/O SIMUL main memory (sram_data.vhd) is depicted in 6.5.3 of the Lab Notes, but

you can use your own. In this case write short assembly program and compile it using the

Text editor of the RESA program. Convert the received .lst file to the VHDL format(.txt)

and replace the initial contents of the sram_data.vhd file. In case you decide to use your

own tests, submit printout of your initialization as well as printouts of your program for

the I/O SIMUL.

6.3 Assignment #3

Implementation of Load/Store Machine with a monitor slave and a logic analyzer:

1. Use project sources_v14 and implement a design of your Load/Store Machine

with a monitor slave and a logic analyzer.

2. Use the .cod file of the assembly program that you have used in 6.2.2 and 6.2.3.

3. Use the RESA Monitor program to run and debug your Load/Store machine

design.

4. Submit printouts of the Monitor program results. Show that your machine

executes instructions correctly. Annotate the printout with explanations of what is

happening in each cycle.


Handout #7: A simplified DLX: design, testing, timing, and

programming

Each question counts as one assignment. Submission deadline is given for each question.

We highly recommend that you divide the load between students in the same group,

otherwise you will find the burden too high.

7.1

Design and test the simplified DLX.

� Submit schematics of the project and of the new modules.

� Submit VHDL file of the control. Describe how you tested the control. Submit

results of testing the control using test vectors. (In order to reduce the amount

submitted simulation, please submit test vectors of the following paths only:

ALU, TESTI, LOAD, STORE, JALR, BTAKEN. However, you should prepare

test vectors for all of the paths.)

� Test your design to see if the correct RTL instruction is executed in each state.

Write short DLX programs that test every instruction. Note that some instructions

must be tested more than once (e.g. “branch taken” and “branch not taken”). Store

these programs in the RAM of the I/O SIMUL module. Build a project from your

DLX design and the modified I/O SIMUL module. Simulate this project. Submit:

(1) Your programs. For every instruction, list the states that are traversed.

(2) Waveforms of a simulation of your design. Add remarks to the waveforms that

show the traversed states, the RTL instruction that were executed, and what they

did.

After completing these stages successfully, it is likely that your design can be run on

the RESA and monitored to see if it functions properly.

7.2

Implement and test your design on the RESA.

Implement your design. Check the project timing.

� Implement your design. Check the project timing. You should easily meet the timing

requirements (In case you don't, please address the Lab Engineer).Re-use the test

programs you used to test the RTL instructions on the RESA. Use the Logic

Analyzer to verify that the RTL instructions are executed properly. Submit

printouts of the monitoring with remarks explaining why you got the right results.

� Read the DLX test program (DLX.lst). Describe how it tests the DLX design. In

the following procedure get the assistance of the Lab's Engineer. Download to the

RESA memory the file DLX.cod and run the test procedure on your design. Get

the Lab's engineer approval of your design.

7.3

Timing optimization of your design

Try to design the fastest design you can. You should at least meet the 50 MHZ

threshold. Implement your design and meet the timing requirements (clock rate at

least 50 MHz). There are a few ways to try to decrease the feasible clock period.

� The first method is to try to reduce delays due to routing in the FPGA. This can be

done by “helping” the place & route tools. You will be told more on how this is

done.

� The second method is to identify the critical path and try to shorten its delay. This

method is applicable provided that there are only a few critical paths.

� The third technique can be used if you failed in shortening the delay of critical

paths. Suppose the critical path includes the ALU. A way to solve this critical

path is to allow two cycles for the ALU. This requires a change in the control so

that each of the corresponding states is divided into two states. We do not

recommend using this method (for example, the software will still report timing

problems because it does not know that the signal is not sampled after one cycle).

You should be able to solve the timing problem without it. After you meet the

timing requirements, Implement and test your design on the RESA. Note that the

timing analysis done by the software tools is often too pessimistic. Your design

may be fast enough even if the software reports otherwise.

7.4

Software program

The goal of this assignment is to write a simple DLX assembly program, that solves a

Problem and run it on the DLX you designed. This assignment will be given to you in the

following weeks.

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