xilinx ise manual

Department of Electronics Engineering 2011

Xilinx ISE 7.1i Software Lab Manual

Dr. Vasantraodada Patil Shetkari Shikshan Mandal’s

PADMABHOOSHAN VASANTRAODADA PATIL INSTITUTE OF

TECHNOLOGY, BUDHGAON-416304

LAB Manual

Xilinx ISE 7.1 (Digital System Design)

DEPARTMENT OF ELECTRONICS ENGINEERING

(2010-11)



Xilinx ISE Overview

The Integrated Software Environment (ISE™) is the Xilinx® design software suite that allows you to take your design from design entry through Xilinx device programming. The ISE Project Navigator

manages and processes your design through the following steps in the ISE design flow.

Design Entry

Design entry is the first step in the ISE design flow. During design entry, you create your source files based on your design objectives. You can create your top-level design file using a Hardware Description Language (HDL), such as VHDL, Verilog, or ABEL, or using a schematic. You can use

multiple formats for the lower-level source files in your design.

Note: If you are working with a synthesized EDIF or NGC/NGO file, you can skip design entry and

synthesis and start with the implementation process.

Synthesis

After design entry and optional simulation, you run synthesis. During this step, VHDL, Verilog, or

mixed language designs become netlist files that are accepted as input to the implementation step.

Implementation

After synthesis, you run design implementation, which converts the logical design into a physical file format that can be downloaded to the selected target device. From Project Navigator, you can run the implementation process in one step, or you can run each of the implementation processes separately. Implementation processes vary depending on whether you are targeting a Field

Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD).

Verification

You can verify the functionality of your design at several points in the design flow. You can use simulator software to verify the functionality and timing of your design or a portion of your design. The simulator interprets VHDL or Verilog code into circuit functionality and displays logical results of the described HDL to determine correct circuit operation. Simulation allows you to create and verify complex functions in a relatively small amount of time. You can also run in-circuit verification after

programming your device.

Device Configuration

After generating a programming file, you configure your device. During configuration, you generate

configuration files and download the programming files from a host computer to a Xilinx device.



What's New in Xilinx ISE 7.1i

This file describes the new features in the Xilinx® Integrated Software Environment (ISE) 7.1i

software release. It contains the following sections:

New Device Support New Software Features New Partner Product Features

Technical Support

New Device Support

This release includes support for the following device families.

Spartan-3E™ FPGA Family Spartan-3L™ FPGA Family Spartan-3™ FPGA XA (Xilinx Automotive) Family Spartan-IIE™ FPGA XA Family CoolRunnner-II™ CPLD XA Family

XA9500XL™ CPLD XA Family

New Software Features

Following are the new features in this release.

Design Management

Following are the design management and design entry enhancements:

Improved ability to run multiple versions of ISE Software. o Version-specific Windows® desktop icon and program group created. o ISE executable sets environment for its version; no need to manually manage environment when

switching versions. o Simply double-click desktop icon (or select from program group) for desired version. Project Navigator features o New Technology Viewer Provides schematic view of post-synthesis/optimization netlists. o RTL and Technology Viewers improvements Cross probing from logic in the RTL Viewer to corresponding source code lines in the ISE Text

Editor. Enhanced schematic rendering capability, providing improved readability. o Easier to add multiple VHDL or Verilog sources via Apply to All checkbox on Source Type dialog. o Easier to enable/disable Advanced properties using option in Process Properties dialog boxes. o Improved CORE Generator™ software integration. o New process to add editable test bench from TBW to project in single step. o Design Summary view The most useful design flow information is shown in a single view, and is updated immediately as

new information becomes available. o Message Filtering capability



You can customize your output and reports to hide certain warning or info messages not applicable to your design.

o Tools integration Mentor Graphics® Precision® RTL Synthesis flow is now integrated into Project Navigator on all

platforms. Cross probing between Timing Analyzer (ITA) and FPGA Editor. Integration of Schematic and Symbol Editors, RTL and Technology Viewers, and ISE Simulator

within Project Navigator.

Improved integration with Xilinx Platform Studio.

o Pushing into a flat (non-hierarchical) user-defined symbol now presents the option to create a VHDL, Verilog, or schematic definition.

o New Paste Special command in Schematic Editor gives more control over how nets and inputs are named in the pasted content.

o Design Rule Checks now detect illegal wired-OR connections. o New preferences give control over the width of nets and buses when printing a schematic. o Schematic Editor has added support for a Partial Bus I/O by providing the ability to take one or

multiple bits of a bus out to an individual I/O port.

ISE Text Editor features o When the RTL Viewer cross probes to a source file, cross probing back to the schematic is

enabled. o Comment and Uncomment functionality is available. VHDL/UCF only have the

Comment/Uncomment LINE functionality. Verilog has both Comment/Uncomment LINE and Comment/Uncomment SELECTION.

o Increase and Decrease Indent functionality is available from menu items and toolbar buttons. o You can view/edit the preferences for the ISE Text Editor, in the typical manner. Preferences

include the font used by the editor, how to treat tab characters, and whether to allow the cursor to be moved beyond the end of the line.

o Functionality for adding and removing breakpoints is available for debugging code while running in

the ISE Simulator.

Synthesis

Following are the Xilinx Synthesis Technology (XST) enhancements. For more information, see the XST User Guide available from the Software Manuals collection.

VHDL Language Support o Support for configurations and nested configurations. o Support for shared variables (dual-write block RAM inference only). o Support for NULL arrays. o Improved support for File Read. Support for hexadecimal values in read operations. Support for std_ulogic type (limited to values “1” and “0”). Support for character and string type read functions. Verilog Language Support o Support of defparams for passing attributes to Xilinx® library primitives. o Support for variable part select. o Improved support for while loops. Macro Inference o Inference of dual-write port block RAM (VHDL only).

http://www.xilinx.com/support/sw_manuals/xilinx7/



o Support for parity bits use for block RAM implementation (limited to Virtex-4™ devices). o Support for Block RAM initialization via signal declaration mechanism. Initialization of dual-port block RAMs in VHDL. Initialization of single and dual-port block RAMs in Verilog. o Support for Block RAM/Block ROM initialization from an external text file. o Finite State Machine (FSM) Processing. Support for Safe FSM implementation. Improved automatic FSM encoding selection. Introduced new speed oriented encoding method, called Speed1. Report of original and final FSM encoding. o Support for Macro inference for Virtex-4 devices and its control via USE_DSP48

constraint/command line switch. o More Macro Inference capabilities are listed in Chapter 1 of the XST User Guide. See the XST User

Guide available from the Software Manuals collection Design Constraints o New constraints controlling design processing have been added. Seven constraints have been

updated with new values or capabilities. Please refer to Chapter 1 of the XST User Guide for a complete list of all the new and modified constraints.

o New syntax for switches supporting multiple directories. This change is related to the support of file and directory names with spaces.

FPGA Flow o Support for automatic inference of BUFGs on most critical internal clocks controlled by

BUFFER_TYPE constraint. o Improved support for Incremental Synthesis. INCREMENTAL_SYNTHESIS constraint can now be

applied to blocks instantiated more than once. o Improved detection and reporting of multi-source problems. o The number of analyzed or failed paths and ports is now reported in Detailed Timing Report.

o Improved quality of results under high optimization effort for speed-oriented optimization.

Verification

Following are verification enhancements:

New ISE Simulator o New built-in HDL simulator, available in limited (free) and unlimited versions. o Integrated VHDL/Verilog simulator with integrated wave editor for test bench creation. o Behavioral/RTL simulation prior to synthesis. o Timing simulation after place and route or fitting. o Design Hierarchy, waveform, and console views. o Source-level debugging capabilities. o Command-line console features TCL interface. o Generate Expected Results process generates expected design output behavior based on input

stimulus. o Simulator can generate Value Change Dump (VCD) file for use in XPower. o Available in Base and Foundation™ configurations only.

Simulation Performance Improvements

o UNISIM and SIMPRIM library optimizations to reduce simulation runtimes. o CompXLib Verilog library compilation time reduction. o Netgen netlisting runtime improvements.

http://www.xilinx.com/support/sw_manuals/xilinx7/



Memory Model Improvements including 2-dimensional array representation of memory contents and added control of memory collision checks.

New JTAG simulation model added for Virtex-4 devices. Ability to generate XST post-synthesis simulation netlists. ModelSim® Xilinx Edition III support. o ModelSim Xilinx Edition III is upgraded to version 6.0a. o Increased capability in free MXE III Starter to support larger designs with better performance. o 20% additional performance improvement in full MXE III. ChipScope Pro™ improvements o Operating System Support The ChipScope Analyzer joins the Core Generator and Inserter on Linux and Solaris platforms. Enterprise Linux 3.0 is fully supported, and Solaris 8 and 9 are supported in client-server mode. o Storage Qualification is available for ILA and IBA cores. This feature, introduced in 6.3.01i, allows users to filter data to be stored after trigger conditions

have been met. o Performance Increase to over 300MHz. ILA and IBA cores have been re-engineered for Virtex-II™, Virtex-II Pro™, Virtex-4, and Spartan-

3™ devices, leading to performance improvements up to a 50% increase in clock frequency. o Multi-Gigabit Transceivers can be debugged by ChipScope Pro software. o The ChipScope Core Inserter now supports full netlist insertion. Designs utilizing Hierarchical

Design flows and non-secure IP blocks can now be fully instrumented. o New communication support: Platform Cable USB o Updates to ATC2 cores support The ATC2 cores now support Virtex-4 devices. Multiple ATC2 cores can be inserted in a single FPGA. The new Plug & Debug process will automatically associate individual signals in the FPGA to the

logic analyzer probe inputs without user intervention. ATC2 cores are supported on the 1680, 1690, and 16900 Logic Analyzers as well as the Infiniium

Mixed-Signal Oscilloscopes.

Implementation

Following are implementation enhancements:

FPGA Editor Features o Ability to see larger shapes that utilize multiple components (such as a carry chain and wide

function) and move and place these shapes together. o Ability to change background from black to white. Constraints Flexibility o Bus delimiters in the UCF file do not have to match the delimiters in the source netlist. Any of the

delimiter types – < >, [ ], { }, or ( ) – can be used to denote a signal within a bus. Improvements to Timing-Driven Packing and Placement o The Place and Route Extra Effort option is available when the Map Effort Level is set to High.

Values available are Normal and Continue on Impossible. o The Place and Route Starting Cost Table option is available. Values can range from 1 to 100. o A new Register Duplication feature can also be enabled, allowing Map to replicate flip flops to

improve timing. Improved detection of designs containing paths that cannot be routed. o Rather than spend a long time attempting to route a design with unroutable paths, the router quickly

detects such cases. Upon detection of an unroutable path, the router exits, giving detailed information about the reason the design is unroutable.



PlanAhead o Ability to edit/create constraints and analyze the effect of the changes using TimeAhead. o Support for PBlock geometry to comprise multiple rectangles enabling rectilinear shaped PBlocks. o Improvement in correlation between the estimated TimeAhead report and the TRACE post-routed

timing results. o Design Rule Check warning users if RTL code is written to not use synchronous output registers

(inside the DSP48 and RAMB16). o The order and comments in the input UCF file are now preserved in the PlanAhead output UCF file. o Ability to apply a floorplan from an existing netlist to a newly resynthesized netlist to preserve QOR.

o Reduction in memory use when loading large designs.

Device Configuration

Following are the cable software enhancements:

The new CableServer executable allows for programming of devices across a network. Following are the iMPACT enhancements:

The new iMPACT Project File (.ipf) provides an easy way to save and restore any configuration work.

Ability to execute SVF files. Configuration Debug enhancements o New Debug menu o Capability to determine if a JTAG chain is broken and where the break occurs. o Capability for users to read and decode the FPGA configuration status register at any time. Improvements to wizards and dialogs for both PROM-file creation and PROM programming

functions. Support drag-and-drop addition of files to projects.

Advanced Users will have the ability to switch off the iMPACT wizard for many functions.

ISE Software Documentation Improvements

Following are improvements to the ISE Help:

ISE Help provides access to all help packages available and includes a common search and indexing capability.

ISE Help now includes design strategies for each of the steps in the ISE software flow.

New Partner Product Features

Following are the new features in partner releases related to the Xilinx ISE 7.1i software release. The Cadence® software includes the following enhancements:

The Xilinx specific runtime improvement in the Cadence® NC-Sim tool is now extended to the Virtex-4 family.

Cadence® Conformal-LEC formal verification tool verifies the functionality of the Synplify Pro V8.0 (or later) synthesized netlist against RTL in a more automated fashion and minimum user intervention for the latest FPGA devices including Virtex-4. The Conformal-LEC can also be used to validate the functionality of post PAR netlist against post synthesis netlist.

Cadence® Allegro PCB SI (SPECCTRAQuest) is now compatible with Xilinx latest RocketIO™ design kit.



The Mentor Graphics® software includes the following enhancements:

Precision® RTL Synthesis: New device support QOR Improvements

o Fmax (~10% faster) o Area (~4% smaller) Precision® Physical o New device support o Additional functionality Incremental placement Bottom up physical design flow support LeonardoSpectrum™ Synthesis: New device support FPGA BoardLink now supports the latest Xilinx devices including Virtex-4. In addition to automating schematic symbols creation and updates, I/O Designer supports the latest

device families and performs design rule checks to assist in creating FPGA pinout.

ModelSim v6.0 has new enhanced user interface.

The Synopsys® software includes the following features and enhancements:

DC FPGA® o The latest FPGA synthesis solution from Synopsys provides the flexibility of a Design Compiler for

FPGA designs. o The ASIC Prototyping Synthesis process can be customized using DC commands, supports

Synopsys DesignWare®, provides inferencing of Xilinx architectural resources including RAMs (BRAM and Distributed RAM).

o New device support. PrimeTime® o The ISE software (Netgen) generates netlist and SDF files with max and relative min delays, which

enables min-max analysis within the PrimeTime software. o New device support. HSPICE® o The HSPICE Signal Integrity Simulation (SIS) software supports S-parameter simulation models for

the RocketPHY™ family of physical layer transceivers (PHYs) and the extended Virtex-II Pro family of 10 Gbps transceivers.

o Also includes CosmosScope™, a powerful, new waveform viewer. Formality® o The ISE software (Netgen) generates an Equivalency Checking (EC) netlist and Formality setup

(SVF) files to verify RTL to post synthesis and post synthesis to post Place and Route netlists. o The Formality software supports RAM inferencing, multiplier matching, and verification for operands

greater than 18 bits and new device support. LEDA® o The LEDA checker supports about 150 FPGA-specific rules, which cover Virtex-II, Virtex-II Pro, and

Spartan-3 devices. o There are 10 new rules provided in LEDA 4.1 compared to what was available in the previous

version with the ISE 6.1i software.

The Synplicity® 8.0 software includes the following enhancements:

Synplify Pro® software



o First feature support for System Verilog o QOR improvements (Better Performance, smaller area) o New device support o Graphical Warning Viewer o TCL and GUI Find function o HTML log file Amplify® Software o Physical Synthesis o Physical Analyst

o Island Timing Report (Spreadsheet view of timing information)

The Product Acceleration Inc.® software includes the following enhancements:

Automated FPGA pinout assignment for Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-4. Updated IO banking design rule checks - single ended and differential pairs for all families. Support Weighted Average Simultaneous Switching Outputs (WASSO) guidelines for all families. Added Support for local clocking and regional clocking rules for all families. Added Verilog and VHDL top level entity/module import capabilities. Added support for Import and Export of Xilinx user constraint file (UCF).

Architecture Support

The ISE™ software supports the following device architecture families:

FPGAs Spartan-II™ Spartan-IIE Spartan-3™ Spartan-3E Spartan-3L™ Virtex™ Virtex-E Virtex-II™ Virtex-II Pro™ Virtex-II Pro X

Virtex-4™

CPLDs CoolRunner™ XPLA3 CoolRunner-II™ XC9500™ XC9500XL

XC9500XV



Project Navigator Overview

Project Navigator organizes your design files and runs processes to move the design from design entry through implementation to programming the targeted Xilinx® device. Project Navigator is the

high-level manager for your Xilinx FPGA and CPLD designs, which allows you to do the following:

Add and create design source files, which appear in the Sources in Project window Modify your source files in the Workspace Run processes on your source files in the Processes for Source window

View output from the processes in the Transcript window

Note: Optionally, you can run the Project Navigator processes from a script you create or from a command line prompt. However, it is recommended that you first become familiar with the basic use of the Xilinx Integrated Software Environment (ISE™) software and with project management, as

described in the following sections.

Project Navigator Main Window

The following figure shows the Project Navigator windows, which allow you to manage your design

starting with design entry through device configuration.



1. Toolbar 2. Sources in Project window 3. Processes for Source window 4. Workspace 5. Transcript window

Note For details on these areas, see Project Navigator Main Window.

Using the Sources in Project Window

The first step in implementing your design into a Xilinx® FPGA or CPLD is to assemble the design source files into a project. The Module View of the Sources in Project window shows the source files you create and add to your project, as shown in the following figure. For information on

creating projects and source files, see Creating a Project and Creating a Source File.

The Module View shows the hierarchy of your design. You can collapse and expand the levels by clicking the plus (+) or minus (-) icons. Each source file appears next to an icon that shows its file type. The file you select determines the processes available in the Processes for Source window. You can double-click a source file to open it for editing in the Workspace. For information on the

different file types, see Source File Types.

From the Module View, you can also change the project properties, such as the device family to target, the top-level module type, the synthesis tool, the simulator, and the generated simulation

language. For information, see Changing the Target Device and Design Flow.

Note: The Sources in Project window also includes the Snapshot View and the Library View. For

information on working with libraries, see Working with VHDL Libraries. For information on working with snapshots, see Working with Snapshots.

Using the Processes for Source Window

The Process View of the Processes for Source window allows you to run actions or "processes" on the source file you select in the Module View of the Sources in Project window. The processes change according to the source file type you select, as shown in the following figures.



The Process View shows the available processes in a hierarchical view. You can collapse and expand the levels by clicking the plus (+) or minus (-) icons. Processes are arranged in the order of a typical design flow: project creation, design entry, constraints management, synthesis, implementation, and programming file creation.

Processes Types

The following types of processes are available as you work on your design:

Tasks

When you run a task process, the ISE software runs in "batch mode," that is, the software processes your source file but does not open any additional software tools in the Workspace.

Output from the processes appears in the Project Navigator Transcript window.

Reports

Most tasks include report sub-processes, which generate a summary or status report, for example, the Synthesis Report or Map Report. When you run a report process, the report appears in the

Project Navigator Workspace.

Tools



When you run a tools process, the related tool launches in standalone mode or appears in the Project Navigator Workspace where you can view or modify your design source files.

Note: The icons for tools processes vary depending on the tool. For example, the Timing Analyzer

icon is shown above.

Process Status

As you work on your design, you may make changes that require some or all of the processes to be rerun. For example, if you edit a source file, it may require that the Synthesis process and all subsequent process be rerun. Project Navigator keeps track of the changes you make and shows

the status of each process with the following status icons:

Up-to-date

This icon shows that the process ran successfully with no errors or warnings and does not need to be rerun. If the icon is next to a report process, the report is up-to-date; however, associated tasks may have warnings or errors. If this occurs, you can read the report to determine the cause of the

warnings or errors.

Warnings reported

This icon shows that the process ran successfully but that warnings were encountered.

Errors reported

This icon shows that the process ran but encountered an error.

Out-of-Date

This icon shows that you made design changes, which require that the process be rerun. If this icon is next to a report process, you can rerun the associated task process to create an up-to-date version of the report.

No icon

If there is no icon, this shows that the process was never run.

Running Processes

To run a process, you can do any of the following:

Double-click the process Right-click while positioned over the process, and select Run from the popup menu, as shown in

the following figure.



Select the process, and then click the Run toolbar button:

When you run a process, Project Navigator automatically processes your design as follows:

Automatically runs lower-level processes

When you run a high-level process, Project Navigator runs associated lower-level processes or sub-processes. For example, if you run Implement Design for your FPGA design, all of the following sub-processes run: Translate, Map, and Place & Route.

Automatically runs preceding processes

When you run a process, Project Navigator runs any preceding processes that are required, thereby "pulling" your design through the design flow. For example, to pull your design through the entire flow, double-click Generate Programming File.

Automatically runs related processes for out-of-date processes

If you run an out-of-date process, Project Navigator runs that process and any related processes required to bring that process up to date. It does not necessarily run all preceding processes. For example if you change your UCF file, the Synthesize process remains up to date, but the Translate process becomes out of date. If you run the Map process, Project Navigator runs Translate but

does not run Synthesize.

Note: For more information on running processes, including additional Process menu commands,

see Running Processes.

Setting Process Properties

Most processes have a set of properties associated with them. Properties control specific options, which correspond to command line options. When properties are available for a process, you can right-click while positioned over the process and select Properties from the popup menu, as shown

in the following figure.



When you select Properties, a Process Properties dialog box appears, with standard properties that you can set. The Process Properties dialog box differs depending on the process you select. For example, the following figure shows the Process Properties dialog box for the Synthesize - XST

process.

After you become familiar with the standard properties, you can set additional, advanced properties in the Process Properties dialog box; however, setting these options is not recommended if you are just getting started with using the ISE software. When you enable the advanced properties, both

standard and advanced properties appear in the Process Properties dialog box.

Note: For more information on process properties, see Setting Process Properties. To set command line options using process properties, see Setting Command Line Options using Process

Properties.

Using the Workspace

When you open a project source file, open the Language Templates, or run certain processes, such as viewing reports or logs, the corresponding file appears in the Workspace. You can open multiple files at one time. Tabs at the bottom of the Workspace show the names of the open files. Click a tab to select the file to view.

You can undock a file in the Workspace to open it in a standalone window outside of the Project

Navigator main window. You can dock or undock the file as needed using the following buttons:



Dock

Undock

Using the Transcript Window

The Console tab of the Transcript window shows output messages from the processes you run. When the following icons appear next to a message, you can right-click the message and select Goto Answer Record to open the Xilinx website and show any related Answer Records. If a line number appears as part of the message, you can right-click the message and select Goto Source

to open the source file with the appropriate line number highlighted.

Warning

Error

Note: The Transcript window also includes the Find in Files tab, Errors tab, and Warnings tab.

Using the Toolbars

The toolbars provide convenient access to frequently used Project Navigator commands. Click once on a toolbar button to execute a command. Depending on which tool you have open in the

Workspace, the following toolbars are available:

Standard Toolbar: Always available Editor Toolbar: Always available Tools Toolbar: This toolbar changes depending on the type of file you are modifying in the

Workspace.

To see a short popup description of a toolbar button, hold the mouse pointer over the button for about two seconds. A longer description appears in the status bar at the bottom of the main window.

For Help on a toolbar button, click the Help toolbar button, as shown in the following figure, and then click the toolbar button on which you want Help. For more information on getting Help, see

Using Xilinx Help.



Creating a Project

Project Navigator allows you to manage your FPGA and CPLD designs using an ISE™ project, which contains all the files related to your design. First, you must create a project and then add source files. With your project open in Project Navigator, you can view and run processes on all the files in your design. Project Navigator provides a wizard to help you create a new project, as follows.

To Create a Project

1. Select File > New Project.

2. In the New Project Wizard, do the following: a. In the Project Name field, enter a name for the project. b. In the Project Location field, enter the directory name or browse to the directory. c. In the Top-Level Module Type drop-down list, select one of the following top-level design module

types: HDL

Select this option if your top-level design file is a VHDL, Verilog, or ABEL (for CPLDs) file. An HDL Project can include lower-level modules of different file types, such as other HDL files, schematics,

and "black boxes," such as IP cores and EDIF files.

Schematic

Select this option if your top-level design file is a schematic file. A schematic project can include lower-level modules of different file types, such as HDL files, other schematics, and "black boxes," such as IP cores and EDIF files. Project Navigator automatically converts any schematic files in your design to structural HDL before implementation; therefore, you must specify a synthesis tool

when working with schematic projects, as described in step 5.

EDIF

Select this option if you converted your design to this file type, for example, using a synthesis tool. Using this file type allows you to skip the Project Navigator synthesis process and to start with the implementation processes.

NGC/NGO

Select this option if you converted your design to this file type, for example, using a synthesis tool. Using this file type allows you to skip the Project Navigator synthesis process and start with the

implementation processes.

3. Click Next. 4. If you are creating an EDIF or NGC/NGO project, do the following in the File Selection page of the

New Project Wizard. If you are creating an HDL or schematic project, skip to the next step. a. In the Input Design field, enter the name of the input design file, or browse to the file and select it. b. Select Copy Input Design to the Project Directory to copy your file to the project directory. If you

do not select this option, your file is accessed from the remote location. c. In the Constraint File field, enter the name of the constraints file, or browse to the file and select it.



d. Select Copy Constraint File to the Project Directory to copy your file to the project directory. If you do not select this option, your file is accessed from the remote location.

e. Click Next.

In the Device and Design Flow page of the New Project Wizard, set the following options. These settings affect other project options, such as the types of processes that are available for your design.

Device Family

Note: To target a Spartan-3L™ device, select Spartan-3™ as the family. When creating an EDIF project, the device family information is read from your EDIF project file, and changing the device family is not recommended.

Device

Note: To target a Spartan-3L device, select a device that ends in l, such as xc3s2000l.

Package Speed Grade

Top-Level Module Type

This is automatically set.

Synthesis Tool

Select one of the following synthesis tools from the Synthesis Tool drop-down list. A partner synthesis tool is only available as an option if the tool was installed on your computer. If a synthesis tool was installed, but it does not appear as an option, set the path to the synthesis tool in the

Integrated Tools Options page of the Preferences dialog box.

Note: When creating an EDIF or NGC/NGO project, this option is not applicable.

XST (Xilinx® Synthesis Technology)

XST is available with ISE Foundation™ software installations. It supports projects that include schematic design files and projects that include mixed language source files, such as VHDL and

Verilog sources files in the same project.

Synplify and Synplify Pro (from Synplicity®, Inc.)

The Synplify® software does not support projects that include mixed language source files. The

Synplify Pro® software supports projects that include mixed language source files, such as VHDL and Verilog sources files in the same project. The Synplify and Synplify Pro software do not support

projects that include schematic design files.

LeonardoSpectrum (from Mentor Graphics®, Inc.)

The LeonardoSpectrum™ software supports projects that include schematic design files. It does not

support projects that include mixed language source files, such as VHDL and Verilog sources files

in the same project.



Precision (from Mentor Graphics®, Inc.)

The Precision® software supports projects that include schematic design files and projects that include mixed language source files, such as VHDL and Verilog sources files in the same project.

When you select the synthesis tool, you must also select one of the following HDL languages for

your project:

VHDL Verilog VHDL/Verilog

Note: This is a mixed language flow. If you plan to run behavioral simulation, your simulator must

support multiple language simulation.

Simulator

From the Simulator drop-down list, select one of the following simulators:

ISE Simulator (Xilinx Simulator)

This simulator allows you to run integrated simulation processes as part of your ISE design flow.

ModelSim (from Mentor Graphics®, Inc.)

You can run integrated simulation processes as part of your ISE design flow using any of the following ModelSim® editions: ModelSim Xilinx Edition (MXE), ModelSim MXE Starter, ModelSim

PE, or ModelSim SE™.

Note: For more information on ModelSim, including the differences between each edition, see

Using the ModelSim Simulator.

Other

Select this option if you do not have ISE Simulator or ModelSim installed or if you want to run simulation outside of Project Navigator. This instructs Project Navigator to disable the integrated

simulation processes for your project.

Generated Simulation Language

If you have a single language design, the language you set for your synthesis tool is already set in this field. The language you select determines the language in which to generate simulation netlists. In addition, this setting determines the language in which to write CORE Generator™ IP behavioral models, schematic files, instantiation templates, StateCAD HDL, test benches, and any other files

that are generated within the Project Navigator flow.

6. If you are creating an EDIF or NGC/NGO project, skip to step 8. If you are creating an HDL or schematic project, click Next, and optionally, create a new source file for your project.



Note: You can only create one new source file while creating a new project. You can create

additional new sources after your project is created.

7. Click Next, and optionally, add existing source files to your project. 8. Click Next to display the Information page of the New Project Wizard. 9. Click Finish to create the project.

Note If you prefer, you can create a project using the New Project dialog box instead of the New Project Wizard, as described above. To use the New Project dialog box, deselect the Use new

project wizard option in the ISE General Options page of the Preferences dialog box.

What to Expect

Project Navigator creates the project file, project_name.ise, in the directory you specified. All source

files related to the project appear in the Project Navigator Sources in Project window. Project Navigator manages your project based on the project properties (top-level module type, device type, synthesis tool, and language) you selected when you created the project. It organizes all the parts of your design and keeps track of the processes necessary to move the design from design

entry through implementation to programming the targeted Xilinx device.

Note: For information on changing project properties, see Changing the Target Device and Design

Flow.

What to Do Next

You can perform any of the following:

Create and add source files to your project.

Add existing source files to your project.

Run processes on your source files.



Using ISE Example Projects

To help familiarize you with the ISE™ software and with FPGA and CPLD designs, a set of example designs is provided with Project Navigator. The examples show different design techniques and source types, such as VHDL, Verilog, ABEL, schematic, or EDIF, and include

different constraints and stimulus files.

To Open an Example

1. Select File > Open Example.

2. In the Open Example dialog box, select the Sample Project Name that you want to use.

To help you choose an example project, the Project Description field describes each project. In

addition, you can scroll to the right to see additional fields, which provide details about the project.

3. In the Destination Directory field, enter a directory name or browse to the directory. 4. Click OK.

What to Expect

The example project is placed in the directory you specified in the Destination Directory field and is automatically opened in Project Navigator. You can then run processes on the example project and

save any changes.

Note: If you modified an example project and want to overwrite it with the original example project, select File > Open Example, select the Sample Project Name, and specify the same Destination Directory you originally used. In the dialog box that appears, select Overwrite the existing

project... and click OK.

Creating a Source File

A source file is any file that contains information about a design. Project Navigator provides a

wizard to help you create new source files for your project.

What to Do First

Open a project in Project Navigator.

To Create a Source File

1. Select Project > New Source.

Note Alternatively, you can double-click Create New Source in the Processes for Source window.

2. In the New Source dialog box, select the type of source you want to create.



Different source types are available depending on your project properties (top-level module type, device type, synthesis tool, and language). Some source types launch additional tools to help you

create the file, as described in Source File Types.

3. Enter a name for the new source file in the File Name field.

Note: Make sure your file name adheres to the file naming conventions.

4. In the Location field, enter the directory name or browse to the directory. 5. Select Add to Project to automatically add this source to the project.

Note: State machines created with State CAD cannot be automatically added to the project. You

must add them manually.

6. Click Next.

7. If you are creating a source file that needs to be associated with an existing source file, select the appropriate source file, and click Next. If this does not apply, skip to the next step.

8. In the New Source Information window, read the summary information for the new source, and click Finish.

What to Expect

After you click Finish, the New Source wizard closes. In some cases, a related tool is launched in which you can finish creating your file. After the source file is created, it appears in the Project Navigator Sources in Project window. If you selected Add to Project when creating the source file,

the file is automatically added to the project.



Source File Types

The following table shows the source file types that appear in the Project Navigator Sources in Project window. Available source types vary depending on your project properties (top-level module type, device type, synthesis tool, and language). The last column describes what to expect when creating the file with the New Source wizard and, if applicable, includes the tool launched when using the New Source Wizard or when editing the file from Project Navigator.

Note: For a list of all the file types generated by the ISE software, see the "Xilinx Development

System Files" appendix in the Development System Reference Guide.

File Type Extension Icon Description New Source Wizard Behavior/Tool Launched

ABEL Test Vector .abv

Describes input stimulus and expected outputs for logic simulation of ABEL design code.

Associates the file with the top-level module and opens a skeleton test bench file in the text editor you specify in the Editor Options page of the Preferences dialog box.

ABEL-HDL Module

.abl

Contains ABEL design code.

Allows you to specify your pin names and then opens the file in the text editor you specify in the Editor Options page of the Preferences dialog box.

Block RAM Memory Map (BMM File)

.bmm

Used in PowerPC™ and MicroBlaze™ processor designs to describe the organization of Block RAM

memory.

Note Only one BMM

Module is allowed per project.

Opens the file in the text editor you specify in the Editor Options page of the Preferences dialog box. The CPU executable code is automatically inserted in the configuration file during design implementation.

Chipscope Definition and Connection (CDC File)

.cdc

Contains generic information about the trigger and data ports of the ChipScope™ core.

Adds the file to the project. Double-click the CDC file in the Sources in Project window to run the implementation process and launch the ChipScope Pro™ Core Inserter. For details, see the ChipScope Pro

Debugging Overview.

Note ChipScope Pro must be

installed for this source type to be available.

Electronic Data Interchange Format (EDIF)

.edn, .edf,

.edif, .sedif

Specifies the design netlist in an industry standard file format.

N/A

Must be generated by a third-party design entry tool and added to the

project.

Note You can only add an EDIF file



as a top-level module, not as a lower-level module. If you are using hierarchical EDIF files, lower-level EDIF files are automatically processed during the implementation process.

ELF .elf

Contains an executable CPU code image.

Note Only one ELF file is

allowed per project.

N/A

Must be generated by the Data2MEM command line tool and added to the project.

Embedded Processor

.xmp

Contains predefined logic functions.

Launches the Xilinx Platform Studio in which you can define the embedded processor system portion of your design. For details, see the Embedded Development Kit Documentation.

Implementation

Constraints File

also known as User Constraints File (UCF)

.ucf

Contains user-specified logical constraints.

Adds the file to the project. Double-click the UCF file in the Sources in Project window, or double-click a Constraints Entry process in the Processes for Source window to open the file. For details, see Constraints Entry Methods.

IP (Architecture Wizard)

.xaw

Contains predefined logic functions that configure architecture features or modules.

Launches one of the Xilinx Architecture Wizards in which you can define your IP. For details, see Working with Architecture Wizard IP.

IP (CoreGen) .xco

Contains predefined logic functions.

Launches the Xilinx CORE Generator™ software in which you can define your IP. For details, see Working with CORE Generator IP.

Memory Definition (MEM File)

.mem

Used in Virtex-II Pro™ Power PC™ and MicroBlaze™ processor designs to define the contents of a Read-Only

Memory (ROM).

Note Only one MEM file is

allowed per project.

Opens the file in the text editor you specify in the Editor Options page of the Preferences dialog box. The CPU executable code is automatically inserted in the configuration file during design implementation.

Project .ise

Contains the project title, list of files, and information for managing the ISE™ project.

N/A

Schematic .sch

Contains a schematic design.

Opens Schematic Editor in the Project Navigator Workspace in which you can define your schematic. For details, see the Schematic Overview.

State diagram .dia

Contains a state diagram file.

Launches StateCAD in which you can define your state diagram. For details,

http://www.xilinx.com/ise/embedded/edk_docs.htm

http://www.xilinx.com/ise/embedded/edk_docs.htm



see Working with State Machines.

Targeted device, package, and speed grade

N/A

Shows the targeted device, package, and speed grade.

N/A

Test Bench Waveform

.tbw

Contains a graphical representation of a test bench that can be converted to an HDL test bench or test fixture.

Prompts you to associate the file with a source and opens the Test Bench Waveform Editor in the Project Navigator Workspace with the signals populated. For details, see the ISE

Simulator Help.

Note This file is for use with the Xilinx® Test Bench Waveform Editor only.

Undefined N/A

Not recognized by Project Navigator and not implemented with the design.

N/A

Must be added to the project.

User Document .doc, .txt, .wri

Contains user information that is not implemented with the project, for example, supporting documentation.

N/A

Must be added to the project.

Verilog Module .v

Contains Verilog design code.

Opens the file in the text editor you specify in the Editor Options page of the Preferences dialog box.

Verilog Test Fixture

.v

Defines the stimulus to the ports of an HDL file.

Prompts you to associate the file with a Verilog source module and then opens a skeleton test bench file in the text editor you specify in the Editor Options page of the Preferences dialog box.

VHDL Library .vhd

Contains a collection of VHDL packages.

Adds a new directory to the vhdl library directory in the Library View of the Sources in Project window.

VHDL Module .vhd

Contains VHDL design code.


VHDL Package .vhd

Contains definitions, macros, sub-routines, supplemental types, subtypes, constants, functions, and other files.


VHDL Test Bench .vhd

Defines the stimulus to the ports of an HDL file.

Prompts you to associate the file with a VHDL source and then opens a skeleton test bench file in the text editor you specify in the Editor Options page of the Preferences dialog box.



FPGA Design Flow Overview

The ISE™ design flow comprises the following steps: design entry, design synthesis, design implementation, and Xilinx® device programming. Design verification, which includes both functional verification and timing verification, takes places at different points during the design flow. This section describes what to do during each step. For additional details on each design step, click a box in the following figure.

Design Entry

Create a Project Navigator project and specify your top-level design file as follows:

1. Create a Project Navigator project.

2. Create files and add them to your project, including a user constraints (UCF) file.

3. Add any existing files to your project.

4. Assign constraints such as timing constraints, pin assignments, and area constraints.

Functional Verification

You can verify the functionality of your design at different points in the design flow as follows:

Before synthesis, run behavioral simulation (also known as RTL simulation). Run functional simulation (also known as gate-level simulation) at the following points in the design

flow:

After Synthesize (UNISIM library)

After Translate (SIMPRIM library)

After device programming, run in-circuit verification.



Design Synthesis

Synthesize your design.

Design Implementation

Implement your design as follows:

1. Implement your design, which includes the following steps: Translate

Map

Place and Route

2. Review reports generated by the Implement Design process, such as the Map Report or Place & Route Report, and change any of the following to improve your design:

Process properties

Constraints

Source files 3. Synthesize and implement your design again until design requirements are met.

Timing Verification

You can verify the timing of your design at different points in the design flow as follows:

Run static timing analysis at the following points in the design flow:

After Map

After Place & Route Run timing simulation at the following points in the design flow:

After Map (for a partial timing analysis of CLB and IOB delays)

After Place and Route (for full timing analysis of block and net delays)

Xilinx Device Programming

Program your Xilinx device as follows:

1. Create a programming file (BIT) to program your FPGA.

2. Generate a PROM, ACE, or JTAG file for debugging or to download to your device.

3. Use iMPACT to program the device with a programming cable.



FPGA Basic Flow

With designs of low to moderate complexity, you can process your design using the ISE™ Basic Flow as follows:

1. Create a Project Navigator project and specify your top-level design file as follows:

a. Create a Project Navigator project.

b. Create files and add them to your project, including a user constraints (UCF) file.

c. Add any existing files to your project.

d. Edit the design files to specify design functionality.

e. Optionally, use the Language Templates to assist in coding of the design. f. Edit the design test bench or waveform files to drive stimulus for testing the design files. Optionally,

do the following:

Use the Test Bench Waveform Editor to specify stimulus for the design.

Use the Language Templates to assist in coding of the test bench.

g. Assign constraints such as timing constraints, pin assignments, and area constraints.

Note: If you are working with an EDIF or NGC/NGO top-level source file and performed behavioral

simulation outside of Project Navigator, skip ahead to step 5.

2. Run behavioral simulation (also known as RTL simulation). 3. Repeat steps 1 and 2 until desired functionality is achieved.

4. Synthesize your design. 5. Implement your design as follows:

a. Run the Implement Design process, which automatically runs the following processes: Translate Map

Place and Route

b. Review reports generated by the Implement Design process, such as the Map Report or the Place

and Route Report, and change any of the following to improve your design:

Process properties

Constraints

Source files

c. Modify the design as necessary, simulate, synthesize, and implement your design again until design requirements are met.

3. Run timing simulation to verify end functionality and timing of the design. 4. Program your Xilinx® device as follows:

c. Create a programming file (BIT) to program your FPGA.

d. Generate a PROM, ACE, or JTAG file for debugging or to download to your device.

e. Use iMPACT to program the device with a programming cable.



FPGA Advanced Flows

In some cases, running your design through the FPGA Basic Flow is not sufficient. For example, if you have strict design requirements, such as dense area constraints, or aggressive timing requirements, or if you are designing for a large FPGA and splitting up the work among several

engineers, you may want to use one of the following Advanced Flows.

FPGA Advanced Flow

1. Create a Project Navigator project and specify your top-level design file as follows:

a. Create a Project Navigator project.

b. Create files and add them to your project, including a user constraints (UCF) file.

c. Add any existing files to your project.

d. Edit the design files to specify design functionality.

e. Optionally, use the Language Templates to assist in coding of the design. f. Edit the design test bench or waveform files to drive stimulus for testing the design files. Optionally,

do the following:

Use the Test Bench Waveform Editor to specify stimulus for the design.

Use the Language Templates to assist in coding of the test bench.

g. Assign constraints, such as timing constraints, pin assignments, and area constraints.

Note: If you are working with an EDIF or NGC/NGO top-level source file and performed behavioral

simulation outside of Project Navigator, skip ahead to step 6.

2. Run behavioral simulation (also known as RTL simulation). 3. Repeat steps 1 and 2 until desired functionality is achieved. 4. Synthesize your design as follows:

a. If you do not want to use the default settings, set the synthesis properties.

b. Run the Synthesize process.

5. Optionally, run post-synthesis functional simulation. 6. Implement your design as follows:

a. If you do not want to use the default settings, set the implementation properties.

b. Translate your design.

c. Optionally, run post-Translate functional simulation.

d. Map your design. Optionally, do the following:

Run static timing analysis (for a partial timing analysis of logic delays without routing). Run post-Map partial timing simulation (for a partial timing analysis of logic delays without routing)

e. Place and Route your design. Optionally, do the following:

Run static timing analysis.

Run back annotation for the following:

Timing information



Pin locations

f. Review reports generated by the Implement Design process, such as the Map Report or the Place and Route Report, and change any of the following to improve your design:

Process properties

Constraints

Source files

7. Optionally, consider the following advanced implementation strategies to improve design performance:

Use the Floorplanner at any of the following points in the design flow to manually place logic:

Before Map

After Map but before Place and Route

After Place and Route

Set the Perform Timing Driven Packing and Placement Map Property. View the placed and routed design in FPGA Editor and manually route sections of the design.

Note: Manually routing is not recommended unless absolutely necessary.

Set multiple place and route passes for your design.

8. Modify the design as necessary, simulate, synthesize, and implement your design, as appropriate, until design requirements are met.

9. Run timing simulation to verify end functionality and timing of the design. 10. Program your Xilinx® device as follows:

a. Create a programming file (BIT) to program your FPGA.

b. Generate a PROM, ACE, or JTAG file for debugging or to download to your device.

c. Use iMPACT to program the device with a programming cable.

Optionally, run in-circuit verification.

Additional Advanced Flows

Following are additional advanced flows designed to help you meet your design requirements.

Advanced Flow More Information

Incremental Design Flow See the following:

Using Incremental Design Development System Reference Guide: See the

"Incremental Design" chapter.

Modular Design Flow Development System Reference Guide: See the

"Modular Design" chapter.



Partial Reconfiguration Flow Development System Reference Guide: See the "Partial Reconfiguration" chapter.

Guided Synthesis and Implementation Flow Development System Reference Guide: See the

following sections:

"Guided Mapping" section in the "MAP" chapter

"Guided PAR" section in the "PAR" chapter

Multi-Cycle Paths Flow Synthesis and Verification Design Guide: See the

"Using Pipelining" section in the "Coding Styles for FPGA Devices" chapter.

Design Entry Overview

Design entry is the first step in the ISE™ design flow. During design entry, you create your source files based on your design objectives. You can create your top-level design file by using a Hardware Description Language (HDL), such as VHDL, Verilog, or ABEL, or by using a schematic. You

specify your top-level module type when you create your project as described in Creating a Project.

You can use multiple formats for the lower-level source files in your design. Different source types are available, depending on your project properties (top-level module type, device type, synthesis tool, and language). You can create these source files in Project Navigator, as described in Creating a Source File. Some source types launch additional tools to help you create the file, as described in Source File Types.

For information on creating efficient designs, such as how to set up your design hierarchy and good

coding practices, refer to the following Xilinx® documentation:

Synthesis and Verification Design Guide, which includes the following chapters:

"Understanding High-Density Design Flow" "General HDL Coding Styles" "Coding Styles for FPGA Devices" XST User Guide, which includes HDL coding techniques. Development System Reference Guide, which contains information about the command line

software programs in the Xilinx Development System.

Application Notes, which discuss technical details.

Note: If you converted your design to an EDIF or NGC/NGO file, for example, using a synthesis

tool, you can skip the design entry processes and start with the implementation process.

http://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=application+notes



HDL Overview

You can use a hardware description language (HDL), such as VHDL, Verilog, or ABEL (for CPLDs), for your top-level or lower-level design files. HDL files describe the behavior and structure of system

and circuit designs. Using HDLs to design high-density devices allows you to do the following:

Use a top-down approach

You can use HDLs to create complex designs that require many designers to work together. After

an overall plan is determined, each designer works on a separate section of the design.

Run functional simulation early in the design cycle

You can verify your design functionality early in the flow by simulating the HDL description. Testing your design decisions at the register transfer level (RTL) or gate level before the design is

implemented allows you to make changes early in the design process.

Use a synthesis engine to translate your design to gates

Synthesis decreases design time by eliminating the need to define every gate. Synthesis to gates reduces the number of errors that may occur during a manual translation of the hardware description to a schematic design. Also, the synthesis tool can apply automation, such as machine encoding styles or automatic I/O insertion during optimization, resulting in greater efficiency.

Retarget your code to different architectures

You can use the same HDL design for new architectures with a minimum of recoding. This works especially well if you inferred, rather than instantiated, components. For details, see Instantiation

and Inference.

Additional details on the advantages of using HDLs are available in the Synthesis and Verification

Design Guide. See the following chapters to help you with your design:

"Introduction," which includes an overview of HDLs. "Understanding High-Density Design Flow," which discusses high-density designing, designing with

hierarchy, and design size versus performance.

Note: You must understand how to properly create hierarchy in your HDL file, as opposed to

creating a "flat" design.

"General HDL Coding Styles," which discusses general coding styles.

"Coding Styles for FPGA Devices," which discusses architecture-specific coding styles.

Review these chapters and consult any of the many HDL textbooks available. In addition, you can enroll in any of the Xilinx® training classes available from the Xilinx website. Click Education to

view the available classes and to sign up.

http://www.xilinx.com/cgi-bin/SW_Docs_Redirect/sw_docs_redirect?locale=en&topic=xilinx+home



Schematic Overview

Using schematics for your top-level or lower-level design files allows you to have a visual representation of your design. You can use schematics for your top-level design, your lower-level

design files, or both, as follows:

Top-level schematic

You can use a schematic as your top-level design and create the lower-level modules using any of the following source types: HDL files, state diagrams, CORE Generator™ cores, Architecture Wizard IP, or schematic files. To instantiate a lower-level module in your top-level design, you must create a schematic symbol from the lower-level module, and instantiate the schematic symbol. For more information, see Creating a Top-Level Schematic.

Note: You do not need to create schematic symbols for CORE Generator cores or for Xilinx®

Unified Library symbols. The CORE Generator software automatically generates schematic

symbols, and library symbols are predefined.

Lower-level schematic

You can use schematics to define the lower-level modules of your design. If the top-level design file is a schematic, you must create a schematic symbol from the lower-level schematic, and then instantiate the symbol in the top-level schematic. If the top-level design file is an HDL file, you must create an HDL instantiation template from the schematic, and then instantiate the template in the

top-level HDL file. For more information, see Creating a Lower-Level Schematic.

Entire design composed of schematics

You can create your entire design, including top-level and lower-level modules, using schematics. The design can be either flat or hierarchical. You must create schematic symbols from the lower-level schematics, and then instantiate them in the top-level schematic design. For more information,

see Creating a Top-Level Schematic and Creating a Lower-Level Schematic.

All schematics are ultimately converted to either VHDL or Verilog structural netlists before being

passed on to your synthesis tool during the Synthesize process.

Note: For more information on working with schematics in Project Navigator, see the Schematic and Symbol Editors Help. For information on Xilinx Unified Library symbols, see the Components Overview and the Libraries Guides available from the ISE™ Software Manuals collection. For

information on cores, see the Intellectual Property and Cores Overview.

Schematic Design Methods

When using a schematic as your top-level design, use either of the following methods to describe

the lower-level modules.



Top-Down Schematic Design Method

Using this method, you create a top-level block diagram description of the design using a schematic. Then, you "push down" into each symbol and define its behavior using an HDL or

schematic file. To use this method, do the following:

1. Create your top-level schematic as described in Creating a Project, selecting Schematic as your

top-level module type. 2. To create individual top-level blocks for the design, use the Symbol Wizard, as described in

Creating a Symbol. When using the Symbol Wizard, ensure that you use the following default

settings:

Pin Name Source: Specify Manually

Shape: Rectangle

Note: The Symbol Wizard allows you to add input, output, or bidirectional pins. You can create bus (multi-signal) pins using parentheses, for example: inbus(7:0).

After you click Finish, the symbol is added to the local symbol library for the project and it opens in

the Project Navigator Workspace. If needed, you can edit the symbol in the Workspace.

3. In the Project Navigator Workspace, click the tab for your top-level schematic. 4. Instantiate your new symbol in the top-level schematic, as described in Adding a Symbol Instance. 5. Right-click the symbol you added, and select Symbol > Push into Symbol.

6. You are prompted to create one of the following template file types:

Schematic

The schematic contains I/O markers that correspond to the pins in the block symbol you created. Build the schematic by adding symbols as described in Adding a Symbol Instance. You can use

Xilinx® Unified Library symbols or symbols that you create.

VHDL or Verilog

The template contains the HDL port descriptions that correspond to the pins in the block symbol you created. You can then add the behavior of the module. The ISE Language Templates provide a convenient method for you to insert pre-built language and functional code samples into your HDL

file. For details, see Working with Language Templates.

Note: The next time you use the Push into Symbol command, the HDL or schematic file opens in

the Project Navigator Workspace.

7. Complete your top-level schematic, starting with step 2 in Creating a Top-Level Schematic.



Bottom-Up Schematic Design Method

Using this method, you create a top-level schematic design and then create lower-level functional blocks to instantiate in the top-level design using either HDL source files or a schematic composed

of Xilinx unified library symbols. To use this method, do the following:

1. Create your top-level schematic as described in Creating a Project, selecting Schematic as your top-level module type.

2. To create lower-level modules, create a new source file as described in Creating a Source File, selecting one of the following file types:

ABEL-HDL Module (CPLDs only)

After you click Finish, the HDL file is added to the project and opens in the Project Navigator Workspace. You can then define the behavior of the module. The ISE Language Templates provide a convenient method for you to insert pre-built language and functional code samples into your HDL

file. For details, see Working with Language Templates.

IP

If you selected a CORE Generator core, the CORE Generator software opens and allows you to define your core. For details, see the CORE Generator Help. If you selected an Architecture Wizard core, the Architecture Wizard tool opens and allows you to define your core. For information, click the More Info buttons in the Architecture Wizard.

Schematic

After you click Finish, the schematic file is added to the project and opens in the Project Navigator

Workspace. Build the schematic by adding symbols as described in Adding a Symbol Instance. You can use Xilinx Unified Library symbols or symbols that you create.

State Diagram

After you click Finish, the StateCAD software displays in which you can create your state machine.

For details, see Working with State Machines.

Verilog Module or VHDL Module

Optionally, you can use the New Source Wizard to predefine the modules ports, which ensures that the appropriate port definitions appear in the HDL file. After you click Finish, the HDL file is added

to the project and opens in the Project Navigator Workspace. Define the behavior of the module. The ISE Language Templates provide a convenient method for you to insert pre-built language and

functional code samples into your HDL file. For details, see Working with Language Templates.

3. In the Module View tab of the Sources in Project window, select the lower-level module file. 4. Create a schematic symbol from the lower-level module, as described in Creating a Schematic

Symbol.

Note: You do not need to convert CORE Generator cores to schematic symbols, because the

CORE Generator software automatically generates schematic symbols.



5. Instantiate your new symbol in the top-level schematic as described in Adding a Symbol Instance. 6. Complete your top-level schematic design, starting with step 2 in Creating a Top-Level Schematic.

Schematic and Symbol Editor Tips

For general tips in creating schematics, see Schematic Design Tips. Following are tips for working

with the Schematic and Symbol Editors:

To update all the schematics in your design with current symbols from your symbol directories, run the Update All Schematic Files process. If you edit a symbol, you must run this process. For details, see Updating All Schematic Files in your Design.

To change the color scheme of the Schematic and Symbol Editors, use Edit > Preferences. For

details, see Setting Color Preferences. To Zoom In on a schematic or symbol,press Ctrl and drag the mouse down and to the right. To

Zoom Out, press Ctrl and drag the mouse up and to the left. For details, see Zooming. To change the sheet size, click the schematic background, and select Edit > Object Properties.

For details, see Resizing a Sheet. To rename a net, right-click the net and select Rename Selected Net. You can rename a single

branch of a net or the entire net. For details and alternate methods, see Naming a Net. To quickly add I/O markers and connecting wires to the symbol pins, select Add > I/O Marker and

then use the mouse to drag a selection box around either the input or the output pins of the symbol. For alternate methods, see Adding an I/O Marker.

To quickly find all branches of a net even if they are not visibly connected, select Tools > Query.

For details, see Running a Query.

Simulation Overview

During HDL simulation, the simulator software verifies the functionality and timing of your design or portion of your design. The simulator interprets VHDL or Verilog code into circuit functionality and displays logical results of the described HDL to determine correct circuit operation. Simulation

allows you to create and verify complex functions in a relatively small amount of time.

Simulation takes place at several points in the design flow. It is one of the first steps after design entry and one of the last steps after implementation, as part of verifying the end functionality and performance of the design. Simulation is an iterative process, which may require repeating until both design functionality and timing is met. For a typical design, simulation comprises the following

high-level steps:

1. Compilation of the simulation libraries

2. Creation of the design and test bench

3. Functional simulation

4. Implementation of the design and creation of the timing simulation netlist

5. Timing simulation

Note: See the Synthesis and Verification Design Guide for detailed information on Xilinx®

simulation capabilities.



Simulation Libraries

Most designs are built with generic code, so device-specific components are not necessary. However, in certain cases, it may be required or beneficial to use device-specific components in the code to achieve the desired end circuit implementation and results. When you instantiate a component in your design, the simulator must reference a library that describes the functionality of the component to ensure proper simulation. Xilinx® provides the following simulation

libraries for simulating primitives and cores:

UNISIM library for functional simulation of Xilinx primitives XilinxCoreLib library for functional simulation of Xilinx cores SIMPRIM library for timing simulation of Xilinx primitives SmartModel simulation library for both functional and timing simulation of Xilinx SmartModel-based

primitives

Note: For details on device primitives, see the Libraries Guides, available from the ISE™ Software

Manuals collection. For details on cores, see the CORE Generator Help. For additional information on simulation libraries, including library specification and compilation, see the Synthesis and

Verification Design Guide.

UNISIM Library

This library is used during functional simulation and contains descriptions for all the device primitives, or lowest-level building blocks. You must specify the UNISIM library anytime you include a device primitive listed in the Libraries Guides in your source code. Specify this library as follows:

VHDL

Add the following library declaration to the top of your HDL file:

library UNISIM;

use UNISIM.Vcomponents.all;

Using this declaration, the simulator references the functional models for all device primitives. In addition to this declaration, you must compile the library and map the library to the simulator. This is

covered in the "Simulation Library Compilation" section below.

Verilog

When you invoke the simulator from within Project Navigator, the simulator script automatically references the UNISIMS_VER library. In addition, you must compile the library and map the library to the simulator. This is covered in the "Simulation Library Compilation" section below.

If you are running the simulator outside of Project Navigator, the UNISIMS_VER library must be referenced to the simulator. The method used to reference this library depends on the simulator.

Please refer to the documentation for your simulator.



XilinxCoreLib Library

This library is used during functional simulation for designs that contain cores created by the Xilinx

CORE Generator™ software. This library is specified as follows:

VHDL

The CORE Generator software automatically generates a VHD file, which is a VHDL wrapper file that includes the library declaration. In addition, you must compile the library and map the library to

the simulator. This is covered in the "Simulation Library Compilation" section below.

Verilog

When you invoke the simulator from within Project Navigator, the simulator script automatically references the XilinxCoreLib_VER library, and the CORE Generator software generates a V file, which is a Verilog wrapper file. In addition, you must compile the library and map the library to the

simulator. This is covered in the "Simulation Library Compilation" section below.

If you are running the simulator outside of Project Navigator, the XilinxCoreLib_VER library must be referenced to the simulator. The method used to reference this library depends on the simulator.

Please refer to the documentation for your simulator.

Note: This library does not apply to CPLDs.

SIMPRIM Library

This library is used for structural simulation netlists produced after implementation, including timing

simulation. This library is specified as follows:

VHDL

The library declaration is automatically written by the netlist. In addition, you must compile the library and map the library to the simulator. This is covered in the "Simulation Library Compilation" section below.

Verilog

When you invoke the simulator from within Project Navigator, the simulator script automatically references the SIMRPRIMS_VER library. In addition, you must compile the library and map the

library to the simulator. This is covered in the "Simulation Library Compilation" section below.

If you are running the simulator outside of the Project Navigator environment, the SIMRPRIMS_VER library must be referenced to the simulator. The method used to reference this

library depends on the simulator. Please refer to the documentation for your simulator.



SmartModel Simulation Library

This library is used for the functional and timing simulation of complex FPGA components, such as the PPC405 and the GT10 components. To simulate these complex SmartModel components, see the Synthesis and Verification Design Guide.

Note: This library does not apply to CPLDs.

Simulation Library Compilation

Before you can simulate your design, you must compile the applicable libraries and map them to the simulator. The Project Navigator Compile HDL Simulation Libraries process automates this task. It compiles all of the relevant libraries for a given device family and writes a library mapping file to the project directory in which it was invoked. For details on running this process, see Compiling HDL Simulation Libraries.

If you want to compile the libraries outside of Project Navigator, you can run the CompXLib program from the command line. For information on CompXLib options and capabilities, see the Synthesis

and Verification Design Guide, or type the following at the command line: compxlib -help.

Test Benches

To simulate your design, you need both the design under test (DUT) or unit under test (UUT) and the stimulus provided by the test bench. A test bench is HDL code that allows you to provide a documented, repeatable set of stimuli that is portable across different simulators. A test bench can be as simple as a file with clock and input data or a more complicated file that includes error checking, file input and output, and conditional testing.

Note: Verilog designers sometimes refer to a Verilog test fixture. "Test bench" and "test fixture" are

used synonymously throughout this documentation.

You can create the test bench using either of the following methods:

Text editor

This is the recommended method for verifying complex designs. It allows you to use all the features available in the HDL language and gives you flexibility in verifying the design. Although this method may be more challenging in that you must create the code, the advantage is that it may produce more precise and accurate results than using the Test Bench Waveform Editor.

To assist in creating the test bench, you can create a template that lays out the initial framework, including the instantiation of the UUT and the initializing stimulus for your design. Create this template as described in Creating a Source File, selecting VHDL Test Bench or Verilog Test Fixture as your source type.



Note: You can also use the Project Navigator Language Templates to create the VHDL or Verilog

code for both the test bench and the design. See Working with Language Templates for details.

Xilinx® Test Bench Waveform Editor

This is the recommended method for verifying less complicated simulation tasks and is recommended if you are new to HDL simulation. It allows you to graphically enter the test bench to drive the stimulus to your design and allows you to check the outputs for the correct values. For detailed information, see the ISE Simulator Help.

Test Bench Strategies

Because the test bench becomes a part of the hierarchy in your code, the following is

recommended:

Make the test bench the top level of the code.

The test bench instantiates the unit under test (UUT), and stimulus is applied from the top-level test

bench to the lower-level design or portion of the design being tested.

Use the instance name UUT for the instantiated unit under test.

This is the default instance name that Project Navigator expects.

You can use the same test bench for both functional and timing simulation. Following are general

recommendations that apply to both types of simulation:

Initialize all input ports at simulation time zero, but do not drive expected stimulus until after 100

nanoseconds (ns) simulation time.

During timing simulation, a global set/reset signal is automatically pulsed for the first 100 ns of simulation. To keep the test bench consistent for both timing and functional simulation, it is

recommended that you hold off input stimulus until the global set/reset has completed.

Note: You can still run the clocks during the first 100 ns of simulation.

Do not provide data to the input ports at the same time as the clock.

For non-timing simulation, this can cause some signals to be applied before the clock and some after the clock. Apply data only after the clock is applied to the input ports. This makes it easier to

keep track of which clock edge data changes are being applied.

If output checking is performed in the test bench, apply data just before the next clock cycle.

For timing simulation, it could take up to an entire clock cycle for the data to propagate through the logic and settle to a known value. Checking data too early in the clock cycle may yield incorrect

results.



Simulation Environments

Every simulator operates differently, but simulating a design comprises the following general steps:

1. Compilation

The simulator converts the HDL code from the design or the test bench into an intermediate form that it can understand. During this step, code parsing and syntax checking also take place. If a

syntax or coding problem is found, it is flagged so you can correct it before proceeding.

2. Elaboration

The simulator merges the pieces of compiled code to form a cohesive simulation platform. The simulator references simulation libraries and uses them as a part of the overall simulation model. If any pieces of the design are missing, possibly caused by an improperly referenced library or

connection issues between the pieces of the design, an error is reported.

3. Execution

Execution is the most significant step in simulation. The simulator processes the elaborated design to derive the design functionality. During execution, "simulation time" passes in which the simulator updates each node in the simulation, including the design outputs, to the proper values at the proper time based on the input stimulus to the design. During this stage, you can view simulation

values, messages, and simulation waveforms.

Note: For detailed information on running the Xilinx® ISE™ Simulator, see the ISE Simulator Help.

For information on how to operate another simulator, refer to the documentation for your simulator.

Functional Simulation

After you compile the simulation libraries and create the test bench and design code, you can perform functional simulation on the design. Functional simulation is an iterative process, which may require multiple simulations to achieve the desired end functionality of the design. Therefore, it is important to set up the proper infrastructure for this type of simulation. Spending time up front

may save time in back end design debugging. Following are general recommendations:

Spend time up front to create a good test bench.

Creating a test bench that you can use for both functional and timing simulation can save time. For

details, see Test Benches.

Ensure that your libraries are properly compiled and mapped.

If your design includes UNISIM components or Xilinx® CORE Generator™ cores, make sure that your libraries are properly compiled and mapped to the simulator. If you are using the ISE™ Simulator or the ModelSim® Xilinx Edition simulator, this is automatically done for you. If you are using a SmartModel component (for example, PPC405 or Gigabit Transceiver), ensure that the



simulator you are using supports the SWIFT interface and the SmartModels are properly set up to interface to the simulator. For details, see Simulation Libraries.

Automate the compilation and elaboration simulation steps.

When you invoke the simulator from within Project Navigator, the ISE tools automatically run these steps. If you are running the simulator outside of Project Navigator, it is recommended that you create a script or use another method to automate these steps. For more information, refer to the documentation for your simulator.

Customize the simulator interface to present the information needed to debug the design.

You may want to include the information console, the structure or hierarchy view, and the waveform viewer as well as other facilities to evaluate the simulation. Customization can improve the simulation experience and can be tied into the automation of the compilation and elaboration steps. If you are using a waveform viewer as a part of simulation debugging, organize the waveform view to display the proper signals in the proper order with the proper radices. This saves time and helps prevent confusion in interpreting simulation results. For information on the ISE Simulator, see the

ISE Simulator Help.

Note: You can perform simulation in different ways, and what works best in one case may not necessarily apply to another. These are general recommendations that can improve simulation in

most cases.



Timing Simulation

After you implement the design using the ISE™ software, you can perform timing simulation on the design. Timing simulation allows you to check that the implemented design meets all timing requirements and behaves as you expect in the device. Performing a thorough timing simulation ensures that the finished design is free of defects that may be missed otherwise. Following are a few examples of defects that timing simulation can help you find:

Post-synthesis and implementation functionality changes Dual-port RAM collisions Missing component generics for VHDL Missing module defparams for Verilog Missing or improperly applied timing constraints

Operation of asynchronous paths

You can perform timing simulation in conjunction with in-system testing to help you further understand how the device is operating. For more information, see the ChipScope Pro Debugging Overview.

Note: See the Synthesis and Verification Design Guide for detailed information on Xilinx® timing

simulation.

Timing Simulation Steps

To perform a full timing simulation, the design must be placed and routed. Following are the general

steps in a full timing simulation:

1. Ensure that your libraries are properly compiled and mapped.

Ensure that the SIMPRIM library is properly compiled and mapped to the simulator. If you are using the ISE Simulator or the ModelSim® Xilinx® Edition simulator, this is automatically done for you. If you are using a SmartModel component (for example, PPC405 or Gigabit Transceiver), ensure that the simulator you are using supports the SWIFT interface and the SmartModels are properly set up

to interface to the simulator. For details, see Simulation Libraries.

Note: If you already used SmartModels during functional simulation, you do not need to set them

up again.

2. The netlister generates a structural simulation netlist, based on the models for the device primitives in the design, and an associated standard delay format (SDF) file that contains all of the annotated

delays for the design for use during simulation.

If you are using Project Navigator, run the Simulate Post-Place and Route Model (FPGAs) or Simulate Post-Fit Model (CPLDs) process to generate the netlist. For details, see Performing

Post-Place & Route Simulation or Performing Post-Fit Simulation.

If you are running from the command line, use NetGen to create the netlist files. For information on using NetGen, see the Development System Reference Guide or the Synthesis and Verification

Design Guide.



3. Load the SDF file.

The instructions for loading the SDF file differ depending on the simulator. Please refer to the simulator documentation. If you are using the ISE Simulator, see the ISE Simulator Help.

4. Use the structural timing netlist, SDF file, and test bench to perform a timing simulation.

Timing simulation is similar to functional simulation, except that you are viewing a structural implementation of the design. In addition, you must account for the timing delays in the design. When you invoke the simulator from within the Project Navigator, the ISE tools automatically run these steps. For more information, see the following topics:

After Place and Route (FPGAs), see Performing Post-Place & Route Simulation.

After Fit (CPLDs), see Performing Post-Fit Simulation.

If you are running the simulator outside of the Project Navigator environment, refer to the

documentation for your simulator.

XST Synthesis Overview

After design entry and optional simulation, you run synthesis. From the Project Navigator, double-click Synthesize in the Processes for Source window to run the synthesis process.

The ISE™ software includes Xilinx® Synthesis Technology (XST), which synthesizes VHDL, Verilog, or mixed language designs to create Xilinx-specific netlist files known as NGC files. Unlike output from other vendors, which consists of an EDIF file with an associated NCF file, NGC files contain both logical design data and constraints. XST places the NGC file in your project directory and the file is accepted as input to the Translate (NGDBuild) step of the Implement Design process. To specify XST as your synthesis tool, you must set the Synthesis Tool Project Property to XST, as described in Changing the Target Device and Design Flow. For details on using XST, see the XST User Guide.

Note: You can set the Synthesis Tool to XST or to a partner synthesis tool. For details on using partner tools, see Using Synplify or Synplify Pro for Synthesis, Using LeonardoSpectrum for

Synthesis, or Using Precision for Synthesis.



XST Design Flow Overview

The following figure shows the flow of files through the XST software.

XST Input and Output Files

XST supports extensive VHDL and Verilog subsets from the following standards:

VHDL: IEEE 1076-1987, IEEE 1076-1993, including IEEE standard and Synopsys®

Verilog: IEEE 1364-1995, IEEE 1364-2001

In addition to a VHDL or Verilog design description, XST can also accept the following files as input:

XCF

Xilinx constraints file in which you can specify synthesis, timing, and specific implementation constraints that can be propagated to the NGC file.

Core files

These files can be in either NGC or EDIF format. XST does not modify cores. It uses them to inform area and timing optimization.

Note: Cores are supported for FPGAs only, not CPLDs.

In addition to NGC files, XST also generates the following files as output:



Synthesis Report

This report contains the results from the synthesis run, including area and timing estimation. For details, see Viewing a Synthesis Report.

RTL schematic

This is a schematic representation of the pre-optimized design shown at the Register Transfer Level (RTL). This representation is in terms of generic symbols, such as adders, multipliers, counters, AND gates, and OR gates, and is generated after the HDL synthesis phase of the synthesis process. Viewing this schematic may help you discover design issues early in the design process.

For details, see Viewing an RTL Schematic - XST.

Technology schematic

This is a schematic representation of an NGC file shown in terms of logic elements optimized to the target architecture or "technology," for example, in terms of LUTs, carry logic, I/O buffers, and other technology-specific components. It is generated after the optimization and technology targeting phase of the synthesis process. Viewing this schematic allows you to see a technology-level representation of your HDL optimized for a specific Xilinx architecture, which may help you discover

design issues early in the design process. For details, see Viewing a Technology Schematic - XST.

Note When the design is run in Incremental Synthesis mode, XST generates multiple NGC and

NGR files, which each represent a single user design partition.

XST Detailed Design Flow

The following figure shows each of the steps that take place during XST synthesis. The following

sections describe each step in detail.



HDL Parsing

During HDL parsing, XST checks whether your HDL code is correct and reports any syntax errors.

HDL Synthesis

During HDL synthesis, XST analyzes the HDL code and attempts to infer specific design building blocks or macros (such as MUXes, RAMs, adders, and subtracters) for which it can create efficient technology implementations. To reduce the amount of inferred macros, XST performs a resource sharing check. This usually leads to a reduction of the area as well as an increase in the clock

frequency.

Finite state machine (FSM) recognition is also part of the HDL synthesis step. XST recognizes FSMs independent of the modeling style used. To create the most efficient implementation, XST uses the target optimization goal, whether area or speed, to determine which of several FSM

encoding algorithms to use.

You can control the HDL synthesis step using constraints. You can enter constraints using any of the following methods:

HDL source file

Enter VHDL attributes or Verilog metacomments.

XCF

Enter global parameters and module-level constraints in the Xilinx constraints (XCF) file. See the "Design Constraints" chapter of the XST User Guide for more information on the use of constraints

in the XCF file.

Project Navigator Process Properties

Set global parameters, such as the optimization goal or effort level. You can modify the synthesis

properties in the following tabs of the Synthesize Process Properties dialog box:

Synthesis Options HDL Options Xilinx Specific Options

Default property values are used for the Synthesize process, unless you modify them.

Note For more information on entering constraints, see Constraints Entry Methods.

Low Level Optimization

During low level optimization, XST transforms inferred macros and general glue logic into a technology-specific implementation. The flows for FPGAs and CPLDs differ significantly at this

stage as follows:

Note: For a list of supported FPGAs and CPLDs, see Architecture Support.



FPGA Flow

The FPGA flow is timing-driven and can be controlled using constraints, such as PERIOD and OFFSET. During low level optimization, XST infers specific components, such as the following:

Carry logic (MUXCY, XORCY, MULT_AND) RAM (block or distributed) Shift Register LUTs (SRL16, SRL16E, SRLC16, SRLC16E) Clock Buffers (IBUFG, BUFGP)

Multiplexers (MUXF5, MUXF6, MUXF7, MUXF8)

The use of technology-specific features may come from a macro implementation mechanism or from general logic mapping. Due to mapping complexity issues, not all available FPGA features may be used. The FPGA synthesis flow supports advanced design and optimization techniques, such as Register Balancing, Incremental Synthesis, and Modular Design.

Note: For information on Register Balancing, see the "Design Constraints" chapter of the XST User Guide; for information on Incremental Synthesis, see the "Incremental Synthesis Flow" section in

the "FPGA Optimization" chapter. For information on Modular Design, see the "Modular Design" chapter of the Development System Reference Guide. For information on specific components, see

the Libraries Guides, available from the ISE Software Manuals collection.

CPLD Flow

The CPLD flow is not timing driven. You cannot specify the frequency of a clock or of an offset value. The goal of the CPLD flow is to reduce the number of logic levels. During low level optimization, XST generates a netlist that contains elements such as AND and OR gates. The CPLD Fitter then determines how to fit these equations to the targeted device. XST supports a special optimization mode, called Equation Shaping, in which XST optimizes and reduces the Boolean equations to sizes accepted by device macrocells. This forces the CPLD Fitter to retain the equation modifications through the KEEP and COLLAPSE constraints in the NGC file.

Note: Equation Shaping only applies to CPLDs. For information on Equation Shaping, see the

"CPLD Optimization" chapter of the XST User Guide.



Compile Time Strategies

Use the following strategies to reduce synthesis compile time.

Incremental Synthesis

Incremental synthesis allows you to resynthesize only the modified portions of your design, which reduces your overall synthesis compile time. Following are the main types of incremental synthesis:

Block level

The synthesis tool resynthesizes the entire block if at least one modification was made in the block.

Gate or LUT level

The synthesis tool attempts to identify the exact changes made to the design and generates the

final netlist with minimal changes.

XST supports block level incremental synthesis. To use the incremental synthesis flow with XST, you must divide your design into several partitions. XST considers each partition a separate unit and generates an NGC netlist file for each. If you make a change to just one partition, XST only resynthesizes the partition you changed, and regenerates the corresponding NGC netlist file. During re-synthesis, XST is aware of all the partitions in the design and re-optimizes the changed

block based on its context with the rest of the design.

Note: For more information, see the "Incremental Synthesis Flow" section in the "FPGA Optimization" chapter of the XST User Guide.

Modular Design

In the Modular Design approach, you divide your design into several modules, but the modules are synthesized separately by a single designer or by multiple designers. For each module, a separate

NGC file is generated, and these netlists are linked during the Translate (NGDBuild) process. The difference between this approach and Incremental Synthesis is that XST is not aware of the other

modules when it synthesizes a module.

Note: For information on Modular Design, see the "Modular Design" chapter of the Development

System Reference Guide.



Area Reduction Strategies

Because timing optimization techniques lead to an area increase, area reduction approaches vary depending on the design optimization goal, whether for area or speed. However, the following

methods can be used in both cases.

Note: For detailed information on constraints, see the Constraints Guide.

FPGA Resource Utilization

Following are checks that can help you reduce area:

Check HDL Advisor messages.

In some cases, XST provides HDL Advisor messages, which show you how to reduce area or increase speed for your design. For example, XST may detect a shift register in your design, but due to the presence of a Reset signal, specific SRL resources cannot be used. In this case, the HDL Advisor suggests modifying your design by removing the Set or Reset signal to achieve an area gain. Monitor these HDL Advisor messages in the Console tab of the Project Navigator Transcript window, or double-click View Synthesis Report.

Check the use of FPGA-specific resources.

Check the Device Utilization Summary section of the Synthesis Report for the use of FPGA-specific resources, such as BRAM, hardware multipliers, and DSP48. If these resources are available, change your HDL code or change the options in the Synthesize Process Properties dialog box to use these resources. For example, you can use available BRAM resources to implement state

machines or part of your general RTL description.

Control of Macro Implementation

XST allows you to choose different implementation methods for a particular resource. Following are the implementation methods available, including the limitations of each:

Multiplier with a constant

You can implement the multiplier using any of the following methods:

Full multiplier implementation KCM

CSD

The efficiency of each method depends on the size of the operand, the size of the constant, and the constant value. XST can make an automatic choice between full or KCM implementation. However, the CSD method must be activated manually using the MULT_STYLE constraint.

Finite state machine encoding



Occasionally, XST may make a less-than-optimal choice during automatic selection of the encoding. Try several encoding methods, starting with compact encoding to see if you can achieve

better results.

Note: For more information about supported macros and how to control their implementation, see

the "HDL Coding Techniques" chapter of the XST User Guide.

Synthesis Process Properties

You can set all of the following properties in the Synthesis Process Properties dialog box to help

reduce area use:

Resource Sharing

In most cases, resource sharing improves area results. In some cases, XST may miss the resource sharing optimization and implement more arithmetic operations than is required. Check the Synthesis Report to identify such situations. To correct this situation, simplify your HDL code to match a coding style documented in the XST User Guide. To apply the RESOURCE_SHARING

synthesis constraint, enable the Resource Sharing HDL Option.

Pack I/O Registers into IOBs

Packing registers into IOBs reduces slice utilization. To apply the IOB synthesis constraint, set the Pack I/O Registers into IOBs Xilinx Specific Option to Yes.

Optimize Instantiated Primitives

By default, XST does not optimize instantiated primitives. If you created any of the design blocks using schematics, enable the Optimize Instantiated Primitives Xilinx Specific Option to improve your

results.

Convert Tristates to Logic

If you target an architecture that supports internal tristates and your design has tristate inferences, XST converts the tristates to logic by default. Replacing internal tristates with logic usually leads to an increase in speed but may also lead to an area increase. To disable tristate to logic conversion, set the Convert Tristates to Logic Xilinx Specific Option to No.

Note: This option is only available when you set the Property display level to Advanced.

Special Considerations for Speed Optimized Designs

The following strategies are specific to designs optimized for speed. Timing optimization generally leads to an area increase, so limiting timing optimization leads to a reduction in the overall area. You can set all of the following properties in the Synthesis Process Properties dialog box to help

reduce area use:



Slice Utilization Ratio Adjust timing constraints and area control using the SLICE_UTILIZATION_RATIO constraint. This constraint defines the percentage of slices XST can use to implement your design or a block of your design. By default, it is set to 100 percent for the entire design. Reduce this value to improve area utilization. If XST cannot meet the constraint, XST does not take any of the area constraints into

consideration. To apply this constraint, use the Slice Utilization Ratio Synthesis Option.

If you run XST without timing constraints, XST attempts to optimize all clocks to improve the maximum operating frequency (Fmax) of the entire design. The timing optimization is based on how each macro is implemented and uses register and logic replication. Register and logic replication is directly related to an area increase and can be controlled using the SLICE_UTILIZATION_RATIO constraint. If the SLICE_UTILIZATION_RATIO constraint is met, the timing constraints stay within the area constraint. If the SLICE_UTILIZATION_RATIO constraint is not met, timing optimization is done without area constraints.

Note: You can synthesize the design without timing constraints to see the preliminary timing

results. However, without timing constraints, XST does not know the requirements for design speed and optimizes the most critical clock first. The clock chosen by XST as most critical may not be the same clock that you consider the most critical. Specifying timing constraints allows XST to better

prioritize timing optimization and also limits logic and register replication.

Read Cores If your design contains cores, apply the READ_CORES constraint. This provides precise information about resources that are already consumed. To apply this constraint, enable the Read Cores Synthesis Option. Note: XST does not optimize cores. It uses them for area and speed estimation and optimization.

Max Fanout

The value set for the MAX_FANOUT synthesis constraint has a direct influence on logic replication, regardless of whether the design is optimized for speed or for area. For example, if you set the value to 100 and the actual fanout of a net is more than 100, XST replicates logic to meet the

maximum fanout requirements. To apply this constraint, set the Max Fanout Xilinx Specific Option.

Register Balancing

Limit the REGISTER_BALANCING constraint to a set of clocks or set of blocks where the register balancing must be performed. Register balancing improves design speed but may lead to an increased number of registers. To use this option, you must set the Register Balancing Xilinx Specific Option to Yes, Forward, or Backward. By default, it is set to No.

Special Considerations for Area Optimized Designs

Identify the blocks that are not critical from a timing perspective, and try to optimize them with an

area optimization goal. Apply the OPT_MODE and KEEP_HIERARCHY constraints to these blocks.

Note: Timing optimization is not performed on the selected blocks.



Speed Strategies

Many of the strategies covered in this section can be controlled through options in the Synthesis

Process Properties dialog box.

Note: For detailed information on constraints, see the Constraints Guide.

Design Considerations

Before attempting to improve your design performance, do the following:

Flatten the hierarchy of your design for better results.

This is the default mode, which allows XST to perform efficient optimization across module boundaries. If needed, you can control the KEEP_HIERARCHY constraint using the Keep Hierarchy Synthesis Option.

Run XST speed optimization without timing constraints on the initial run.

This is the default mode, which allows you to see the performance that can be achieved with no constraints. In this case, XST attempts to optimize the most critical or slowest clock or critical region of the design. If optimization is achieved, XST selects another critical clock or region to improve. However, the clock chosen by XST as most critical may not be the same clock that you consider the most critical. Therefore, on subsequent synthesis runs, specify timing constraints for synthesis to

guide XST during the optimization process.

Ensure that XST reads in your black box cores (EDIF or NGC files) during the optimization process.

This is the default mode, which allows XST to use timing information from the cores to better optimize the synthesizable part of the design. If needed, you can control the READ_CORES constraint using the Read Cores Synthesis Option.

Note: XST does not modify or optimize cores. It uses them for area and speed estimation and

optimization.

Speed Strategy Quick Methods

The following methods do not require detailed design analysis and can be applied globally to the entire design using the options in the Synthesis Process Properties dialog box:

Optimization Effort

By default, XST synthesizes designs using Normal optimization effort. However, setting the effort to High may improve speed up to five percent, at the cost of increased runtime. To apply the

OPT_EFFORT constraint, set the Optimization Effort Synthesis Option.



Register Balancing

Use register balancing to improve speed at the cost of increased area. If your design no longer fits after using register balancing, make a precise timing analysis of your design and apply register balancing only on the most critical clocks or regions of your design. To use the REGISTER_BALANCING constraint, you must set the Register Balancing Xilinx Specific Option to Yes, Forward, or Backward. By default, it is set to No.

Note: This does not apply to CPLDs.

Convert Tristates to Logic

If you target an architecture that supports internal tristates and your design has tristate inferences, convert the tristates to logic. The replacement of internal tristates by logic usually leads to an increase in speed and area. However, this replacement can lead to an area reduction, because the

logic generated from tristates can be combined and optimized with surrounding logic. To convert tristates, set the Convert Tristates to Logic Xilinx Specific Option to Yes.

Note: This does not apply to CPLDs. This option is only available when you set the Property display

level to Advanced.

Optimize Instantiated Primitives

By default, XST does not optimize instantiated primitives. If some of the design blocks are created as schematics, enable the OPTIMIZE_PRIMITIVES constraint by enabling the Optimize Instantiated

Primitives Xilinx Specific Option.

Note: This does not apply to CPLDs.

Resource Sharing

In most cases, resource sharing improves area and speed results. However, for some designs, disabling resource sharing can improve speed up to 10 percent. To disable the

RESOURCE_SHARING synthesis constraint, disable the Resource Sharing HDL Option.

Speed Strategy In-Depth Methods

If the quick methods do not improve your design, analyze your timing reports, including critical path information, to find out how the design can be improved. Check the number of analyzed and failed paths for a better understanding of the significance of each of the timing problems. If you ran XST with timing constraints, you can check the Timing Detail section of the Synthesis Report for information on the number of destination registers for failed paths. For information on how to view these reports, see Viewing a Synthesis Report and Viewing a Post-Place and Route Static Timing

Report.

Following are additional checks that can help you improve speed for FPGA designs. These checks do not apply to CPLDs.



Check HDL Advisor messages.

These messages help you improve your design. For example, if you place a KEEP constraint on a net and this constraint prevents XST from improving design speed, the XST HDL Advisor points out this limitation. Monitor these HDL Advisor messages in the Console tab of the Project Navigator Transcript window, or double-click View Synthesis Report.

Check the use of FPGA-specific resources.

Check the use of resources, such as block versus distributed RAM and LUT-based versus hardware multipliers. For example, if your critical path goes through a multiplier and the multiplier is implemented using a MULT18X18 primitive, you can increase the speed by changing the

implementation to a LUT structure and pipelining it.

Control macro implementation.

XST allows you to choose different implementation methods for a particular resource. Following are

the different implementation methods available, including the limitations of each:

Multiplier with a constant

You can implement the multiplier using any of the following methods:

Full multiplier implementation KCM

CSD

The efficiency of each method depends on the size of the operand, the size of the constant, and the constant value. XST can make an automatic choice between full or KCM implementation. However,

the CSD method must be activated manually using the MULT_STYLE constraint.

Finite state machine encoding

Occasionally, XST may make a less-than-optimal choice during automatic selection of the encoding. Try several encoding methods starting with compact encoding to see if you can achieve

better results.

Note: For more information about supported macros and how to control their implementation, see

the "HDL Coding Techniques" chapter of the XST User Guide.

Adjust Slice Utilization Ratio.

The SLICE_UTILIZATION_RATIO constraint, which is set to 100 percent for the entire design by default, controls the amount of logic and register replication that takes place during timing optimization. For example, if you specify a ratio of 50 percent for one of the blocks in your design, but XST detects that the actual ratio is 48 percent, XST performs timing optimization until timing constraints are met or until the 50 percent limit is reached. If the timing is not met, but the ratio limit is reached, decrease the ratio limit to see if it is possible to meet the timing constraints. If the timing constraints are met after decreasing the ratio, find a way to reduce the area for less critical blocks to



allow greater area for the critical block. To apply this constraint, use the Slice Utilization Ratio Synthesis Option.

Adjust Max Fanout.

The value set for the MAX_FANOUT synthesis constraint controls logic replication. If the critical path goes through a net with a high fanout, XST replicates the logic or inserts a buffer. In general, this improves the speed of the design, but the logic replication for this net may be excessive or insufficient. You can apply a different maximum fanout value to a particular net to force XST to further replicate or reduce the net to improve performance. To apply this constraint, set the

MAX_FANOUT constraint on a specific signal in the HDL code.

Disable equivalent register removal.

In general, removing equivalent registers leads to better area and speed optimization, and by default, XST removes these registers. However, if you introduced these registers in a specific block to improve the performance of your design, disable the equivalent register removal for the entire block or for particular registers. To disable the EQUIVALENT_REGISTER_REMOVAL constraint globally, disable the Equivalent Register Removal Xilinx Specific Option. To disable this constraint for a particular register, set the EQUIVALENT_REGISTER_REMOVAL constraint to NO in the HDL

code.

Register partition boundaries when using incremental synthesis.

When you use an incremental synthesis flow to divide your design into several partitions, XST cannot perform efficient optimization across partition boundaries, which leads to less-than-optimal results. When using an incremental synthesis flow, register the boundaries for each of the partitions. This minimizes the impact on optimization. For example, if the critical path goes through two partitions, XST must preserve hierarchy and cannot optimize across the partitions. In this case,

use registers to separate these block or to change your design partitions.

Note: For more information on incremental synthesis, see the "Incremental Synthesis Flow" section in the "FPGA Optimization" chapter of the XST User Guide.

Reduce area.

If your target device is nearing capacity, the placer and router may have problems finding efficient routing, and may have problems meeting timing objectives. When the route delay is significantly higher than the logic delay in the Timing Reports, this indicates such a problem. Reducing area may free more routing and logic placement resources to help meet speed requirements. For details, see Area Reduction Strategies.

Note: For more information on Timing Reports, see the Timing Analyzer Help.



Implementation Overview for FPGAs

After synthesis, you run design implementation, which comprises the following steps:

1. Translate, which merges the incoming netlists and constraints into a Xilinx® design file 2. Map, which fits the design into the available resources on the target device 3. Place and Route, which places and routes the design to the timing constraints

4. Programming file generation, which creates a bitstream file that can be downloaded to the device

From the Project Navigator Processes for Source window, you can double-click Implement Design to run the implementation process in one step, or you can double-click Translate, Map, and Place & Route to run each of the implementation processes separately. To generate the programming

file, double-click Generate Programming File.

Default property values are used for the implementation process, unless you modify them. Properties can be set for the Implement Design process or for each of the separate implementation

processes.

Note: In addition to the regular implementation flow described here, you can also run a hierarchical

flow as described in Hierarchical Flows Strategies for FPGAs.

Translate

The Translate process merges all of the input netlists and design constraints and outputs a Xilinx native generic database (NGD) file, which describes the logical design reduced to Xilinx primitives.

See the following table for details.

Translate Process

Command line tool NGDBuild

Input files EDIF, SEDIF, EDN, EDF, NGC, UCF, NCF, URF, NMC, BMM

Output files BLD (report), NGD

Process properties Translate Properties

Tools available after running process Constraints Editor, Floorplanner, PACE

Note Each of these tools modifies the UCF file. When

you rerun Translate with the updated UCF, the NGD file is updated.

Map

The Map process maps the logic defined by an NGD file into FPGA elements, such as CLBs and IOBs. The output design is a native circuit description (NCD) file that physically represents the design mapped to the components in the Xilinx FPGA. See the following table for details.



Map Process

Command line tools MAP

Input files NGD, NMC, NCD, NGM

Note The NCD and NGM files are for guiding.

Output files NCD, PCF, NGM, MRP (report)

Process Properties Map Properties

Tools available after running process Floorplanner, FPGA Editor, Timing Analyzer

Place and Route

The Place and Route process takes a mapped NCD file, places and routes the design, and produces an NCD file that is used as input for bitstream generation. See the following table for

details.

Place and Route Process

Command line tools PAR

Input files NCD, PCF

Note In addition to the NCD file from MAP, PAR also accepts an NCD file for guiding.

Output files NCD, PAR (report), PAD, CSV, TXT, GRF, DLY

Process Properties Place & Route Properties

Tools available after running process Floorplanner, FPGA Editor, Timing Analyzer, XPower

Programming File Generation

The Generate Programming File process produces a bitstream for Xilinx device configuration. After the design is completely routed, you must configure the device so it can execute the desired function. See the following table for details.

Generate Programming File Process

Command line tools BitGen

Input files NCD, PCF, NKY

Output files BGN, BIN, BIT, DRC, ISC, LL, MSD, MSK, NKY, ISC, RBA, RBB, RBD, RBT

Process Properties General Options, Configuration Options, Startup Options, Readback Options, Encryption Options

Tools available after running process iMPACT



Design Performance and Runtime Strategies for FPGAs

The following strategies can help you achieve performance, as well as decrease your overall design

time and implementation runtime.

Reasonable Performance Objectives

Set reasonable performance objectives as follows:

Ensure that your performance objectives match the device.

You must select a device that can achieve the clock speeds needed for your design. For information on how to determine device utilization, see the "Evaluating Design Size and Performance" section in the "Understanding High-Density Design Flow" chapter of the Synthesis

and Verification Design Guide.

Evaluate levels of logic.

If your HDL code produces too many levels of logic, you may not be able to meet your timing objectives. Propagation delays may be minimal, but the routing delays may jeopardize your ability to meet your timing objectives. See the "Evaluating your Design for Coding Style and System Features" section in the "Understanding High-Density Design Flow" chapter of the Synthesis and

Verification Design Guide.

I/O Placement Locking with PACE

Use Pinout and Area Constraints Editor (PACE) to place your inputs and outputs so that the data path is flowing left to right or right to left. This helps the placer and router understand the structure of the data. This reduces the complexity of the placing and routing and may also reduce the amount

of resources used. For information on using PACE, see the PACE Help.

Place and Route Effort Levels

Following are strategies for setting the effort levels for the placer and router. You can control the effort levels using either of the following methods:

Project Navigator: Place & Route Properties Command line: PAR options (For details, see the "PAR Options" section in the "PAR" chapter of the

Development System Reference Guide.)



Standard Effort Level

Start with the default Standard setting for the situations described in the following table.

Project Navigator Property

PAR Command Line Option

When to Use

Place & Route Effort Level (Overall): Standard

-ol std Use this default setting in the following situations:

On the initial design run to assess potential problems in the design. This ensures that runtime is kept to a minimum while you assess your design. For example, place and route your design using the Standard setting, and then run Timing Analyzer or TRACE to assess whether you have a critical path with too many levels of logic. If this is the case, you can modify your HDL to reduce the levels of logic. For details, see the "Evaluating your Design for Coding Style and System Features" section in the "Understanding High-Density Design Flow" chapter of the of the Synthesis and Verification Design Guide.

To discover packing issues that can be fixed using mapping properties. For details on the Project Navigator properties, see Map Properties. For details on the corresponding command line options, see the "Map Options" section of the "MAP" chapter in the Development System Reference Guide.

When your design does not have aggressive timing goals. This results in faster runtime while still achieving timing objectives.

When the design is not stable or is only partially designed.

Place & Route Effort Level (Overall): Standard

and

Deselect Use Timing Constraints

-ol std

and

-x

When a design takes too long to route, you can debug the design using this combination of settings. If the routing succeeds with these settings, it may indicate that the long runtime is due to the Place and Route process trying to achieve your timing objectives.

Different Combinations of the Placer and Router Effort Levels

If your timing objectives are not met after using the default Standard setting, try different combinations of the Placer Effort Level and the Router Effort Level settings to improve performance, as shown in the following table. Performance can be focused on placement

objectives, timing objectives, or both.

Note: Do not use High effort levels unless absolutely necessary. This setting causes longer

runtimes with little or no improvements.





When to Use

Placer Effort Level

Router Effort Level

-pl -rl

Standard Medium

or

High

std med

or

high

Use this combination when critical paths are fully placed, and routing requires Medium or High effort to achieve timing objectives.

Medium Standard med std Use this combination when critical paths are fully placed, but some placement requires Medium effort to be placed properly.

Medium Medium

or

High

med med

or

high

Use this combination when critical paths are fully placed but some placement requires Medium effort to be placed properly, and routing requires Medium or High effort to achieve timing objectives.

High Standard high std Use this combination if the design is highly utilized or if timing constraints are difficult to meet. Having a higher quality placement can dramatically reduce the time needed to route and meet timing, resulting in an overall runtime

reduction.

Using Multi-Pass Place and Route (MPPR) with this combination enables the placer and router to find the best placement without wasting too much runtime. After the best placement is found, you can set the Router Effort Level to High (-rl high) to help meet timing. To maintain the existing placement, set the Place and Route Mode to Route Only or use the par -p option.

High High high high Use this combination when the design has aggressive timing, and placement and routing requires High effort levels to meet timing objectives.

Extra Effort Level

Extra Effort is useful when your design is within three percent of meeting all timing objectives. Extra Effort performs additional optimization but significantly increases runtime and does not guarantee better results. Extra Effort is not recommended as a default setting and is not recommended when

the design is unstable. You can set Extra Effort using either of the following methods:

Project Navigator: Extra Effort Place & Route Property Command line: par -xe option (For details, see the "PAR Options" section in the "PAR" chapter of

the Development System Reference Guide.)



Note: On the command line, you can only set par -xe when also setting -ol high. In Project Navigator, you can only modify the Extra Effort Level if the Place & Route Effort Level (Overall) is set to High. In addition, this property is only available when you set the Property display level to

Advanced.

Timing-Driven Packing and Placement

Use the Perform Timing-Driven Packing and Placement property to limit the number of slices containing unrelated logic in your design. To see the number of slices containing unrelated logic in your design, read the Map Report before you set this property. If you have more than 15 percent of unrelated logic usage, you may need to use a larger device that better fits your design instead.

This property increases Map runtime but may help your design meet timing objectives, which would otherwise not be met during Place and Route. Use this property only after you try the different Place

and Route Effort Levels and still cannot meet timing objectives. You can set this property using either of the following methods:

Project Navigator: Perform Timing-Driven Packing and Placement Map Property Command line: map -timing option (For details, see the "MAP Options" section in the "MAP"

chapter of the Development System Reference Guide.)

Note: For Virtex™, Virtex-E, Spartan™-II, and Spartan-IIE device families, this property is called Perform Timing-Driven Packing, because it drives packing but not placement. This property is only

available when you set the Property display level to Advanced.

Multi-Pass Place and Route

Use the Multi-Pass Place and Route (MPPR) process when your design is stable and you are close to meeting timing objectives. This process allows you to use different "cost tables." Each cost table uses a different placement. One or more of these cost tables may provide a significant improvement

in performance. For details, see Running Multi-Pass Place & Route.

When you make a change to your design, you must run MPPR again to achieve your timing objectives. Do not assume that a cost table used in a previous MPPR run will achieve your timing

objectives after you make changes to the design.

Note: If you are running MPPR from the command line, see the "PAR Reports" section in the "PAR"

chapter of the Development System Reference Guide.

Turns Engine

The Turns Engine allows you to try different place and route strategies at the same time, using a network of computers. See the "Turns Engine (PAR Multi-Tasking Option)" section in the"PAR" chapter of the Development System Reference Guide.

Note: This option is not supported for Windows® operating systems.



Performance-Related Map and Place and Route Properties

Following are the Project Navigator properties and corresponding command line options you can

set to control the performance of the Map and Place and Route processes.

Note: Some of these properties are only available when you set the Property display level to

Advanced.

Performance-Related Map Properties

You can set the following properties using either of the following methods:

Project Navigator: Map Properties Command line: MAP options (For details, see the "MAP Options" section in the "MAP" chapter of

the Development System Reference Guide.)


MAP Command Line Option

When to Use

Perform Timing-Driven Packing and Placement

and

Map Effort Level: High

-timing

and

-ol high

Use this combination to drive the packing and placement operations with user-generated timing constraints. By default, the Map Effort Level is set to Medium when using Perform Timing-Driven Packing and Placement. However, setting the Map Effort Level to High (map -ol high) achieves the best results. With this setting, your Map runtime increases. This combination creates a fully placed but not routed NCD file.

Note When running place and route, you do not need to set the Place and Route Mode to Route Only or use the par -p option. Place and route does not redo placement.

Map to Input Functions

-k {4|5|6|7|8} Use this property to reduce the levels of logic. Use this property sparingly and only after you have attempted to reduce the levels of logic in your HDL source file.

Pack I/O Registers/ Latches into IOBs

-pr {i|o|b} Use this property to reduce setup and clock-to-out timing from pad to register or register to pad.

Performance-Related Place and Route Properties

You can set the following properties using either of the following methods:

Project Navigator: Place & Route Properties Command line: PAR options (For details, see the "PAR Options" section in the "PAR" chapter of the

Development System Reference Guide.)



When to Use



Place & Route Effort Level (Overall)

-ol {std|med|high} Set this property to High when the design timing objectives are aggressive.

Placer Effort Level -pl {std|med|high} Set this property to High when the placement is not optimal.

Router Effort Level -rl {std|med|high} Set this property to High when timing is not achieved but

placement is optimal.

Extra Effort -xe {n|c} Set this property when you are close to meeting timing objectives. Extra Effort is not recommended as a default setting. It is not recommended when you are far from

meeting your timing objectives, because it increases

runtimes.

Note In Project Navigator, you can only modify the Extra

Effort Level if the Place & Route Effort Level (Overall) is set to High. On the command line, you can only set par -xe when also setting -ol high.

Advanced Place and Route Strategies

Following are advanced strategies for placing and routing your design:

Use clock region area groups with time groups as area groups.

Use this strategy on a limited basis when necessary. This strategy is useful in confining the synchronous elements of global clock buffers to specific clock regions to prevent contention in clock regions between global clocks. For details, see the "AREA_GROUP" and "TIMEGRP" sections in the "Constraints" chapter of the Constraints Guide.

Create relationally placed macros (RPMs) to help with packing and placement. For details, see the "RLOC" section in the "Constraints" chapter of the Constraints Guide.

Use manual routing with directed routing constraints in the FPGA Editor to maintain the routing of critical nets. For details, see Manually Routing your Design in the FPGA Editor Help.

Floorplan your critical path to help in placement and in packing. For details, see the Floorplanner

Help.

Use FPGA Editor when necessary, as described in Implementation Strategies using FPGA Editor.

Timing Constraints

Use timing constraints as follows:

Do not overconstrain the design to meet timing objectives.

For example, do not place a 120 megahertz (MHz) constraint on a 100 MHz clock. Overconstraining the design makes it more difficult for the placer and router to achieve timing closure. In some cases,



this produces worse results than using realistic timing objectives. Overconstraining is the most frequent cause of a long place and route runtime.

Use timing constraints in your synthesis tool to get the best possible design implementation. Use global timing constraints instead of individual timing constraints where possible.

TIMEGRP

Use TIMEGRPs to group signals with the same timing requirements. If a FROM-TO constraint is necessary, define the specific TIMEGRP instead of using generic timing groups, such as FFS and

RAMS. This reduces runtime and dramatically reduces memory usage.

OFFSET

Use OFFSET constraints with individual timing groups only for exceptions, for example, when the

input or output signals are clocked by the same clock but have different timing requirements.

PERIOD

Use PERIOD constraints whenever possible. Limit the number of FROM-TO constraints.

FROM-TO

Use FROM-TO to define a multi-cycle path that does not require meeting a single cycle. Group as

many elements together as possible to limit the number of FROM-TO constraints.

TIG

Use TIG constraints when appropriate to reduce the difficulty of meeting all timing constraints

during Place and Route.

Additional Recommendations

Following are additional recommendations to reduce runtime and improve design performance:

Manually place RAMB16 and MULT18X18 design elements to reduce runtime. For details, see the "LOC" section in the "Constraints" chapter of the Constraints Guide.

Limit the use of AREA_GROUP constraints. Too many AREA_GROUP constraints, especially

overlapping ones, cause long runtimes.

Consider using the hierarchical design flows to reduce runtimes when limited changes are made to

the design. For details, see Hierarchical Flows Strategies for FPGAs.

Ensure that your computer has twice the amount of RAM listed as used in the Place & Route (PAR) report, up to the maximum of 4 gigabytes (GB). This reduces the possibility of using disk swap space.

Use the PlanAhead® software to reduce runtime and achieve faster performance.



Configuration Overview

After generating a programming file using the Generate Programming File process, you configure

your device. Configuration comprises the following steps:

Download of the programming file from a host computer to a target board Generation of optional configuration files, which you can use in a configuration device, such as a

PROM, or in other software programs

The following sections describe how to configure your device and how to generate optional

configuration files.

Note: Default property values are used for these processes, unless you modify them.

Configuring a Device

To configure a device correctly, you must know which cable configuration mode you want to use. For FPGAs, you can use Boundary Scan, Slave Serial, or SelectMAP. For CPLDs, you can only use Boundary Scan, also known as JTAG. The most commonly used mode is Boundary Scan. When using this mode, you must connect the cable leads to the following pins: TDO, TDI, TCK, TMS, VCC, and GND. For more information on this type of configuration, see the XAPP501

Application Note and the Data Sheets for the device you are targeting.

You can program FPGAs and CPLDs in-system, directly from a host-computer using a Xilinx®

download cable. To configure a device, do the following:

1. Connect the cable to an appropriate port on the host computer and to the correct pins on the target board.

2. Expand Generate Programming File.

3. Double-click Configure Device.

This opens iMPACT, which includes wizards to guide you through the configuration download process, including specifying your configuration mode and configuring your device.

Note: For details on configuring a device, see Device Configuration in the iMPACT Help.

Generating Optional Configuration Files

Optionally, you can generate configuration files to program a configuration device, such as a PROM, or to use with other software programs. FPGAs and CPLDs each support different

configuration files, and generation of these files differs, as follows:

For FPGAs, do the following:

1. In the Project Navigator Processes for Source window, expand Generate Programming File. 2. Double-click Generate PROM, ACE, or JTAG File.

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For CPLDs, do the following:

1. In the Project Navigator Processes for Source window, expand Implement Design. 2. Expand Optional Implementation Tools.

3. Double-click Generate SVF/XSVF/STAPL File.

Running these processes opens iMPACT, which includes wizards to help you create your configuration files. Each configuration files has a different purpose as described in the following sections.

PROM Files

Xilinx FPGAs are SRAM-based and must be programmed every time power is cycled. The most common method of programming Xilinx FPGAs is by using Xilinx PROMs connected to a chain of FPGAs. You must program these PROMs using PROM files created from the FPGA chain

bitstreams.

PROM files include information on the FPGA chain length and contain bitstreams that are reformatted for use with PROM programmers. Several PROM file formats are available: MCS, EXO, TEK, HEX, UFP, BIN, and ISC. iMPACT can directly program Xilinx PROM devices using MCS, EXO, and ISC file formats. If you are using a third-party programmer, check the documentation that

came with the tool to see if a particular format is required.

When you create a PROM file using iMPACT, you must select one of the following types of PROM files to target:

Xilinx® PROM

iMPACT generates a PROM file you can use to program a Xilinx PROM or chain of PROMs.

For more information, see Xilinx and Platform Flash PROM Settings.

Generic Parallel PROM

iMPACT generates a PROM file that you can use to program parallel PROMs made by third-party

companies. These PROMs are typically byte-wide, directly-accessible memory devices that require addresses for certain pins so that specific locations can be read. iMPACT allows you to generate PROM files for parallel PROMs; it does not support programming of parallel PROMs. For more

information, see Parallel PROM Settings.

Note: For more information on these file types, see PROM Formatter Settings in the iMPACT Help.

For information on using PROM configuration, see the XAPP501 Application Note.

System ACE Files

Xilinx System Advanced Configuration Environment (ACE) files are used with the System ACE™ device family, which features greater capacity and flexibility than Xilinx PROMs. Following are the different System ACE solutions, which allow you to program an FPGA target chain or chains:

System ACE Compact Flash (System ACE CF)




This configuration solution is a chipset, which comprises an ACE controller device and a CompactFlash storage device.

System ACE Soft Controller (System ACE SC)

This configuration solution is a chipset, which comprises a Xilinx PROM, a Xilinx FPGA with the

ACE SC controller design, and an Advanced Micro Devices™, Inc., (AMD™) flash memory device.

Note: For more information on using iMPACT to generate these files, see System ACE CF Settings

and System ACE MPM/SC Settings in the iMPACT Help. For more information on the System ACE CompactFlash or Soft Controller solutions, see the System ACE Solutions Data Sheets.

Boundary Scan or JTAG Files

Boundary scan files, also known as JTAG files, are script files that describe a sequence of boundary scan commands and data. To create these script files, iMPACT records the sequence of boundary scan actions in iMPACT and writes these sequences to the script file. Following are the

different file formats and their uses:

SVF and STAPL files

You can use serial vector format (SVF) files and STAPL files with automated test equipment (ATE)

to test boards before sending the boards to your customers.

XSVF files

You can use the Xilinx serial vector format (XSVF) file for embedded systems in which the FPGA is configured by an on-board microprocessor. For information on designing and programming FPGAs

in embedded systems, see the XAPP058 Application Note.

Note: For information on boundary scan file generation, see Boundary-Scan Files in the iMPACT

Help.

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Configuration Troubleshooting

Following are common configuration issues and suggestions for where to look for more information.

Issue What to Do

Configuration fails. Use the Configuration Problem Solver to determine why configuration failed.

Configuration succeeds, but the device does not appear to be active.

Use the Configuration Problem Solver to determine why the device is not active.

Error message: "Connecting to cable (Parallel Port - LPT1)...Cable connection failed."

See Answer Record 15742.

Error message: 585 This error appears when you are trying to program or initialize a chain, and your cable is not

properly connected. Do the following:

Make sure that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage.

Make sure VCC or GND cable leads are connected to sufficient voltage. If your cable is externally powered, make sure the power supply is connected and operating.

Other configuration issues Search the Answer Browser, or see Contacting Xilinx Technical Support.

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