halim 2012

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Comparative Study of Comparator and Encoder in a

4-bit Flash ADC using 0.18μm CMOS Technology

Ili Shairah Abdul Halim, Siti Lailatul Mohd Hassan, Nurul Dalila binti Mohd Akbar, A’zraa Afhzan Ab. Rahim

Faculty of Electrical EngineeringUniversiti Teknologi MARA

Shah Alam, 40450, Selangor, Malaysia

e-mail: [email protected], [email protected], [email protected], [email protected]

Abstract — This paper describes a comparative study of

comparator and encoder in 4-bit Flash Analog to Digital

Converter (ADC) for Pipeline ADC to obtain a high speed ADC.

In this paper, the conventional comparator is replaced with an

open loop comparator and the non-ROM type encoder is used as

the alternative for the conventional encoder. It is implemented

using 0.18μm CMOS technology. Generally, the Silvaco

Electronic Design Automation (EDA) tools is used for drawing

the schematics, do the simulations and designing the layout of theproposed Flash ADC. The simulation results include 1.8V analog

input range and 24.2662 mW of power dissipation at maximum

sampling frequency of 500MHz with the lowest propagation

delay time of 539.61ps.

Keywords-Flash ADC, XOR Encoder, Open Loop Comparator

I. I NTRODUCTION

Data conversion circuit plays an important role in high-ratedata communications. ADC can be found in almost everymodern mixed-signal integrated circuit. A pipeline ADC isdesigned to offer an attractive combination of high speed, highresolution, low power dissipation and small die size. In pipeline

ADC consists of Sample and Hold Circuit (SHC), the FlashADC, the Multiplying Digital to Analog Converter (MDAC)and Digital Error Correction (DEC). The flash architecture is aconverter topology that allows fast data conversion, mainly dueto its parallel structure. Since the demand on the speed fordigital processing keep increasing which requires higher speedin analog interface blocks, many alternatives in redesigning thecomparator in flash architecture has been done. The Flash ADCin [1] is only using 200 MS/s for its sampling rate. Hence, inthis paper, in order to increase the speed, some modificationson the analog and digital part have to be done. For example, in[2], a high speed differential clocked comparator circuit is usedwhere the comparator consists of a preamplifier and a latchfollowed by a dynamic latch that operates as an output sampler.In this paper, the proposed Flash ADC design used an openloop comparator where it has a very minimal number oftransistor and a XOR encoder to encode the thermometer codeinto binary code.

II. DESIGN OF FLASH ADC

A. Flash ADC

Flash ADC is ideal for applications requiring very large bandwidth; however they typically consume more power thanother ADC architectures. For an n-bit converter as in Fig. 1, the

circuit consists of 2n-1 comparators, a resistive ladder with 2

n

resistors that provides the reference voltages and athermometer to binary code encoder as shown in Fig. 2. Thereference voltage for each comparator is one least significant

bit (LSB) greater than the reference voltage for the comparatorimmediately below it [3].

Figure 1. Block diagram of an N-bit Flash ADC

B.

ComparatorFor a voltage comparator, it will produce output '1' when

the analog input voltage is greater than the reference voltage.On the other hand, when the analog input voltage is less thanthe reference voltage, the comparator will produce output '0'. InFlash ADC, the 2

n-1 comparators contribute the input for the

encoder in the form of thermometer code. Comparator is one ofthe key blocks for high speed operation. When comparatorssample the input signal in parallel, this leads to high powerconsumption and slower speed as the number of bit isincreasing.

1) Conventional Comparator

The conventional comparator as shown in Fig. 3 consists

of three stages which are an input preamplifier, a latch and an

output buffer. The latch circuit is not suitable for a high

resolution. Thus, the preamplifier is needed. The output buffer

is needed to amplify the signal coming from the latch and to

provide enough current for the load [4].

2) Proposed Comparator(Open Loop Comparator)

This comparator is an open loop comparator and consistsof three stages which are input stage, push-pull inverter and

output stage as shown in Fig. 4. The advantage of this circuit

978-1-4673-3033-6/10/$26.00 ©2012 IEEE

2012 International Symposium on Computer Applications and Industrial Electronics (ISCAIE 2012), December 3-4, 2012, KotaKinabalu Malaysia

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is that the circuit consumes minimal number of transistor and

thus the circuit area is small [5].

Figure 2. 4-bit Flash ADC

Figure 3. Conventional comparator

Figure 4. Proposed comparator

C. Digital Encoder

After the comparators produce the thermometer code, a

digital encoder is used to convert the thermometer code into binary code. In this work, there are two types of digital

encoder has been compared, which are XOR encoder and

Wallace Tree encoder. These encoders will be compared based

on their performance in propagation delay time. The best

encoder will be chosen as the proposed encoder when it gives

the smallest propagation delay time.

1) XOR EncoderAs shown in Fig. 7, the logic function for the encoder is

reformulated to reduce wire crossings and delays in layout. In

Fig. 6, gray code is chosen as an intermediate code tominimize the effect of the metastability and bubble errors.

XOR gates can be used to replace the AND/NAND gates due

to the special format of the thermometer code itself. For

example, and are proved as shown below:

(1)

(2)

When is 1, due to the special format of thermometer code,

is 0, which means is always 0. The proof for other

gates is similar. Therefore, the encoder can be implemented

only with XOR gates, which improves the reliability of theencoder. As shown in Fig. 7, extra delay cells are added to

match the delay difference among the signal paths [7].

2) Wallace Tree Encoder

Wallace Tree method can correct higher order bubbles.The Wallace Tree method is originally used to implement high

speed multipliers in computer arithmetic units is the most

efficient. It has been used with the thermometer code in Flash

ADCs where the number of "1's" is counted (instead of the

01 transition being determined. Due to the tree structure, the

number of cells is doubled and one stage is added for every 1

bit resolution increase. The Wallace Tree is consists of a treeof full adders as shown in Fig. 8 [8].

Figure 6. Digital encoder

Figure 7. The encoder implemented in XOR gates


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Figure 8. 4-bit of Wallace Tree encoder

III. SIMULATION R ESULTS AND DISCUSSIONS

The Flash ADC is designed in 0.18μm CMOS technologywith a 1.8 V supply. A bias current of 1mA is used for all gatesin the comparator circuit.

A. Comparator Result

In Fig. 4, a proposed comparator circuit is shown. The

frequency of the analog signal input is varied in the way that

the minimal propagation time delay is obtained. For the

functionality purpose as shown in Fig. 9a, the referencevoltage, Vref is set to 0.9V and the supply voltage is 1.8V. As

illustrated in Fig. 9b, if the input voltage is higher than 0.9V,

the output of comparator is high and vice versa.

a)

b)Figure 9. Output of comparator

Simulation results for the conventional and proposed

comparator at several frequencies are summarized in table I

and II respectively. As shown in both table, power dissipation

of a comparator is increased proportional to the frequency.Generally by increasing the frequency, the delay of the

comparator will be decreased and thus the comparator will

have a higher speed.

By comparing between the conventional and the proposed

comparator, it is proved that the proposed comparator which

has a smaller feature size is chosen as the component in the

Flash ADC because it results a smaller propagation delay time

and thus has a higher speed.

TABLE I. CONVENTIONAL COMPARATOR R ESULTS WITH VARIOUS

FREQUENCY

Frequency Tplh (ns) Tphl (ns) Tavg (ns) Power

200MHz 0.23772 4.8949 2.56631 2.94574 mW

500MHz 0.13279 1.9921 1.06245 2.97749 mW

TABLE II. OPEN LOOP COMPARATOR R ESULTS WITH VARIOUS

FREQUENCY

Power dissipation in a Flash ADC happens only at the time

when the comparators are working, which is called the

sampling period. Nowadays the demand on the low cost and

low noise comparator is very high. Power dissipation is the

wasted power in the form of heat, voltage drop. The results ofthe power dissipation of proposed and conventional

comparator are shown in table III. As stated in Eq. (3), power

dissipation is directly proportional to the bias current value.

Hence, the power will decrease as the current decrease. A

minimal current is needed to drive the Flash ADC, thereforethe bias current should not be too small. It is shown that the

proposed comparator has a smaller power dissipation

compared to the conventional comparator. Hence, in this

paper, the proposed Flash ADC will choose 1mA for the bias

current.

P = Vdd x Idd (3)

TABLE III. POWER DISSIPATION OF CONVENTIONAL AND PROPOSED

COMPARATOR WITH TWO DIFFERENT BIAS CURRENT

Conventional Proposed

Current 1 mA 5 mA 1 mA 5 mA

Power

dissipation

2.97749

mW

10.3251

mW

2.76476

mW

10.1062

mW

B. Encoder Result

As the digital part, the speed of the encoder also plays an

important role in the Flash ADC. In this paper, two types of

encoder have been tested which are, XOR encoder and

Wallace Tree encoder. All the results of the propagation delay

time and the power dissipation have been summarized in tableIV and as the conclusion; the XOR encoder gives the smallest

power dissipation and the lowest propagation delay time (Tp).

Thus, XOR encoder is used as the proposed encoder in order

to contribute a higher speed in Flash ADC circuit.

TABLE IV. COMPARISON BETWEEN 3 TYPES E NCODER

XOR Encoder Wallace Tree

Encoder

Power 1.23248mW 1.47870mW

Tplh 1.694ns 2.492ns

Tphl 49.556 ns 52.166ns

Tavg 25.625ns 27.329ns

C. Comparison With Previous Work

Fig. 10a shows the analog input signal where the input

range is 1.8V. Fig. 10b, Fig. 10c, Fig. 10d and Fig. 10e show

Frequency Tplh (ns) Tphl (ns) Tavg (ns) Power200MHz 0.32272 4.9876 1.32758 2.71906 mW

500MHz 0.21351 0.6669 0.14010 2.76476 mW


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the outputs of the Flash ADC where it starts with the most

significant bit (MSB), bit 3 and followed by the least

significant bit (LSB), bit 0 respectively. Table V shows thesimulation results for 4-bit proposed Flash ADC.

TABLE V. 500 MHZ 4-BIT PROPOSED FLASH ADC

Proposed Flash ADC

Technology 0.18 μm

Power Supply 1.8 VTemperature 27 C

Power Dissipation 24.2662 mW

Tphl 778.59 ps

Tplh 300.63 ps

Tp 539.61 ps

a)

b)

c)

d)

e)

Figure 10. Simulation results for the 4-bit proposed Flash ADC

TABLE VI. COMPARISON WITH PREVIOUS WORK

Previous Work [1] Present Work

Power Supply 3.3 V 1.8V

Technology 0.35 μm 0.18 μm

Resolution 4-bit 4-bit

Speed 200 MS/s 500 MS/s

Power Dissipation 12.4 mW 24.2662 mW

IV. LAYOUT OF THE FLASH ADC

Fig. 11 shows the layout of 4-bit flash ADC using 0.18μm.It includes a resistive ladder with 16 resistors, 15 comparatorsand a thermometer code to binary encoder. On the left side ofthe layout design is the analog part and on the right side is thedigital part. The area of the layout design is 182.575μm x

295.5053μm.

V. CONCLUSION

High speed architecture for a 4-bit Flash ADC is presented

using 0.18μm CMOS Technology. The proposed Flash ADC

can achieve a higher speed compared to the previous work [1].

Author has compared the results between the previous work

and the present work. The comparison of the results is shown

in the table VI. As the conclusion, the proposed method can

increase up until 500MHz of sampling frequency in the proposed Flash ADC in 1.8V power supply. For future

development, 90 nm technology can be apply to this design to

obtained a higher speed with a lower power.

Figure 11. Layout of proposed 4-bit Flash ADC

ACKNOWLEDGMENT

The author would like to acknowledge with gratitude,UiTM Research Management Institute and Faculty ofElectrical Engineering, UiTM for supporting this work underExcellent Fund (Research Intensive Faculty) code 80/2012.

R EFERENCES

[1] Sudakar S. Chauhan, S. Manabala, S.C. Bose, and R. Chandel, "A NewApproach To Design Low Power CMOS Flash A/D Converter", International Journal of VLSI design & Communication Systems(VLSICS), Vol.2, No.2, June 2011, p.100.

[2]

Samad Sheikhaei, Shahriar Mirabbasi, and Andre Ivanov, "A 0.35mCMOS Comparator Circuit For High-Speed ADC Applications" Circuitsand Systems, 2005. ISCAS 2005. IEEE International Symposium on, Vol. 6, p. 6134-6137

[3] Pradeep Kumar, Amit Kolhe, "Design & Implementation of Low Power3-bit Flash ADC in 0.18m CMOS", International Journal of SoftComputing and Engineering (IJSCE), ISSN: 2231-2307, Volume-1,Issue-5, November 2011.

[4] Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design,Oxford University Press, Inc. 2002.

[5] R. J. Baker, H. W. Li and D.E Boyce, CMOS Circuit Design, LayoutAnd Simulation, New York, IEEE Press, 2008.

[6] Meghana Kulkarni, V. Sridhar, G.H.Kulkarni, "The QuantizedDifferential Comparator In Flash Analog To Digital Converter Design", International Journal of Computer Networks & Communications

(IJCNC), Vol.2, No.4, July 2010.[7] Lianhong Wu, Fengyi Huang, Yang Gao, Yan Wang , Jia Cheng, "A 42

mW 2 GS/s 4-bit flash ADC in 0.18-m CMOS", 2009, InternationalConference on Wireless Communication and Signal Processing, WCSP ,2009, p. 1-5.

[8] Paula Pereira, Jorge R. Fernandes, and Manuel M. Silva,"Wallace TreeEncoding In Folding And Interpolation ADCs", IEEE InternationalSymposium on Circuits and Systems, 2002, ISCAS 2002, vol. 1, pp I-509-I-512.


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