genx emu ddr 18 november 2008© vibro-meter confidential and subject to export control as per front...

GEnx EMU DDR 18 November 2008 © Vibro-Meter Confidential and subject to Export Control as per Front Page Section 2.3 CPM Slide 1

EXPORT CONTROLTHE INFORMATION AND TECHNICAL DATA CONTAINED IN THIS DOCUMENT ARE CLASSIFIED UNDER CATEGORY 4E001.A ACCORDING

TO THE SWISS EXPORT CONTROL REGULATIONS. EACH RECIPIENT IS RESPONSIBLE TO ENSURE THAT USAGE AND/OR TRANSFER ORDELIVERY OF THIS INFORMATION COMPLIES WITH ALL RELEVANT EXPORT CONTROL REGULATIONS.

PROPRIETARY INFORMATIONTHE INFORMATION CONTAINED IN THIS DOCUMENT IS THE PROPERTY OF THE VIBRO-METER GROUP OF COMPANIES AND SHALL BE

USED ONLY BY THE RECIPIENTS FOR THE PURPOSE FOR WHICH IT HAS BEEN SUPPLIED AND SHALL NOT BE DISCLOSED TO ANY THIRDPARTY WITHOUT THE WRITTEN CONSENT OF VIBRO-METER


GEnx 1B Engine Monitoring UnitP0x Delta DDR – Section 2.3 Rev 1

Communications Processing Module (CPM)

Updated 19th November 2008

Indication of updated slide following DDR review 11-18-2008


GENx CPM DDR Review – 11/18/2008

IntroductionPDR Mini-Review Action ItemsCPM ArchitectureBoard Views / Photos Reasons for ChangesSummary of ChangesPCB Layout ChangesPCB Material ChangeThermalVibrationPowerWeightEMI Grounding and ProtectionSwitching FrequenciesComponent SelectionManufacturing and TestabilityFPGA ChangesScheduleVerification / Certification strategy


Introduction

The CPM changes identified herein are included with the P0X (increased size cast chassis).

Existing P06 CPM is compliant to specification.

Changes are driven by manufacturing testability, Industry Norm compliance (e.g IPC) and an initiative to improve Reliability.


CPM PDR Mini-Review Action Items

Action Item Required Action Owner Status Meggitt DDR Comments1 SRAM BGA Lead-free Solder Plan Evaluate impact of the lead-free plan relative to

the SRAM BGA. Determine if there may be need of an outside house for BGA pre-tinning.

Meggitt CLOSED This action is addressed in Slide 36

2 CPM Thermal Analysis Need to perform analysis. Include results at P0X Review.


3 FR4 PWB Glass Plies Confirm single/double ply construction. Meggitt CLOSED PCB is Double ply Construction4 FR4 PWB Single Glass Ply If single ply is used, evaluate if extra PWB

dielectric test is needed to screen for void issues.Meggitt CLOSED Not Applicable - Double ply

5 VSM & VMU PWB Glass Plies Provide construction comparison relative to present / proposed P0X designs.

Meggitt CLOSED Data provided via Meggitt CM_436 and presented within DDR Section 2.4, VSM material

6 Stacked Power Rail Capacitors Evaluate transient power-up stress when voltage rails may be offset.


7 Removal of Thermal Planes Provide more detail on premise as being removed due to being unnecessary.


8 CPM Weight Re-evaluate the weight reduction calculations. Meggitt CLOSED This action is addressed in Slide 339 PSM Stability With reduction of ~1 amp, verify the stability

margin of the PSM with the reduced CPM load.Meggitt CLOSED This action is addressed in Slide 32

10 Ground Plane Conduct a separate meeting to discuss the from/to EMU grounding changes for P0X.

Meggitt CLOSED Completed on 8-4-08

11 Ground Plane Include the from/to details at the P0X Review. Meggitt CLOSED Completed on 8-4-0912 Ground Plane Within the CPM, provide explanation of each

board layer (ie circuit traces, grounding, shielding, etc).


13 Obsolescence List Re-review. Speculation that this SRAM will be obsolete within 3 years.

Meggitt CLOSED Similar to action 1 - see slide 36

Open 0 0%Closed 13 100%

Total 13

Action Item 9 status changed to Closed


EMU Internal Architecture

SignalConditioning

Speed Inputs

Vibe ProcessorDigital Signal Processor

(TI TMS320VC33)

Level C OS

Accel Inputs

Strain Gauges

VRT Inputs

Buffers Interface

Dual PortRAM

Dual PortRAM

FLASH

RAM

CPU2 Processor(Freescale MPC5554)

Level E

FIFO

FLASH

RAM

CPU1 Processor(Freescale MPC5554)

Level C/E

Interface

Interface CAN Bus (2) Datalinks

Interface HSESB (2) Datalink

Interface RS232 Ground Datalink

Interface ARINC 429 Ground Datalink

Interface RS232 Debug Datalink

Interface CAN Bus Debug Datalink

Dual PortRAM

FLASH

RAM

AFDX Processor(Freescale MPC5554)

Level C

RS232 Debug DatalinkGSE Test Signals Power Supply 115V 400 Hz ac power

RS232 Debug Datalink

InterfaceARINC 664 AFDX Datalink

InterfaceRS232 Debug Datalink

Engine Position

Descrete I/O

External ConnectionsAircraftEngineGroundDevelopment

SignalConditioning

SPI

RAM

CPMVSM

PSU


CPM Functional Block Diagram

FPGA Control

VSM DSP

CAN SW Test

429 Bus

CPU 1 RS232

DiscretesDual AFDX

Dual Hi Speed RS 485

ARINC 429

HSESB

4/8 MB Burst

FLASH

8 MB Burst SRAM

384 MB Flash

32 MB SRAM

32K x 32 Dual-Port

SRAM

XCVRS

EEPROM 2KB

Engine ID

VSM Temp Sensors

VSM SensorsInput

SPI

3

Temp Sensors

PSM Control & power

FPGA Control

4/8 MB Burst

FLASH

8 MB Burst SRAM

4 IN 4 OUT 32K x 32

Dual-Port SRAM

8 MB Burst SRAM

32K x 32 Dual Port

SRAM

Dual 1K x 32 FIFO

128 MB Flash

Dual AFDX PHY

XCVRS XCVRS

I2C Controller

XC

VR

S

FPGA Control

&Dual AFDX

MAC 10Mbps

Dual CAN

CPU 2 MPC5554 132 MHz

CPU 2 RS232

BDM

CPU 1 MPC5554 132 MHz

BDMBDM

AFDX RS232

AFDX MPC5554 132 MHz

GSE RS232


P0x CPM Board Views


Reasons for Changes

Improve Module manufacturing Testability and test coverage to conform to Vibro-Meter DFM and DFT Unit Reliability and NADCAP/IPC compliance (PCB material and Via Ratio reduction)Correct existing, minor tracking errors 2 mod wires on bottom side of board

Implement EMI mod wires

No functional Changes

No changes affecting Software compatability

No changes affecting CPM performance

No changes to internal switching fequencies


Reasons for Changes – Board Size

Additional real estate is required to add JTAG buffer components and to improve Via ratio

½ inch increase on card depth

Increased EMU chassis size of 1 inch

Additional½ inch


Summary of Changes (1)

Existing board New board Reason

14 SRAM TQFP 7 SRAM BGA119 Power/thermal reduction

Component Placement

14 Standard buffer 14 JTAG Buffer (3 chain) Increased manufacturing test coverage

Short Stiffeners Extended Stiffeners Improved Vibration response

Weight: 494 gr Actual Weight: 420 gr -

Dimension 197.5 mm x 219 Increased dimensions

210 mm x 219 mm (1/2 inch increase)

Additional aea required to add test points, JTAG compatible buffers and improve via ratio

Board thickness 2.8mm Board thickness 2.12mm Reduced weight

Improved via ratio


Summary of Changes (2)

Existing board New board Reasons

Copper layer Copper layer removed Weight and via ratio improvements

FPGA v13 Updated FPGA firmware for new Buffer control logic

Buffer control logic is different between existing & new board

Heater circuits tracks and component placement

Removal of Heater circuit Legacy from P02/P03

Via Ratio 14:1 Via Ratio 10:1 Reliability

PCB material:

FR4 TG170 Epoxy-fiberglassIPC4101A/24 (IS410)

PCB Material:

FR4 TG170 Epoxy-fiberglassIPC4101A/98 (IS420)

Reliability

Implement Ground Plane mods as per Grounding mini-review (Slide 36)

Lessons learnt


PCB Layout Placement Changes

Old versus New comparison on following slides


Old / New CPM – Top View


Old / New CPM – Bottom View


Via ratios

The ratio of the circuit board thickness to the smallest hole diameter is 14 for old board and 10 for new board

Existing board is IPC non-compliant

New board is IPC Class 3 compliant


PCB Stack up

Old and New PCB Stack-Up identified in the attached

Microsoft Word Document


PCB Material Change

Change of PCB material from IS410 to IS420 Both are FR-4 IS420 provides higher resistance to thermal stress High-Tg and temperature-resistant base material with improved expansion

behavior in the z-axis CTE is compatible to BGA material (die) IS420 Technical Datasheet attached

PCB supplier is NADCAP approved

Adobe Acrobat Document


Real Estate capacityEstimated 5% to 10% spare capacityZero Spare capacity on P06 CPM


Schematics

The current and new Schematics have been supplied to GEA seperately and will be re-submitted as part of eVSE for P0x


Stacked Power Rail – Transient Power-up Stress

PDR Mini-review Action item 6

CPM re-designed as per attached Report

Microsoft Word Document


Thermal Analysis


Temperature and Altitude Conditions Table III – M50TF4002-S3

Condition Temperature

High Operating Ambient Temperature – no cooling (Notes 1 and 2) 80ºC

Short Time High Operating Ambient Temperature – no cooling (Notes 1 and 2)

88ºC

Ground Survival High Ambient Temperature (Note 3) 88ºC

High Operating Altitude Ambient Temperature(Note 1)

60ºC at 50,000 ft.

Operating Low Temperature (Note 1) -55ºC

Ground Survival Low Temperature (Note 3) -55ºC

NOTES:1. A film coefficient of 7.2 Btu/(hour-square foot-ºC) applies.2. During operation at this condition, internal component temperatures shall remain below maximum rated operating temperatures.3. A film coefficient of 3.6 Btu/(hour-square foot-ºC) applies.


Environmental and Imposed Stresses Table II – M50TF4002-S3

Profile 1 – 22 Percent Occurrence Max Temp (Ambient) 24.8 ºC






Thermal Analysis

A « worst case » thermal analysis of the new CPM card was outsourced to Mentor Graphics, France.

Report available in French but will be translated

Top 10 components with least thermal margin on following slide


CPM Thermal Analysis –Top 10 Components with Least Thermal Margin

Component IDJunction

Temperature(Tj)

TjmaxSurvivability

Margin @ 80 Deg CSurvivability

Margin @ 88 Deg C

CAN#1 113 150 42 34 SRAM_gs832018t#2 112 125 18 10 MPC5554 BGA #3 112 150 43 35 SRAM_gs832018t#5 111.5 125 18.5 10.5 SRAM_gs832018t#7 111 125 19 11 SRAM_gs832018t#1 111 125 19 11 MPC5554 BGA #1 111 150 44 36 SRAM_gs832018t#4 111 125 19 11 MPC5554 BGA #2 111 150 44 36 PQFP_APA300 #2 110 150 45 37

Thermal Analysis performed at 85 Deg C Ambient

Table updated to show survivability margins at 80 and 88 Deg C


ConclusionsThe Thermal analysis was conducted at 85 Deg C ambient in “worst case” conditions

From the data available there is no issues with thermal margin, either from a survivability or operational standpoint

For the P0x design, the thermal analysis will be validated as follows: Instrument the top 10 least margin components (from Thermal Analysis) whilst running

the following test in a closed chassis environment

• Soak at 80 ºC , until all internal temperatures have stabilized, operate for a minimum 2 hours – verify thermal margin against manufacturers max junction temperatures

Instrumented test will be performed at 80 Deg C


Vibration

FEM Modal Analysis completed on new board with extended stiffeners and reduced PCB thickness


Board Modifications affecting Vibration

Copper Layer removed

Extended Stiffener implementation

Board dimension increased : 210 x 219 [mm]

PCB Thickness reduced : 2.12 [mm]

Total CPM Weight Reduced by : 74g (Weight = 420 [g])


Vibration Analysis

Current Board New BoardExtended StiffenersShort Stiffeners


FEM Modal Analysis

Current design New design

430 Hz 425 HzConclusion

New board is expected to have equivalent vibration behaviour

Extended Stiffeners

Current Board New BoardShort Stiffeners


CPM Power Consumption / Impacts on Existing PSU Design

CPM Power Consumption Old board: 14 SRAM @ 230 mA: 3220mA New board: 7 SRAM @ 310 mA: 2170 mA

------------- 1050 mA reduction

PDR Mini-Review Action Item 9: Power Supply Stability with reduced Load PSM (3.3V to CPM) was designed and tested for range Zero to 3A. By the design topology of switching DC/DC converters, we know that a

converter designed for max 3A, will work for any current up to 3A. We can expect with reduced consumption is reduced output ripple

Second Bullet added to cover PDR Mini-Review action 9 (PSM stability)


Weight

Existing Board Weight : 494 gr

New Board Weight : 420gr

Weight Reduction : 74 gr (2.6oz)


Component Selection (New Components)

New components introduced in this CPM Design JTAG Buffers

• Existing buffers replaced with JTAG equivalent devices (14 off)• These are upscreened parts

SRAM • 7 BGA devices replacing 14 TQFP devices• 7 x 17 ball Bump BGA-14 x 22 mm2 Body-1.27 mm Bump Pitch• Military Temperature range parts• Extract of Data sheet attached



Component Obsolescence Status

P0x Component Obsolescence Status updated on 11/14/2008 – No issues raised

Microsoft Excel Worksheet


Component Obsolescence – BGA SRAMThe (new) BGA SRAM was raised as a specific obsolescence risk by GEA –> PDR Mini review actions 1 & 13

Meggitt Response as follows: See attached letter from manufacturer (GSI) regarding continued production of this part

BGA SRAM pre-tinning: • The BGA cannot be pre-tinned. They can be reballed but this process is not

recommended by Vibro-Meter

All military customers are using this version (SnPb balls)

Obsolescence Mitigation -> We will have 12 months to take a decision: 1. Place a last buy order, 2. Demonstrate reliability of a Pbfree BGA inside a SnPb process3. Reball the component



EMI Grounding and Lightning Protection


EMI Grounding Scheme (CPM)

The Overall EMU Grounding scheme has been subject to an earlier mini-review with GEA (Feb 15, 2008)

The CPM Grounding scheme fits into the overall Grounding scheme and is identified on following slide


EMI Grounding Scheme - CPM

0 Ohms1nf/2kv

CALMARK / WEDGELOCK

0 Ohms1nf/2kv 0 Ohms1nf/2kv0 Ohms1nf/2kv

CALMARK / WEDGELOCK

CPM BOARDGROUND PLANES (0V DIGITAL)

CHASSISGROUND

CHASSISGROUND

0 Ohms1nf/2kv0 Ohms1nf/2kv0 Ohms1nf/2kv0 Ohms1nf/2kv

COUPLE OF CAPACITY & RESISTOR, NUMBER OF COUPLE DEPENDING THE PLACE ALLOWED ON THE BOARD

COUPLE OF CAPACITY & RESISTOR, NUMBER OF COUPLE DEPENDING THE PLACE ALLOWED ON THE BOARD

3x STIFFENER

ON EACHSCREW

ALL GROUND /

SHIELDCONNECTED

TO 0V DIGITAL

BO

AR

D C

ON

NE

CT

OR

S


Lighting protection

1.6KV isolation between Case_gnd and on board components

ESDA19SC6 and SLVU2.8 protection are used


Internal Switching Frequencies - CPM

Frequency: Used For:

25MHz Master oscillator for AFDX & FPGA timing & other time bases

56MHz Master oscillator for CPUs & FPGA timing, local CPU buses

112MHz (132MHz)

2X PLL in CPUs for internal operating rate

40MHz PLL derived from 25MHz in FPGA for HSSB & various timing

300kHz 1.5V & 2.5V switching regulators (on-board CPU)

2.5MHz HSSB external I/F {derived from 40MHz}


Internal Switching Frequencies – CPM cont.

Frequency: Used For:

10MHz AFDX external I/F {PLL derived from 25MHz}

1MHz ARINC 429 controller clock {derived from 40MHz}

100kHz ARINC 429 external I/F {derived from 1MHz}

88-330kHz I2C serial bus for on-board and inter-board peripherals [SW configured at 88kHz]

1MHz SPI serial I/F for inter-board peripheral

1MHz CAN external I/F [SW configured]


BGA Devices

BGA SRAM 7 x 17 Bump BGA-14 x 22 mm2 Body-1.27 mm Bump Pitch

Smaller BGA devices than those already implemented (3 off 5554 Power-PC BGA 416)

SRAM BGA ball size / spacing is larger than the MPC5554

Five CPM boards manufactured and all BGA joints have undergone X-Ray. No issues raised from a manufacturing perspectice

BGA Solder Joint Life Analysis


Solder Joint Life Analysis

Analysis Scope: • Thermal Cycle Fatigue Life Analysis

• Plastic Ball Grid Array (PBGA) With 416 Solder Balls

• 5 Different Temperature Profiles With Percent Occurrences

Analysis Results:

• Published in Meggitt CM GEnx EMU CM-VM-GEAE-020 R1 ‘Solder Joint Thermal Fatigue Analysis for New Temperature Profiles’

• A thermal cycle equilibrium equation was used to obtain the forces, stresses and thermal cycle fatigue life of the solder joints (63/37 sn/pb) for the Type 5554 PBGA. The most critical solder joints were in the corners of the square PBGA because these solder balls are the greatest distance from the neutral axis of the component. The approximate solder joint fatigue life was based upon the airplane flying 3 long flights a day, 6 days a week, 48 weeks a year for a total of 864 flights a year. This resulted in a solder joint fatigue life of about 31.2 years, when each flight was equal to one thermal cycle.


Electrical Components Derating

M50TF4002-S3 Paragraph 3.6.12 Electrical Components Derating In lieu of the requirements of M50TF72, internal components of the EMU shall be

derated using TE000-AB-GTP-010 as a guide, or an alternate procedure subject to Purchaser approval, under the following conditions:

(a) The highest mission profile temperature defined in Table II - [M50TF4002] for the hottest mission mix day, excluding mission profiles with less than 10 percent occurrence.

(b) All input and output interfaces utilized during normal system operation connected with nominal loading and mid-range input signals as applicable.

The existing CPM is shown to be fully compliant via Meggitt ECM GEnx EMU CM-VM-GEAE-262

Derating analysis to be updated for EMU P0XNew CPM components (BGA SRAM and JTAG buffers) will be compliant


Manufacturing Testability

Due to dense population of existing board the DFM/DFT standards for testability were never achievedDetailed DFM/DFT reviews have been held with manufacturing departmentBoard test strategy includes JTAG testing and « Bed of Nails » functional testing (using MTS TM Test Equipment) JTAG test coverage

• Existing Board: Calculated test coverage of 25%• New Board: Calculated test coverage of 75%

Bed of Nails• Additional test points have been added on new board

Test coverage at board level will be > 95% and fully Automated


FPGA Changes

Reasons for FPGA Changes

Change Description

Change Impacts?

DO-254


Reason for FPGA Changes

Implement new buffer control for JTAG devices


FPGA Change Description

Old buffer New Buffer

OEn and DIR pin Direction are managed only with two OEn pins


Impacts?

There are NO impacts on CPM Bootloader or on CPM Operational Software (AFDX/OS/AS)

FPGA firmware change will be configuration controlled via CPM and EMU Hardware part number change controlled via GEA DCID and DPD (PNR 2122M32P08)


DO-254 Certification

A delta DO-254 certification is in progress for the CPM FPGA devices on CPU 1 and CPU 3


P0x CPM Key Milestones & Validation Status

Five Boards Manufactured

Bench Testing Verification Completed at Module level

Production JTAG testing completed

DAT (Thermal) testing in P0x chassis is pending availability of Flex prints and is scheduled Jan 2009


25 Point Matrix

Certification Strategy

New CPM will be certified at Component level as part of GEnx -2B component certification tests (currently scheduled Feb to May 2009)

25 point Component Certification matrix

Microsoft Excel Worksheet

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