gate dielectric scaling for high-performance cmos: from ... · 200 300 400 500 00.20.40.60.8 drain...

Gate Dielectric Scaling for High-Performance CMOS:

from SiO2/PolySi to High-K/Metal-Gate

Robert ChauIntel Fellow

Technology and Manufacturing GroupIntel Corporation

November 06 2003

Robert Chau Intel Corporation Nov 06, 2003

1

Content• Introduction

• SiO2 Scaling

• Review on High-K Problems

• Significant Breakthroughs in High-K/Metal-Gate

• High-K/Metal-gate NMOS & PMOS Transistors with Record-Setting Drive Performance

• Summary


2

Introduction

10

10035

0nm

250

nm

180

nm

130

nm

90 n

m

Thic

knes

s (Å

)

• 1.2nm physical SiO2 in production in our 90nm logic technology node

• 0.8nm physical SiO2 in our research transistors with 15nm physical Lg

• Gate leakage is increasingwith reducing physical SiO2 thickness

• SiO2 running out of atomsfor further scaling

• Will eventually need high-K

Physical SiO2 Thickness


3

SiO2 Scaling

PolySi

Silicon

PolySi

Silicon

SiO2

Silicon substrate

1.2nm SiO 2

Gate

Silicon substrate

1.2nm SiO2

PolySi

• 1.2nm physical SiO2 in production (90nm logic node)• 0.8nm physical SiO2 in research transistors


4

Electrical Characteristics of 0.8nm Physical SiO2 & PolySi Gate

0.0

0.5

1.0

1.5

2.0

-1 -0.5 0 0.5 1Vg

Cap

acita

nce

(µF/

cm²) NMOSPMOS NMOSPMOS

--

0.0

0.5

1.0

1.5

2.0

-1 -0.5 0 0.5 1

Vg (V)

Cap

acita

nce

(µF/

cm²)

NMOSPMOS NMOSPMOS

0.8nm0.8nm

Inversion Capacitance

0.0

0.5

1.0

1.5

2.0

-1 -0.5 0 0.5 1Vg

Cap

acita

nce

(µF/


--

0.0

0.5

1.0

1.5

2.0

-1 -0.5 0 0.5 1

Vg (V)

Cap

acita

nce

(µF/

cm²)

NMOSPMOS NMOSPMOS

0.8nm0.8nm

0.0

0.5

1.0

1.5

2.0

-1 -0.5 0 0.5 1Vg

Cap

acita

nce

(µF/


--

0.0

0.5

1.0

1.5

2.0

-1 -0.5 0 0.5 1

Vg (V)

Cap

acita

nce

(µF/

cm²)

NMOSPMOS NMOSPMOS

0.8nm0.8nm

Inversion Capacitance

1E-6

1E-5

1E-4

1E-3

1E-2

1E-1

1E+0

1E+1

1E+2

1E+3

-1 -0.5 0 0.5 1Vg (Volts)

J g (A

/cm

²)

NMOSNMOSInversion

PMOSInversion

1E-6

1E-5

1E-4

1E-3

1E-2

1E-1

1E+0

1E+1

1E+2

1E+3

-1 -0.5 0 0.5 1Vg (Volts)

J g (A

/cm

²)

NMOSNMOSInversion

PMOSInversion


5

Research Transistor with 15nm Physical Lg and 0.8nm Physical SiO2 and

PolySi Gate

0

100

200

300

400

500

0 0.2 0.4 0.6 0.8

Drain Voltage (V)

Drain

Cur

rent

(µA

/ µm)

Vg = 0.8V

0.7V

0.6V

0.5V

0.4V

0.3V

15nm NMOS

0

100

200

300

400

500

0 0.2 0.4 0.6 0.8

Drain Voltage (V)

Drain

Cur

rent

(µA

/ µm)

Vg = 0.8V

0.7V

0.6V

0.5V

0.4V

0.3V

15nm NMOS

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

0 0.2 0.4 0.6 0.8

Gate Voltage (V)

Dra

in C

urre

nt (A

/µm

)

Vd = 0.8V

Vd = 0.05V

S.S. = 95mV/decadeDIBL = 100mV/VIoff = 180nA/um

15nm NMOS

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

0 0.2 0.4 0.6 0.8

Gate Voltage (V)

Dra

in C

urre

nt (A

/µm

)

Vd = 0.8V

Vd = 0.05V

S.S. = 95mV/decadeDIBL = 100mV/VIoff = 180nA/um

15nm NMOS0.8nm physical SiO20.8nm physical SiO2

• Well-controlled short-channel characteristicsRobert Chau Intel Corporation

Nov 06, 20036

Formation of High-K: Atomic Layer Deposition


7

• Sequential introduction of precursor molecules MCl4(g) and H2O(g); M=Zror M = Hf

Step 3

Step 1

Step 2

MCl4(g)+ HO-(surface) MCl3O(surface) + HCl(g)

Step 4

MCl2O2(surface) + 2H2O(g)MO2(OH)2(surface) + 2HCl(g)Hydroxyl surface formed in preclean

Repeat steps 4-5

MCl3O(surface) + HO-(surface) MCl2O2(surface) + HCl(g)

Step 5

MO2(OH)2(surface) + MCl4(g) MO2MCl2O2(surface) + 2 HCl(g)

Review on High-K Problems(High-K/PolySi-Gate)

• High-K and polySi gate are incompatible due to Fermi level pinning at the high-K and polySi interface which causes high threshold voltages in transistors

• High-K/polySi transistors exhibit severely degraded channel mobility due to the coupling of SO phonon modes in high-K to the inversion channel charge carriers


8

High-K and PolySi are Incompatible

• Defect formation at the polySi-high-K interface

• TCAD simulation shows it takes only 1 defect out of 100 surfaceatoms to “pin” the transistor threshold voltage (high Vth)

OM

O O O OM M M

OM

O O O OM M M

O O O OO O OO

OM

O O O OM M M

OM

O O O OM M MM

OM

O O O OM M M

OM

O O O OM M MM

SiSi Si Si Si Si SiSi SiSiSi Si Si Si Si Si Si Si Si Si

SiSi Si Si Si Si Si Si Si Si Si

SiSi Si Si Si Si Si Si Si Si Si

MSi

Si

Si

Si

SiPoly Si

Interface

High-KM = Zr orM = Hf

Defect


9

Mobility Degradation in High-K/PolySi

High-K / Poly-Si

0

100

200

300

400

500

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6Electric Field (MV/cm)

Inve

rsio

nEl

ectr

on M

obili

ty (c

m2 /V

.s) Universal Mobility

SiO2 / Poly-Si


10


11

Problems of High-K/PolySi Transistors

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

0 0.2 0.4 0.6 0.8 1 1.2Vg (V)

Id (A

/µm

)

Vd = 1.3VLg = 110nm

PolySi/High-KToxe = 17A

PolySi/SiO2Toxe = 20A

[Higher Vth and lower mobility]

Experimental Evidence of Phonon Scattering in High-K/PolySi Gate

1.0E-05

1.5E-05

2.0E-05

2.5E-05

3.0E-05

3.5E-05

4.0E-05

4.5E-05

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5

E-Field (MV/cm)

d(1/

ueff)

/dT High-K/PolySi

SiO2/PolySi

Phonon scattering

E-Field

µ

0

1

>∂

∂

TPHµ

0

1

<∂

∂

TCoulµ

0

1

=∂

∂

TSRµ

µph ↓ T ↑

µCoul ↑ T ↑

µSR~ const

Coulombic Phonon SurfaceRoughness

SRphCouleff µµµµ1111

++=


12

Review on High-K Problems(High-K/Metal-Gate)

• Metal gate electrodes are able to screen the high-K SO phonons from coupling to the inversion channel charge carriers and reduce the mobility degradation problem

• However the use of high-K/metal-gate requires metal gate electrodes with the “correct” work functions on high-K for both PMOS and NMOS transistors for high performance


13

Significant Breakthroughs in High-K/Metal-Gate made by Intel

• N-type metal and P-type metal with the correct work functions on high-K have been engineered and demonstrated for high-performance CMOS

• High-K/metal-gate stack achieves NMOS and PMOS channel mobility close to SiO2’s

• High-K/metal-gate stack shows significantly lower gate leakage than SiO2


14

We have Engineered N-type and P-type Metal Electrodes on High-K with the “Correct” Work

Functions for NMOS and PMOS on Bulk Si

NDK

SDK

-1.1-1.0-0.9-0.8-0.7-0.6-0.5-0.4-0.3-0.2-0.10.00.1

N+p

oly

P+po

ly

P-m

etal

N-m

etal

Met

al A

Met

al B

Met

al C

Met

al D

Met

al E

Met

al F

Met

al G

Met

al H

Met

al I

Met

al J

Gate Electrode Materials

Tran

sist

or F

latb

and

Volta

ge(V

)

P-type Metal on High-K

N-type Metal on High-K

N+ PolySi/SiO2

P+ PolySi/SiO2

Mid-gap Metal on High-K


15

High-K/n-type Metal-Gate Stack Achieves NMOS Channel Mobility Close to SiO2

SiO2/polySi

W fill + poor contacts

W fill + improved contact

Nitridation

Optimization

20Å High-K/polySi

TiN fill + improved contact

10 12 14 16 18 20 22 24 26Inversion Electrical Thickness, Toxe (A)

NM

OS

Mob

ility

(cm

2 /V.s

)

Eeff = 1.0MV/cm

High-K/ n+ type Metal-Gate

SiO2/PolySi


16

High-K/p-type Metal-Gate Stack Achieves PMOS Channel Mobility Close to SiO2

10 15 20 25 30Inversion Electrical Thickness, Toxe (Å)

PMO

S M

obili

ty (c

m2/V

.s)

High-K/p+ Metal-GateSiO2/PolySi

Eeff = 1.0MV/cm


17

High-K Reduces Gate Leakage

SiO2/polySi

High-K/metal-gate

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

0 5 10 15 20 25

Accumulation Electrical Tox [A]

Jox

[A/c

m2 ]


18

High-K/Metal-gate NMOS and PMOS Transistors with Record-Setting

Drive Current (Idsat) Performance

• NMOS and PMOS high-K/metal-gate transistors were made on bulk Si– Physical gate length (Lg) = 80nm– Electrical Oxide Thickness @ inversion (Toxe) = 1.45nm

• Record-setting NMOS Idsat– Idsat = 1.66mA/um, Ioff = 37nA/um at Vcc = 1.3V

• Record-setting PMOS Idsat– Idsat = 0.69mA/um, Ioff = 25nA/um at Vcc = 1.3V


19

High-K/Metal-Gate NMOS with Record-SettingDrive Current Performance

• Electrical Tox at Inversion (Toxe) = 1.45nm• Transistor physical gate length (Lg) = 80nm

00.00020.00040.00060.00080.001

0.00120.00140.00160.0018

0 0.2 0.4 0.6 0.8 1 1.2 1.4Vd (V)

Id (A

/µm

)1.E-101.E-091.E-081.E-071.E-061.E-051.E-041.E-031.E-02

0 0.2 0.4 0.6 0.8 1 1.2 1.4Vg (V)

Id (A

/µm

)

Ion = 1.66mA/umIoff = 37nA/um

Lg = 80nmToxe = 14.5A



20

High-K/Metal-Gate PMOS with Record-SettingDrive Current Performance

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

1E-04

1E-03

-1.3-1.1-0.9-0.7-0.5-0.3-0.1Vg (V)

Id (A

/µm

)

Vd=0.05V

Vd=1.3V

Ion = 693 µA/µmIoff = 25 nA/µm


-7.E-04

-6.E-04

-5.E-04

-4.E-04

-3.E-04

-2.E-04

-1.E-04

0.E+00-1.3-1.1-0.9-0.7-0.5-0.3-0.1

Vds (V)

Id (A

/µm

)


• Electrical Tox at Inversion (Toxe) = 1.45nm• Transistor physical gate length (Lg) = 80nm


21

Summary• We have implemented 1.2nm physical SiO2 in our

90nm logic technology node and products, and have demonstrated 0.8nm physical SiO2

• We have engineered and demonstrated NMOS and PMOS high-K/metal-gate stacks on bulk Si with i) the correct work functions, ii) channel mobility close to SiO2’s and iii) very low gate leakage

• We have fabricated high-K/metal-gate NMOS and PMOS transistors on bulk Si with record-setting drive current performance

• We believe high-K/metal-gate is a key technology option for the 45nm logic technology node, to be in production in 2007


22

gate dielectric scaling for high-performance cmos: from ... · 200 300 400 500 00.20.40.60.8 drain...

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