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Eighth Edition

GATEELECTRONICS & COMMUNICATION

Digital Electronics

Vol 6 of 10

R. K. Kanodia Ashish Murolia

NODIA & COMPANY

GATE Electronics & Communication Vol 6, 8eDigital ElectronicsRK Kanodia & Ashish Murolia

Copyright © By NODIA & COMPANY

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To Our Parents

Preface to the Series

For almost a decade, we have been receiving tremendous responses from GATE aspirants for our earlier books: GATE Multiple Choice Questions, GATE Guide, and the GATE Cloud series. Our first book, GATE Multiple Choice Questions (MCQ), was a compilation of objective questions and solutions for all subjects of GATE Electronics & Communication Engineering in one book. The idea behind the book was that Gate aspirants who had just completed or about to finish their last semester to achieve his or her B.E/B.Tech need only to practice answering questions to crack GATE. The solutions in the book were presented in such a manner that a student needs to know fundamental concepts to understand them. We assumed that students have learned enough of the fundamentals by his or her graduation. The book was a great success, but still there were a large ratio of aspirants who needed more preparatory materials beyond just problems and solutions. This large ratio mainly included average students.

Later, we perceived that many aspirants couldn’t develop a good problem solving approach in their B.E/B.Tech. Some of them lacked the fundamentals of a subject and had difficulty understanding simple solutions. Now, we have an idea to enhance our content and present two separate books for each subject: one for theory, which contains brief theory, problem solving methods, fundamental concepts, and points-to-remember. The second book is about problems, including a vast collection of problems with descriptive and step-by-step solutions that can be understood by an average student. This was the origin of GATE Guide (the theory book) and GATE Cloud (the problem bank) series: two books for each subject. GATE Guide and GATE Cloud were published in three subjects only.

Thereafter we received an immense number of emails from our readers looking for a complete study package for all subjects and a book that combines both GATE Guide and GATE Cloud. This encouraged us to present GATE Study Package (a set of 10 books: one for each subject) for GATE Electronic and Communication Engineering. Each book in this package is adequate for the purpose of qualifying GATE for an average student. Each book contains brief theory, fundamental concepts, problem solving methodology, summary of formulae, and a solved question bank. The question bank has three exercises for each chapter: 1) Theoretical MCQs, 2) Numerical MCQs, and 3) Numerical Type Questions (based on the new GATE pattern). Solutions are presented in a descriptive and step-by-step manner, which are easy to understand for all aspirants.

We believe that each book of GATE Study Package helps a student learn fundamental concepts and develop problem solving skills for a subject, which are key essentials to crack GATE. Although we have put a vigorous effort in preparing this book, some errors may have crept in. We shall appreciate and greatly acknowledge all constructive comments, criticisms, and suggestions from the users of this book. You may write to us at [email protected] and [email protected].

Acknowledgements

We would like to express our sincere thanks to all the co-authors, editors, and reviewers for their efforts in making this project successful. We would also like to thank Team NODIA for providing professional support for this project through all phases of its development. At last, we express our gratitude to God and our Family for providing moral support and motivation.

We wish you good luck ! R. K. KanodiaAshish Murolia

SYLLABUS

GATE Electronics & CommunicationsBoolean algebra, minimization of Boolean functions; logic gates; digital IC families (DTL, TTL, ECL, MOS, CMOS). Combinatorial circuits: arithmetic circuits, code converters, multiplexers, decoders, PROMs and PLAs. Sequential circuits : latches and flip-flops, counters and shift-registers. Sample and hold circuits, ADCs, DACs. Semiconductor memories. Microprocessor(8085): architecture, programming, memory and I/O interfacing.

IES Electronics & Telecommunication

Transistor as a switching element ; Simplification of Boolean functions, Karnaguh map , Boolean algebra, and applications; IC logic families : DTL, ECL, TTL, NMOS, CMOS and PMOS gates and their comparison; Full adder , Half adder; IC Logic gates and their characteristics; Digital comparator; Multiplexer Demultiplexer; Flip flops. J-K, R-S, T and D flip-flops; Combinational logic Circuits; Different types of registers and counters Waveform generators. Semiconductor memories.A/D and D/A converters. ROM an their applications.

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CONTENTS

CHAP 1 NUMBER SYSTEM AND CODES

1.1 INTRODUCTION 1

1.2 ANALOG AND DIGITAL SYSTEMS 11.2.1 Advantages of Digital System 21.2.2 Limitations of Digital System 2

1.3 NUMBER SYSTEMS 21.3.1 Decimal Number System 21.3.2 Binary Number System 31.3.3 Octal Number System 31.3.4 Hexadecimal Number System 4

1.4 NUMBER SYSTEM CONVERSION 51.4.1 Decimal-to-Binary Conversion 51.4.2 Decimal-to-Octal Conversion 61.4.3 Decimal-to-Hexadecimal Conversion 71.4.4 Octal-to-Binary conversion 71.4.5 Binary-to-Octal Conversion 71.4.6 Hexadecimal-to-Binary Conversion 81.4.7 Binary-to-Hexadecimal Conversion 81.4.8 Hexadecimal-to-Octal and Octal-to-Hexadecimal Conversion 8

1.5 BASIC BINARY ARITHMETIC 91.5.1 Binary Addition 91.5.2 Binary Subtraction 91.5.3 Binary Multiplication 91.5.4 Binary Division 9

1.6 COMPLEMENTS OF NUMBERS 10

1.7 NUMBER REPRESENTATION IN BINARY 111.7.1 Sign-Magnitude Representation 111.7.2 1’s Complement Representation 111.7.3 2’s Complement Representation 12

1.8 COMPLEMENT BINARY ARITHMETIC 131.8.1 Addition Using 1’s Complement 131.8.2 Subtraction Using 1’s Complement 131.8.3 Addition Using 2’s Complement 141.8.4 Subtraction using 2’s Complement 15

1.9 HEXADECIMAL ARITHMETIC 151.9.1 Hexadecimal Arithmetic Using 1’s or 2’s Complements 151.9.2 Hexadecimal Subtraction Using 15’s or 16’s Complement 15

1.10 OCTAL ARITHMETIC 161.10.1 Octal Arithmetic using 1’s or 2’s Complements 161.10.2 Octal Subtraction using 7’s or 8’s complement 16

1.11 DECIMAL ARITHMETIC 171.11.1 Decimal Arithmetic Using 1’s or 2’s Complements 171.11.2 Decimal Subtraction Using 9’s and 10’s Complement 17

1.12 BINARY CODES 18

1.13 BINARY CODED DECIMAL (BCD) CODE OR 8421 CODE 201.13.1 BCD-to-Binary Conversion 201.13.2 Binary-to-BCD Conversion 20

1.14 BCD ARITHMETIC 201.14.1 BCD Addition 211.14.2 BCD Subtraction 21

1.15 THE EXCESS-3 CODE 22

1.16 GRAY CODE 231.16.1 Binary-to-Gray Code Conversion 231.16.2 Gray-to-Binary Code Conversion 241.16.3 Applications of Gray Code 24

EXERCISE 1.1 25

EXERCISE 1.2 31

EXERCISE 1.3 33

SOLUTIONS 1.1 41

SOLUTIONS 1.2 53

SOLUTIONS 1.3 58

CHAPTER 2 BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION

2.1 INTRODUCTION 63

2.2 BOOLEAN ALGEBRA 632.2.1 Logic Levels 632.2.2 Truth Table 64

2.3 BASIC BOOLEAN OPERATIONS 642.3.1 Boolean Addition (Logical OR) 642.3.2 Boolean Multiplication (Logical AND) 652.3.3 Logical NOT 65

2.4 THEOREMS OF BOOLEAN ALGEBRA 662.4.1 Complementation Laws 662.4.2 AND Laws 662.4.3 OR Laws 662.4.4 Commutative Laws 672.4.5 Associative Laws 672.4.6 Distributive Law 672.4.7 Redundant Literal Rule 672.4.8 Idempotent Law 672.4.9 Absorption Law 672.4.10 Consensus Theorem 672.4.11 Transposition Theorem 682.4.12 De Morgan’s Theorem 682.4.13 Shannon’s Expansion Theorem 68

2.5 SIMPLIFICATION OF BOOLEAN EXPRESSIONS USING BOOLEAN ALGEBRA 682.5.1 Complement of Boolean Function 69

2.5.2 Principal of Duality 692.5.3 Relation Between Complement and Dual 69

2.6 LOGIC GATES 692.6.1 Logic Levels 702.6.2 Types of Logic Gates 70

2.7 UNIVERSAL GATE 752.7.1 NAND Gate as a Universal Gate 752.7.2 NOR Gate as a Universal Gate 77

2.8 ALTERNATE LOGIC-GATE REPRESENTATIONS 79

2.9 BOOLEAN ANALYSIS OF LOGIC CIRCUITS 802.9.1 Converting Boolean Expressions to Logic Diagram 802.9.2 Converting Logic to Boolean Expressions 81

2.10 CONVERTING LOGIC DIAGRAMS TO NAND / NOR LOGIC 822.10.1 NAND-NAND Logic 822.10.2 NOR-NOR Logic 83

EXERCISE 2.1 84

EXERCISE 2.2 105

EXERCISE 2.3 107

SOLUTIONS 2.1 117

SOLUTIONS 2.2 144

SOLUTIONS 2.3 148

CHAPTER 3 THE K-MAP

3.1 INTRODUCTION 155

3.2 REPRESENTATION FOR BOOLEAN FUNCTIONS 1553.2.1 Sum-of-Products (SOP) 1563.2.2 Product-of-Sum (POS) 156

3.3 STANDARD OR CANONICAL SUM-OF-PRODUCTS (SOP) FORM 1563.3.1 Minterm 1573.3.2 S Notation 1573.3.3 Converting SOP Form to Standard SOP Form 158

3.4 STANDARD OR CANONICAL PRODUCT-OF-SUMS (POS) FORM 1583.4.1 Maxterm 1583.4.2 P Notation 1593.4.3 Converting POS Form to standard POS Form 159

3.5 CONVERTING STANDARD SOP FORM TO STANDARD POS FORM 160

3.6 BOOLEAN EXPRESSIONS AND TRUTH TABLES 161

3.7 CALCULATION OF TOTAL GATE INPUTS USING SOP AND POS 162

3.8 KARNAUGH MAP (K-MAP) 1623.8.1 Structure of K-map 1633.8.2 Another Structure of K-map 1653.8.3 Cell Adjacency 165

3.9 PLOTTING A K-MAP 1663.9.1 Plotting Standard SOP on K-map 1663.9.2 Plotting Standard POS on K-map 1663.9.3 Plotting a Truth Table on K-map 166

3.10 GROUPING OF CELLS FOR SIMPLIFICATION 1663.10.1 Grouping of Two adjacent Cells (Pair) 1663.10.2 Grouping of Four Adjacent Cells (Quad) 1673.10.3 Grouping of Eight Adjacent Cells (Octet) 1683.10.4 Redundant Group 169

3.11 MINIMIZATION OF SOP EXPRESSIONS 169

3.12 MINIMIZATION OF POS EXPRESSIONS 170

3.13 CONVERTING SOP TO POS AND VICE-VERSA 170

3.14 DON’T CARE CONDITIONS 1713.14.1 K-map Simplification With Don’t Care Conditions 1713.14.2 Conversion of Standard SOP to Standard POS with Don’t Care Conditions 171

3.15 K-MAPS FOR MULTI-OUTPUT FUNCTIONS 171

3.16 LIMITATIONS OF K-MAP 172

EXERCISE 3.1 173

EXERCISE 3.2 186

EXERCISE 3.3 188

SOLUTIONS 3.1 192

SOLUTIONS 3.2 223

SOLUTIONS 3.3 228

CHAPTER 4 COMBINATIONAL CIRCUITS


4.2 DESIGN PROCEDURE FOR COMBINATION LOGIC CIRCUITS 231

4.3 ADDERS 2324.3.1 Half-Adder 2324.3.2 Full-Adder 233

4.4 SUBTRACTORS 2354.4.1 Half-Subtractor 2354.4.2 Full-Subtractor 236

4.5 BINARY PARALLEL ADDER 237

4.6 CARRY LOOK-AHEAD ADDER 2384.6.1 Carry Generation 2384.6.2 Carry Propagation 2394.6.3 Look Ahead Expressions 239

4.7 SERIAL ADDER 240

4.8 COMPARATOR 2414.8.1 1-bit Magnitude Comparator 2414.8.2 2-bit Magnitude Comparator 242

4.9 MULTIPLEXER 2444.9.1 2-to-1 Multiplexer 2454.9.2 4-to-1 Multiplexer 2454.9.3 Implementation of Higher Order Multiplexers using Lower Order Multiplexers 2474.9.4 Applications of Multiplexers 247

4.10 DEMULTIPLEXER 2474.10.1 1-to-2 Demultiplexer 2484.10.2 1-to-8 Demultiplexer 249

4.10.3 Applications of Demultiplexers 2504.10.4 Comparison between Multiplexer and Demultiplexer 250

4.11 DECODER 2514.11.1 2-to-4 Line Decoder 2524.11.2 Applications of Decoder 253

4.12 ENCODERS 2534.12.1 Octal-to-Binary Encoder 2534.12.2 Decimal-to-BCD Encoder 254

4.13 PRIORITY ENCODERS 256

4.14 CODE CONVERTERS 257

4.15 PARITY GENERATOR 2594.15.1 Even Parity Generator 2604.15.2 Odd Parity Generator 260

EXERCISE 4.1 262

EXERCISE 4.2 281

EXERCISE 4.3 284

SOLUTIONS 4.1 291

SOLUTIONS 4.2 314

SOLUTIONS 4.3 318

CHAPTER 5 SEQUENTIAL CIRCUITS


5.2 SEQUENTIAL LOGIC CIRCUITS 323

5.3 LATCHES AND FLIP-FLOPS 3245.3.1 General Block Diagram of a Latch or Flip-flop 3245.3.2 Difference between Latches and Flip-flops 325

5.4 S-R LATCH 3255.4.1 S -R Latch using NOR Gates 3255.4.2 S -R Latch using NAND Gates 326

5.5 FLIP-FLOPS 3275.5.1 S-R Flip-Flop 3275.5.2 D-Flip Flop 3285.5.3 J-K Flip-Flop 3295.5.4 T Flip-Flop 331

5.6 TRIGGERING OF FLIP-FLOPS 3325.6.1 Level Triggering 3325.6.2 Edge Triggering 3325.6.3 Edge Triggered S -R Flip Flop 3345.6.4 Edge Triggered D Flip-Flop 3365.6.5 Edge Triggered J -K Flip-Flop 3375.6.6 Edge Triggered T -Flip-Flop 339

5.7 OPERATING CHARACTERISTIC OF FLIP-FLOPS 340

5.8 APPLICATION OF FLIP-FLOPS 342

5.9 REGISTER 3435.9.1 Buffer Register 3435.9.2 Shift Register 344

5.9.3 Applications of Shift Registers 345

5.10 COUNTER 3455.10.1 Asynchronous and Synchronous Counter 3455.10.2 Up-Counter and Down-Counter 3465.10.3 MOD Number or Modulus of a Counter 348

5.11 SHIFT REGISTER COUNTERS 3485.11.1 Ring Counter 3485.11.2 Johnson Counter 349

EXERCISE 5.1 352

EXERCISE 5.2 369

EXERCISE 5.3 372

SOLUTIONS 5.1 383

SOLUTIONS 5.2 402

SOLUTIONS 5.3 407

CHAPTER 6 LOGIC FAMILIES


6.2 CLASSIFICATION OF DIGITAL LOGIC FAMILY 413

6.3 CHARACTERISTIC PARAMETERS OF DIGITAL LOGIC FAMILY 4146.3.1 Speed of Operation 4146.3.2 Power Dissipation 4156.3.3 Voltage Parameters 4156.3.4 Current Parameters 4166.3.5 Noise Immunity or Noise Margin 4166.3.6 Fan-In 4176.3.7 Fan-out 4176.3.8 Operating Temperature 4176.3.9 Speed Power Product 417

6.4 RESISTOR-TRANSISTOR LOGIC (RTL) 4186.4.1 Circuit Operation 4186.4.2 Drawbacks of RTL Family 418

6.5 DIRECT COUPLED TRANSISTOR LOGIC (DCTL) 4196.5.1 Circuit Operation 419

6.6 DIODE TRANSISTOR LOGIC (DTL) 419

6.7 TRANSISTOR-TRANSISTOR LOGIC (TTL) 421

6.8 TTL CIRCUIT OUTPUT CONNECTION 4226.8.1 Totem-pole Output 4226.8.2 Open-collector Output 4236.8.3 Tri-state Output 423

6.9 TTL SUBFAMILIES 424

6.10 EMITTER COUPLED LOGIC (ECL) 4256.10.1 ECL OR/NOR Gate 4266.10.2 ECL Characteristics 4276.10.3 Advantages and Disadvantages of ECL Family 427

6.11 INTEGRATED INJECTION LOGIC (I2L) 4286.11.1 Characteristic of I2L 428

6.11.2 I2L Inverter 4286.11.3 I2L NAND Gate 4286.11.4 I2L NOR Gate 4296.11.5 Advantages of I2L 4296.11.6 Disadvantages of I2L 429

6.12 METAL OXIDE SEMICONDUCTOR (MOS) LOGIC 4306.12.1 NMOS Inverter 4306.12.2 NMOS NAND Gate 4316.12.3 NMOS NOR Gate 4326.12.4 Characteristics of MOS Logic 433

6.13 COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) LOGIC 4336.13.1 CMOS Inverter 4346.13.2 CMOS NAND Gate 4346.13.3 CMOS NOR Gate 4356.13.4 Characteristics of CMOS Logic 4366.13.5 Advantages and Disadvantages of CMOS Logic 437

6.14 COMPARISON OF VARIOUS LOGIC FAMILIES 437

EXERCISE 6.1 439

EXERCISE 6.2 455

EXERCISE 6.3 458

SOLUTIONS 6.1 465

SOLUTIONS 6.2 485

SOLUTIONS 6.3 490

CHAPTER 7 INTERFACING TO ANALOG


7.2 DIGITAL TO ANALOG CONVERTER 4957.2.1 Parameters of DAC 496

7.3 DAC CIRCUITS 4967.3.1 R - R2 Ladder Type DAC 4967.3.2 Weighted Resistor Type DAC 497

7.4 ANALOG-TO-DIGITAL CONVERTER 4977.4.1 Sample-and-hold circuit 4987.4.2 Quantization and Encoding 4997.4.3 Parameters of ADC 499

7.5 ADC CIRCUITS 5007.5.1 Flash Type A/D Converter 5007.5.2 Counting A/D Converter 5017.5.3 Dual Slope Type A/D Converter 5037.5.4 Successive Approximation Type ADC 503

7.6 ASTABLE MULTIVIBRATOR 5047.6.1 Astable Multivibrator Using BJT 5057.6.2 Astable Multivibrator Using 555 Timer 5077.6.3 Astable Multivibrator Using Op-amps 507

7.7 MONOSTABLE MULTIVIBRATOR 5087.7.1 Monostable Multivibrator Using BJT 5087.7.2 Monostable Multivibrator Using 555 Timer 510

7.8 SCHMITT TRIGGER 5117.8.1 Schmitt Trigger Using BJT 5127.8.2 Schmitt Trigger Using 555 Timer 513

EXERCISE 7.1 515

EXERCISE 7.2 532

EXERCISE 7.3 535

SOLUTIONS 7.1 541

SOLUTIONS 7.2 564

SOLUTIONS 7.3 568

CHAPTER 8 MICROPROCESSOR


8.2 MICROCOMPUTER 5718.2.1 Memory 5728.2.2 Input-Output Interfacing 5728.2.3 System Bus 572

8.3 MICROPROCESSOR OPERATION 5728.3.1 FETCH 5738.3.2 EXECUTE 573

8.4 MICROPROCESSOR ARCHITECTURE 5738.4.1 System Bus 5738.4.2 Arithmetic Logic Unit (ALU) 5738.4.3 Registers 5748.4.4 Program Counter (PC) 5748.4.5 Flags 5748.4.6 Timing and Control Unit 574

8.5 PIN DIAGRAM OF 8085 MICROPROCESSOR 5748.5.1 Address and Data Bus 5758.5.2 Control and Status Signals 5758.5.3 Power Supply and Clock Frequency 5768.5.4 Interrupts and Other Operations 5768.5.5 Serial I/O Ports 577

8.6 INSTRUCTION SET 5778.6.1 Data Transfer Instructions 5778.6.2 Arithmetic Instructions 5798.6.3 Branching Instructions 5818.6.4 Logic Instructions 5848.6.5 Control Instructions 587

EXERCISE 8.1 589

EXERCISE 8.2 602

EXERCISE 8.3 605

SOLUTIONS 8.1 609

SOLUTIONS 8.2 621

SOLUTIONS 8.3 625***********

Chap 2

Boolean Algebra and Logic Simplification

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GATE STUDY PACKAGE Electronics & Communication

Sample Chapter of Digital Electronics (Vol-6, GATE Study Package)

2.1 INTRODUCTION

This chapter, concerned with the basic study of Boolean algebra and simplification theory, includes the following topics: • Introduction to Boolean algebra: logic levels, truth table.

• Basic Boolean operations: addition, multiplication, not operation

• Various theorems of Boolean algebra

• Meaning of positive and negative logic

• Various types of logic gates: AND, OR, NOT, NAND, NOR, XOR, XNOR gates.

• Universal logic gates; conversion of logic diagrams to universal logic gates.

• Boolean analysis of logic circuits.

2.2 BOOLEAN ALGEBRA

Boolean algebra is mathematics of logic. It is one of the most basic tools which is used in the analysis and synthesis of logic circuit. In Boolean algebra, often the variables are represented by capital letters such as A, B , C , X , Y , Z . The Boolean value of a variable is either logic 0 or logic 1. These, 0 and 1, are known as Boolean constants.

2.2.1 Logic Levels

Boolean logic variable ‘0’ or ‘1’ is not used to represent actual numbers but it is used to represent the state of voltage variable called logical level. Commonly used representation of logic levels are shown in Table below.

Table 2.1: Representation of Logic Levels for Boolean Variables

Logic 0 Logic 1

False True

Open switch Close switch

CHAPTER 2BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION

Chap 2Boolean Algebra and Logic Simplification

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Networks Electronic Devices Analog ElectronicsDigital Electronics Signals & Systems Control Systems ElectromagneticsCommunication SystemsGeneral Aptitude Engineering Mathematics

10 Subject-wise books by R. K. Kanodia

Logic 0 Logic 1

Low High

No Yes

OFF ON

2.2.2 Truth Table

A truth table represents the relation between all inputs and possible outputs of any logic device or logic circuit in a tabular form. The number of inputs may vary from one to many depending upon the device or complexity of the circuit. Number of output also varies in this way and may be one or more. For different digital circuits, some of the examples of truth table are given below.

Table 2.2: Examples of Truth Tables for 1-input, 2-input and 3-input Circuits

2.3 BASIC BOOLEAN OPERATIONS

Boolean algebra uses only three basic operations, namely1. OR operation

2. AND operation

3. NOT operation

2.3.1 Boolean Addition (Logical OR)

The OR operation in Boolean algebra is similar to addition in ordinary algebra i.e., OR means logical addition operation. The logical OR operation on A and B is denoted by

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Y A B= + , where ‘+’ is the OR operatorThe output Y corresponding to various combinations of inputs, A

and B , is shown in Table 2.3 below.

Table 2.3: Truth Table for OR Operation

Input Output

A B Y A B= +

0 0 0

0 1 1

1 0 1

1 1 1

NOTE :The minimum number of inputs for OR operation is two. The number of outputs is always one, irrespective of the number of inputs.

2.3.2 Boolean Multiplication (Logical AND)

The AND operation in Boolean algebra is similar to multiplication in ordinary algebra i.e, AND performs logical multiplication operation.

Let A and B be two Boolean variables. Then, the logical AND operation on A and B is denoted by

Y A B:= ,where : is the AND operator. The output Y corresponding to various combinations of inputs, A and B , is shown in Table 2.4 below.

Table 2.4: Truth table for AND operation

Input Output

A B Y AB=

0 0 0

0 1 0

1 0 0

1 1 1

NOTE :The minimum number of inputs for AND operation is two. The number of output is always one, irrespective of the number of inputs.

2.3.3 Logical NOT

NOT is the simplest of the three basic operations of Boolean algebra. It is also known as inversion and complement. The NOT operation is indicated by a bar ‘-’ over the variable. If A is a variable, then NOT of A is expressed as A . The truth Table of the NOT operation is shown in Table 2.5.


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Table 2.5: Truth table for NOT operation

Input Output

A Y A=

0 1

1 0

NOTE :Logical NOT is the only Boolean operation which must be performed with only one operand or one input. Note that in some texts, the NOT operation is also presented as Al.

2.4 THEOREMS OF BOOLEAN ALGEBRA

The theorems of Boolean algebra can be used to simplify many complex Boolean expression and also to transform the given expression into a more useful and meaningful equivalent expression. These theorems are discussed as below.

2.4.1 Complementation Laws

The term complement implies to invert, i.e. to change 1’s to 0’s and 0’s to 1’s. The five laws of complementation are as follows:1. The complement of 0 is 1, i.e. 0 1=

2. The complement of 1 is 0, i.e. 1 0=

3. If A 0= , then A 1=

4. If A 1= , then A 0=

5. The double complementation does not change the function, i.e. A A=

2.4.2 AND Laws

The four AND laws are as follows:1. Null Law: A 0 0: =

2. Identity Law: A A1: =

3. A A A: =

4. A A 0: =

2.4.3 OR Laws

The four OR laws are as follows:1. Null Law: 0A A+ =

2. Identity Law: 1A 1+ =

3. A A A+ =

4. A A 1+ =

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2.4.4 Commutative Laws

Commutative law states that the order of the variable in OR and AND operations is not important. The two commutative laws are

A B+ B A= + A B: B A:=

2.4.5 Associative Laws

Associative law states that the grouping of variables in AND or OR expression does not affect the result. There are two associative laws.

A B C+ +_ i A B C= + +_ i

A B C: :_ i A B C: := _ i

2.4.6 Distributive Law

The distributive laws allow factoring or multiplying out of expressions. There are two distributive laws

A B C+_ i AB AC= + A BC+ A B A C= + +_ _i i

2.4.7 Redundant Literal Rule

This law states that ORing of a variable with the AND of the complement of that variable with another variable, is equal to ORing of the two variables, i.e.

A AB+ A B= +Another theorem based on this law is

A A B+_ i AB=

2.4.8 Idempotent Law

Idempotence means the same value. There are two idempotent laws

A A A A: : : :g A= A A A Ag+ + + + A=

2.4.9 Absorption Law

There are two absorption laws

A A B:+ A= A A B: +_ i A=

2.4.10 Consensus Theorem

There are two consensus theorems,

AB AC BC+ + AB AC= + A B A C B C+ + +_ _ _i i i A B A C= + +_ _i i


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2.4.11 Transposition Theorem

There are two transposition theorems, the first is given as

AB AC+ A C A B= + +_ _i i

A B A C:+ +_ _i i A C A B: := +

2.4.12 De Morgan’s Theorem

De Morgan’s theorem gives two of the most powerful laws in Boolean algebra. These theorems are very useful in simplification of Boolean expressions,

A B+ A B= AB A B= +

2.4.13 Shannon’s Expansion Theorem

According to this theorem, any switching expression can be decomposed with respect to a variable A into two parts, one containing A and the other containing A . This concept is useful in decomposing complex system into an interconnection of smaller components.

, , , ....f A B C_ i , , ... , , , ...A f B C A f B C1 0: := +_ _i i

, , , ...f A B C_ i , , , ... , , , ...A f B C A f B C0 1:= + +_ _i i8 8B B

2.5 SIMPLIFICATION OF BOOLEAN EXPRESSIONS USING BOOLEAN ALGEBRA

In Boolean algebra, we have to reduce the Boolean expression into its simplest form such that the hardware cost reduces efficiently. The basic rules, laws and theorems of Boolean algebra discussed in this chapter, are used to simplify Boolean expressions. The following steps are used to simplify a Boolean expression using Boolean algebra,

METHODOLOGY: TO SIMPLIFY A BOOLEAN EXPRESSION USING BOOLEAN ALGEBRA

1. Remove all parentheses and multiply all variables.

2. Look for the identical terms. Only one of those terms be retained and all others skipped. For example,

AB AB AB+ + AB=

3. Look for a variable and its complement in the same term. This term can be removed. For example,

A BB: A 0 0:= = ; ABCC AB 0 0:= =

4. Look for pairs of terms that are identical except for one variable which may be missing in one of the terms. The larger term can be removed. For example,

ABC D ABC+ ABC D ABC ABC1 1:= + = =_ i

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5. Look for pairs of terms which have the same variables, except in one term a variable is complemented and in other term is it not. Such terms can be combined into a single terms. For example,

ABC D ABCD ABC D D ABC ABC

AB C D AB C D AB C D C D AB AB

1

1

:

:

+ = + = =

+ + + = + + + = =

_

_ _ _ _

i

i i i i7 A

6. Apply Boolean theorem and laws discussed earlier for further simplification.

2.5.1 Complement of Boolean Function

The complement of a Boolean function is obtained in the following steps:

METHODOLOGY: TO OBTAIN COMPLEMENT OF BOOLEAN EXPRESSION

1. Change all the ANDs to ORs and all the ORs to ANDs i.e., change all ‘ :’ to ‘+’ and all ‘+’ to ‘ :’

2. Complement each of the individual variables.

3. Change all 0’s to 1’s and 1’s to 0’s.

2.5.2 Principal of Duality

Duality is a very important property of Boolean algebra. The dual of a Boolean expression is obtained by replacing all ‘ :’ operations with ‘+’ operations, all ‘+’ operations with ‘ :’ operations, and complementing all 0’s and 1’s. The variables are not complemented in this process. Dual of a function , , , ...f A B C_ i is given as

, , , ..., , , ,f A B C 0 1d

:+_ i7 A , , , ..., , , ,f A B C 1 0 := +_ i

2.5.3 Relation Between Complement and Dual

For a given Boolean expression , , , ...f A B C_ i the relation between its complement and dual expressions are given as

, , , ....f A B Cc _ i , , , ... , , , ...f A B C f A B Cd= =_ _i i

, , , ...f A B Cd _ i , , , ... , , , ....f A B C f A B Cc= =_ _i i

where subscript ‘c ’ represents the complement and subscript ‘d ’ represents the dual of the given function.

NOTE :The above relation states that the dual can be obtained by complementing all the literals in complement function , , , ....f A B C^ h.

2.6 LOGIC GATES

Logic gates are the fundamental building blocks of digital systems. Logic gates are electronic circuits that perform the most elementary


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Boolean operations. Before understanding the logic gates, we must understand the meaning of positive and negative logic.

2.6.1 Logic Levels

Inputs and outputs of logic gates can occur only in two levels. These two levels are termed HIGH and LOW, or TRUE and FALSE, or ON and OFF, or simply 1 and 0. There are two different ways to assign a signal value to logic level such as positive logic and negative logic.1. Positive Logic: If higher of the two voltage levels represents a logic

‘1’ and the lower of the two levels represents a logic ‘0’, then the logic system is referred to as a positive logic system. Figure 2.1 shows the positive logic system.

Figure 2.1: Positive Logic System

2. Negative Logic: If the higher of the two voltage levels represents a logic ‘0’ and the lower of the two levels represents a logic ‘1’, then the logic system is referred to as a negative logic system. Figure 2.2 shows the representation of negative logic systems.

Figure 2.2: Negative Logic System

3. Mixed Logic: In mixed logic, the assignment of logical values to voltage values is not fixed, and it can be decided by the logic designers. Mixed logic provides a simplified mechanism for the analysis and design of digital circuits. The proper use of mixed logic notation provides logic expressions and logic diagrams that are analogue to each other. Also, a mixed logic diagram provides clear information as to the operation of a circuit.

2.6.2 Types of Logic Gates

Logic gates are electronic circuits with a number of inputs and one output. There are three basic logic gates, namely 1. OR gate,

2. AND gate,

3. NOT gate

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Other logic gates that are derived from these basic gates are1. NAND gate,

2. NOR gate,

3. EXCLUSIVE-OR gate,

4. EXCLUSIVE-NOR gate

AND GateAn AND gate is a logic circuit with two or more inputs and one output that performs ANDing operation. The output of an AND gate is HIGH only when all of its inputs are in the HIGH state. In all other cases, the output is LOW. For a positive logic systems, it means that the output of the AND gate is a logic ‘1’ only when all of its inputs are in logic ‘1’ state. In all other cases, the output is logic ‘0’. The logic symbol and the truth table of a two-input AND gate are shown in Figure 2.3 and Table 2.6 respectively.

Figure 2.3: Logic Symbol of Two-input AND gate

Table 2.6: Truth table of a 2-input AND gate

Input Output

A B Y AB=

0 0 0

0 1 0

1 0 0

1 1 1

OR GateAn OR gate is a logic circuit with two or more inputs and one output that performs ORing operation. The output of an OR gate is LOW only when all of its inputs are LOW. For all other possible input combinations, the output is HIGH. For a positive logic system, the output of an OR gate is a logic ‘0’ only when all of its inputs are at logic ‘0’. For all other possible input combinations, the output is a logic ‘1’. The logic symbol and the truth table of a two-input OR gate are shown in Figure 2.4 and Table 2.7 respectively.

Figure 2.4: Logic Symbol of Two-input OR gate


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Table 2.7: Truth table of a 2-input OR gate

Input Output

A B Y A B= +

0 0 0

0 1 1

1 0 1

1 1 1

NOT GateA NOT gate, also called an inverter is a one-input, one-output logic circuit whose output is always the complement of the input. That is, a LOW input produces a HIGH output, and vice versa. It means that for a positive logic system, a logic ‘0’ at the input produces a logic ‘1’ at the output, while a logic ‘1’ at the input produces a logic ‘0’ output. It is also known as a complementing circuit or an inverting circuit. The logic symbol and the truth table of an inverter are shown in Figure 2.5 and Table 2.8 respectively.

Figure 2.5: Symbol for a NOT gate

Table 2.8: Truth Table of NOT Gate

Input Output

A Y A=

0 1

1 0

NAND GateThe term NAND implies NOT-AND. A NAND gate is equivalent to AND gate followed by a NOT gate. The standard logic symbol for a 2-input NAND gate is shown in Figure 2.6. This symbol is same as AND gate symbol except for a small circle (bubble) on its output. This circle represents the NOT function.

Figure 2.6: Logic symbol of NAND gate

The truth Table 2.9 of a NAND gate is obtained from the truth Table of an AND gate by complementing the output entries. The output of a NAND gate is a logic ‘0’ when all its inputs are a logic ‘1’.

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For all other input combinations, the output is a logic ‘1’. NAND gate operation is logically expressed as

Y A B:=

Table 2.9: Truth Table of a 2-input NAND Gate

Input Output

A B Y AB=

0 0 1

0 1 1

1 0 1

1 1 0

NOR GateThe term NOR implies NOT-OR. A NOR gate is equivalent to OR gate followed by a NOT gate. The standard logic symbol for a 2-input NOR gate is shown in Figure 2.7. This symbol is same as OR gate symbol except for a small circle (bubble) on its output. This circle represents the NOT function.

Figure 2.7: Logic symbol of NOR gate

The truth Table 2.10 of a NOR gate is obtained from the truth Table of an OR gate by complementing the output entries. The output of a NOR gate is a logic ‘1’ when all its inputs are logic ‘0’. For all other input combinations, the output is a logic ‘0’. The output of a two-input NOR gate is logically expressed as

Y A B= +

Table 2.10: Truth table of a 2-input NOR gate

Input Output

A B Y A B= +

0 0 1

0 1 0

1 0 0

1 1 0

Exclusive-OR (XOR) GateThe Exclusive-OR gate, commonly known as EX-OR gate, is a two-input, one-output gate. The logic symbol for the Ex-OR gate is shown in Figure 2.8 and the truth table for a two-input EX-OR operation is given in Table 2.11.


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Figure 2.8: Symbol for 2-input Ex-OR Gate

Table 2.11: Truth Table of a 2-input Ex-OR Gate

Input Output

A B Y A B5=

0 0 0

0 1 1

1 0 1

1 1 0

From the truth table it can be stated that, the output of an EX-OR gate is a logic ‘1’ when the two inputs are at different logic and a logic ‘0’ when the two inputs are at the same logic.

NOTE :1. The exclusive-OR and equivalence gates both can be extended to more than

two inputs. However, multiple-input exclusive OR gates are uncommon from the hardware standpoint.

2. For a multiple output-input EX-OR logic function we can conclude that the output of a multiple-input EX-OR logic function is a logic ‘1’ only when an odd number of input variables are ‘1’.

Exclusive-NOR (XNOR) GateThe exclusive-NOR gate, commonly known as Ex-NOR, is an Ex-OR gate, followed by an inverter. It has two inputs and one output. The logic symbol for the Ex-NOR gate is shown in Figure 2.9, and the truth table for the two-input Ex-NOR operation is given in Table 2.12.

Figure 2.9: Symbol for 2-input Ex-NOR Gate

Table 2.12: Truth Table of a 2-input Ex-NOR Gate

Input Output

A B Y A B9=

0 0 1

0 1 0

1 0 0

1 1 1

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The Boolean expression for the Ex-NOR gate is Y A B5= . Using DeMorgan’s theorem,

A B5 AB AB AB AB:= + = ( )( )A B A B AB A B= + + = +

The output of a two-input EX-NOR gate is a logic ‘1’ when the inputs are same and a logic ‘0’ when they are different.

NOTE :1. Likewise Ex-OR gates, three or more variable Ex-NOR gates also do not exist.

Normally, multiple-input EX-NOR logic functions can be implemented using more than one 2-input Ex-NOR gates.

2. For a multiple output-input EX-NOR logic function we can conclude that the output of a multiple-input EX-NOR logic function is a logic ‘1’ only when an even number of input variables are ‘0’. Note if all inputs are 0, then also output will be ‘1’.

2.7 UNIVERSAL GATE

NAND and NOR gates are known as universal gates because any of these two gates is capable of implementing all other gate functions.

2.7.1 NAND Gate as a Universal Gate

The NAND gate can be used to implement the NOT function, AND function, the OR function and other functions also as explained below.

The NOT Gate using NAND GateAn inverter can be made from a NAND gate by connecting all of the inputs together and creating, in effect, a single common input, as shown in Figure 2.10, for a two-input NAND gate. Algebraically, we may write

Y A B:= A A A:= =

Figure 2.10: NOT gate using NAND gate

The AND Gate Using NAND GateTo construct an AND gate from NAND gates, an inverter or a NOT gate is required to invert the output of a NAND gate. This inversion cancels out the first inverted operation of NAND gate and the final result will be AND function as depicted in Figure 2.11. Algebraically,

Y AB AB= =

Figure 2.11: AND Gate using NAND Gate


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The OR Gate using NAND GateTo construct OR function using only NAND gates, first we transform the OR function as follows.

Y A B= + A B= + A A=

A B:= (De Morgan’s Theorem)The above equation is implemented using only NAND gates as

shown in the Figure 2.12.

Figure 2.12: OR Gate using NAND Gate

The NOR Gate Using NAND GateWe know that Boolean expression for NOR gate is

Y A B= + A B:= (De Morgan’s Theorem)

A B:= A A=The above equation is implemented using only NAND gates, as


Figure 2.13: NOR Gate Using NAND Gate

The Ex-OR Gate using NAND GateThe Boolean expression for Ex-OR gate is given by

Y AB AB= +

AB AB= + X X=

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AB AB:= _ _i i (De Morgan Theorem)So, five NAND gates are required to implement the Ex-OR gate

as shown in Figure 2.14.

Figure 2.14: Ex-OR Gate using NAND Gate

Ex-NOR Gate Using NAND GateEx-NOR gate can be constructed by taking complement of Ex-OR. That is, we need one more NAND gate to implement the Ex-NOR function. Figure 2.15 shows Ex-NOR implementation using five NAND gates.

Figure 2.15: Ex-NOR Gate Using NAND Gate

2.7.2 NOR Gate as a Universal Gate

Just like the NAND gate, the NOR gate also may be used to implement all other operations of Boolean algebra. These are explained in following texts.

NOT Gate Using NOR GateIn the same way as the NAND gate described above, an inverter can be made from a NOR gate by connecting all of the inputs together and creating, in effect, a single common input, as shown in Figure 2.16. Algebraically,

Y A B= + A A A= + =

Figure 2.16: NOT Gate Using NOR Gate


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OR Gate Using NOR GateAn OR gate can be created by simply inverting the output of a NOR gate as shown in Figure 2.17. Algebraically,

Y A B A B= + = +

Figure 2.17: AND Gate Using NOR Gate

AND Gate using NOR GateAND function can be generated using three NOR gates. We know that Boolean expression for AND gate is

Y A B:=

A B:= A A=

A B= + (DeMorgan’s Theorem)The above equation is implemented using only NOR gates as


NAND Gate using NOR GateThe Boolean expression for NAND gate is

Y A B:=

A B= + (DeMorgan’s Theorem)

A B= + A A=The above equation is implemented using only NOR gates, as


Figure 2.18: AND Gate Using NOR Gate

Figure 2.19: NAND gate using NOR gate

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The Ex-OR Gate using NOR GateXOR function may also be implemented by using NOR gates. The Ex-OR operation is given by,

Y AB BA= +

AA AB BA BB= + + + 0AA BB= =_ i

A A B B A B= + + +_ _i i A A B B A B= + + +_ _i i

A A B B A B= + + + + +_ _i i

A A B B A B= + + + + +_ _i i X X=_ i

The above expression can be realized using five NOR gates as shown in Figure 2.20.

Figure 2.20: Ex-OR Gate Using NOR Gate

The Ex-NOR Gate using NOR GateTo implement Ex-NOR gate using NOR gates, we just remove the last NOR gates from the circuit of Ex-OR gates shown in Figure 2.21.

Figure 2.21: Ex-NOR Gate using NOR Gate

2.8 ALTERNATE LOGIC-GATE REPRESENTATIONS

We have discussed the five basic logic gates (AND, OR, INVERTER, NAND, and NOR) and the standard symbols used to represent them in a logic circuit diagram. Most of the logic networks use standard symbols. But in some networks an alternative set of symbols is used in addition to the standard symbols. Table 2.13 shows the alternate set of symbols for the five basic gates.


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Table 2.13: Alternate Logic Gate Representations

Logic Normal Symbol Alternate symbol

NOT

AND

OR

NAND

NOR

To convert any normal symbol to its corresponding alternate symbol, the following steps are used:

METHODOLOGY: TO CONVERT STANDARD SYMBOL TO ALTERNATE SYMBOL

Step 1: Add bubbles (indication of inversion) at those input or output points where it is not present.

Step 2: Remove all pre-existing bubbles of the normal symbol, if there is any at the point (only NOT, NAND and NOR gates)

Step 3: If the existing normal logic symbol is AND, change it to OR, Similarly, if it is OR, then change it to AND. There is no change for the triangular symbol of NOT gate.

2.9 BOOLEAN ANALYSIS OF LOGIC CIRCUITS

A Boolean function may be transformed from an algebraic expression into a logic diagram using AND, OR and NOT gates. This is also referred to as AOI logic. Conversely, a logic circuit can be transformed into Boolean expressions for the analysis.

2.9.1 Converting Boolean Expressions to Logic Diagram

The simplest way to convert a Boolean expression to a logic circuit is to start with the output and work towards the input. Assume that the expression Y AB AC ABC= + + is to be realized using AOI logic. Start with the final expression AB AC ABC+ + , we go through following steps:

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METHODOLOGY: TO CONVERT BOOLEAN EXPRESSION TO LOGIC DIAGRAM

Step 1: The expression Y AB AC ABC= + + contains three terms (AB , AC , ABC ) which are ORed together. So, draw an OR gate with three inputs as shown below.

Step 2: AB must be the output of an AND gate whose inputs are A and B and AC must be output of an AND gate whose inputs are A and C . Similarly, ABC must be output of a 3-input AND gate with inputs A , B and C . We introduce these three AND gates as shown below.

Step 3: Now, C must be the output of an inverter whose input is C and similarly, A will be the output of an inverter whose input is A. So we put two inverters as shown below.

This is the complete logic diagram of given function

2.9.2 Converting Logic to Boolean Expressions

Any logic circuit, no matter how complex it is, can be described using Boolean expressions. To derive the Boolean expression for a given logic circuit, start from the left-most input and work toward the final output, writing output for each gate. As an example, consider the logic


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diagram shown in Figure 2.22. We go through the following steps to get the Boolean expression.

Figure 2.22: Logic diagram for which Boolean expression to be determined

METHODOLOGY: TO CONVERT LOGIC DIAGRAM TO BOOLEAN EXPRESSION

Step 1: In the logic diagram shown in Figure 2.22, the output of left-most OR gate with inputs A and B is A B+_ i.

Step 2: The output of left-most AND gate with inputs C and D is CD .

Step 3: The outputs of the OR gate and AND gate are the inputs of right-most AND gate. Therefore, the expression for this AND gate is A B CD:+_ i , which is the final output expression for the entire circuit.

2.10 CONVERTING LOGIC DIAGRAMS TO NAND / NOR LOGIC

Since, NAND logic and NOR logic are universal logic system, digital circuits which are first computed and converted to AOI logic may then be converted to either NAND logic or NOR logic depending on the choice.

2.10.1 NAND-NAND Logic

A logic network can be converted into NAND-NAND gate network by going through following steps:

METHODOLOGY: TO OBTAIN NAND-NAND GATE NETWORK

Step 1: First draw the circuit in AOI logic i.e., using AND, OR and NOT gates.

Step 2: Add a circle (bubble) at the output of each AND gate and at the inputs to all the OR gates.

Step 3: Add an inverter on each line that received only one circle in steps 2, so that the polarity of signals on those lines remains unchanged from that of the original diagram.

Step 4: Replace bubbled OR by NAND and each inverter by its NAND equivalent.

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2.10.2 NOR-NOR Logic

The procedure of converting an AOI logic to NOR-NOR logic is same as above except steps 2 and 4.

METHODOLOGY: TO OBTAIN NOR-NOR GATE NETWORK

Step 1: First draw the circuit in AOI logic i.e., using AND, OR and NOT gates.

Step 2: Add a circle (bubble) at the output of each OR gate and at the inputs to all the AND gates.

Step 3: Add an inverter on each line that received only one circle in steps 2, so that the polarity of signals on those lines remains unchanged from that of the original diagram.

Step 4: Replace bubbled AND by NOR and each inverter by its NOR equivalent.

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EXERCISE 2.1

MCQ 2.1.1 In the following circuit the output Z is

(A) ( )( )( )A B C D E F+ + +

(B) AB CD EF+ +

(C) ( )( )( )A B C D E F+ + +

(D) AB CD EF+ +

MCQ 2.1.2 In the following circuit, the output X is

(A) MNQ (B) ( )N Q M+

(C) ( )M Q N+ (D) ( )Q M N+

MCQ 2.1.3 In the following circuit, the output Z is

(A) ( )AB C D E+ + (B) ( )AB C D E+

(C) AB CD E+ + (D) AB CDE+

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MCQ 2.1.4 The Boolean expression ( )( )( )X Y X Y X Y+ + + is equivalent to(A) XY (B) XY

(C) XY (D) XY

MCQ 2.1.5 In the following circuit, the output Z is

(A) A B C+ + (B) ABC

(C) AB BC AC+ + (D) Above all

MCQ 2.1.6 Given that AB AC BC AB AC+ + = + , then ( )( )( )A C B C A B+ + + is equivalent to(A) ( )( )A B A C+ + (B) ( )( )A B A C+ +

(C) ( )( )A B A C+ + (D) ( )( )A B A C+ +

MCQ 2.1.7 In the following circuit the output X is

(A) AB (B) AB

(C) AB (D) 0

MCQ 2.1.8 In the following circuit the output Y is

(A) AB AB C+ + (B) AB AB C+ +

(C) AB AB C+ + (D) AB AB C+ +


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(A) ABC (B) ABC

(C) ABC (D) 0


(A) ABC (B) ( )AB C B+

(C) ABC (D) ( )AB C B+


(A) ABC (B) ABC

(C) 0 (D) ABC

MCQ 2.1.12 The truth table of a circuit is shown below.

A B C X

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

The expression for X is(A) AB BC AC BC+ + + (B) BC ABC+

(C) BC (D) ABC

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MCQ 2.1.13 A BC+ is equivalent to(A) ( )( )A B A C+ + (B) A B+

(C) A C+ (D) ( )( )A B A C+ +

MCQ 2.1.14 The truth table of a circuit is shown below.

A B C Z

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

The Boolean expression for Z is

(A) ( )( )A B B C+ + (B) ( )( )A B B C+ +

(C) ( )( )A B B C+ + (D) Above all

MCQ 2.1.15 The Boolean expression for the truth table shown is

A B C f

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 0

(A) ( )( )B A C A C+ + (B) ( )( )B A C A C+ +

(C) ( )( )B A C A C+ + (D) ( )( )B A C A C+ +

MCQ 2.1.16 The Boolean expression AC BC+ is equivalent to(A) AC BC AC+ +

(B) BC AC BC ACB+ + +

(C) AC BC BC ABC+ + +

(D) ABC ABC ABC ABC+ + +


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MCQ 2.1.17 Expression A AB ABC ABCD ABC DE+ + + + would be simplified to(A) A AB CD E+ + +

(B) A B CDE+ +

(C) A BC CD DE+ + +

(D) A B C D E+ + + +

MCQ 2.1.18 The simplified form of a logic function ( ( ))Y A B C AB AC= + + is(A) AB (B) AB

(C) AB (D) AB

MCQ 2.1.19 The reduced form of the Boolean expression of ( ) ( )Y AB AB:= is(A) A B+

(B) A B+

(C) AB AB+

(D) AB AB+

MCQ 2.1.20 If XY XY Z+ = then XZ XZ+ is equal to(A) Y (B) Y

(C) 0 (D) 1

MCQ 2.1.21 If XY 0= then X Y5 is equal to(A) X Y+ (B) X Y+

(C) XY (D) XY

MCQ 2.1.22 If A 0= in logic expression Z [ ] [ ]A EF BC D A DE BC DE= + + + + + +, then(A) Z 0= (B) Z 1=

(C) Z BC= (D) Z BC=

MCQ 2.1.23 From a four-input OR gate the number of input condition, that will produce HIGH output are(A) 1 (B) 3

(C) 15 (D) 0

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MCQ 2.1.24 In the following circuit, for which of the following input combination output will be 1 ?

(A) ,A B0 0= =

(B) ,A B1 0= =

(C) ,A B0 1= =

(D) Either A 1= or B 1=

MCQ 2.1.25 A logic circuit control the passage of a signal according to the following requirements:1. Output X will equal A when control input B and C are the same.

2. X will remain HIGH when B and C are different.

The logic circuit would be

MCQ 2.1.26 The output of logic circuit is HIGH whenever A and B are both HIGH as long as C and D are either both LOW or both HIGH. The logic circuit is


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MCQ 2.1.27 Consider the statements below.1. If the output waveform from an OR gate is the same as the

waveform at one of its inputs, the other input is being held permanently LOW.

2. If the output waveform from an OR gate is always HIGH, one of its input is being held permanently HIGH.

The statement, which is always true, is(A) Both 1 and 2

(B) Only 1

(C) 2

(D) None of the above

Common Data For Q. 28 and 29 :A Boolean function Z ABC= is to be implemented using NAND and NOR gate. Each gate has unit cost. Only ,A B , and C are available.

MCQ 2.1.28 If both gates are available then minimum cost is(A) 2 units (B) 3 units

(C) 4 units (D) 6 units

MCQ 2.1.29 If only NAND gates are available, then minimum cost is(A) 2 units (B) 3 units

(C) 4 units (D) 6 units

MCQ 2.1.30 In the circuit shown below the LED emits light when

(A) both switches are closed

(B) both switches are open

(C) only one switch is closed

(D) LED does not emit light irrespective of the switch positions

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MCQ 2.1.31 If the input to the digital circuit shown below consisting of a cascade of 20 XOR gates is X , then the output Y is equal to

(A) X (B) X

(C) 0 (D) 1

MCQ 2.1.32 In the network shown below F can be written as

(A) ... ...X X X X X X X X X Xn n n0 1 3 5 2 4 5 1 1+ +- -

(B) ... ...X X X X X X X X X Xn n n0 1 3 5 2 3 4 1+ + -

(C) ... ... ...X X X X X X X X X X Xn n n n0 1 3 5 2 3 5 1+ + + -

(D) ... ... ...X X X X X X X X X X X Xn n n n n0 1 3 5 1 2 3 5 1 2+ + + +- - -

MCQ 2.1.33 The gate G1 and G2 in figure shown below have propagation delays of 10 ns and 20 ns respectively.

If the input Vi makes an abrupt change from logic 0 to 1 at t t0= then the output waveform Vo is

[t t 101 0= + ns, t t 102 1= + ns, t t 103 2= + ns]


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MCQ 2.1.34 Which of the following Boolean expressions correctly represents the relation between , ,P Q R and M1

(A) ( )XM P Q ROR OR1 = (B) ( )XM P Q RAND OR1 =

(C) ( )XM P Q RNOR OR1 = (D) ( )X XM P Q ROR OR1 =

MCQ 2.1.35 If the X and Y logic inputs are available and their complements X and Y are not available, the minimum number of two-input NAND required to implement X Y5 is(A) 4 (B) 5

(C) 6 (D) 7

MCQ 2.1.36 In the negative logic system,(A) The more negative of the two logic levels represents a logic ‘1’

state

(B) The more negative of the two logic levels represents a logic ‘0’ state

(C) All input and output voltage levels are negative

(D) The output is always complement of the intended logic function

MCQ 2.1.37 Positive logic in a logic circuit is one in which(A) logic 0 and 1 are represented by 0 and positive voltage respectively

(B) logic 0 and 1 are represented by negative and positive voltages respectively

(C) logic 0 voltage level is higher than logic 1 voltage level

(D) logic 0 voltage level is lower than logic 1 voltage level

MCQ 2.1.38 How is inversion achieved using Ex-OR gate ?(A) Giving input signal to the two input lines of the gate tied together

(B) Giving input to one input line and logic zero to the other line

(C) Giving input to one input line and logic one to the other line

(D) Inversion cannot be achieved using Ex-OR gate

IES EE 1992

IES EC 2002

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MCQ 2.1.39 Match List-I with List-II and select the correct answer using the codes given below the lists.

List - I List - II

a. A B 05 = 1. A B=Y

b. A B 0+ = 2. A B=

c. A B 0: = 3. orA B1 1= =

d. A B 15 = 4. orA B1 0= =

Codes : a b c d(A) 3 2 1 4(B) 2 3 4 1(C) 3 2 4 1(D) 2 3 1 4

MCQ 2.1.40 Consider the following statements:(1) A NAND gate is equivalent to an OR gate with its inputs inverted.

(2) A NOR gate is equivalent to an AND gate with its inputs inverted.

(3) A NAND gate is equivalent to an OR gate with its output inverted.

(4) A NOR gate is equivalent to an AND gate with its output inverted.

Which of these statements are correct?(A) 1 and 2 (B) 2 and 3

(C) 3 and 4 (D) 1 and 4

MCQ 2.1.41 The output (X ) waveform for the combination circuit shown below for the inputs at A and B (waveform shown in the figure) will be

IES EE 1999


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MCQ 2.1.42 Which of the following represents the correct waveform for X in the given circuit diagram.

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MCQ 2.1.43 A logic circuit and input waveform to it shown below.

The output waveform is represented by

MCQ 2.1.44 In a natural food restaurant, fruit is offered for desert but only in certain combination. One choice is either orange or apple or both. Another choice is either mango and apple or neither. A third choice is orange, but if you choose orange, then you must also take banana. If the fruits are represented by their first alphabet of the name, then the logical expression that specifies the fruit available for desert in the simplified form is(A) A B+ (B) M O+

(C) A O+ (D) M B+

MCQ 2.1.45 The open collector wired circuit shown below functions as

(A) Ex-NOR (B) AND

(C) Ex-OR (D) NOR


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MCQ 2.1.46 The simplified form of the expression ( )( )( )w x w x yz w y+ + + +l l l is(A) w xy wx w yz+ +l l l l (B) w xy wx+l l

(C) xy wx wyz+ +l l (D) xy wx w yz+ +l l

MCQ 2.1.47 The elevator door should open if the elevator is stopped, it is level with the floor, and the timer has not expired, or if the elevator is stopped, it is level with the floor, and a button is pressed. IfD " Elevator door opens ; S " Elevator is stopped ;F " Level with floor ; T " Timer expired ; B " Button pressedWhich of the following Boolean expression represents the above condition ?(A) D SFT SFB= +l (B) D SFT B= l

(C) D SF T B= + l (D) ( )D S F T B= + l

MCQ 2.1.48 The logic circuit shown in the given figure can be minimized to


(A) ( )AD B C A D+ + (B) ( )AD B C A D5 +

(C) ( )AD B C A D5 + (D) ( )A D B C AD5 +

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MCQ 2.1.50 What does the expression AD ABCD ACD AB ACD AB+ + + + + on minimization result into ?(A) A D+

(B) AD A+

(C) AD

(D) A D+

MCQ 2.1.51 Which one of the following logical operations is performed by the digital circuit shown below ?

(A) NOR (B) NAND

(C) Ex-OR (D) OR

MCQ 2.1.52 The switching circuit given in the figure an be expressed in binary logic notation as

(A) ( )( )L A B C D E= + +

(B) L AB CD E= + +

(C) ( )( )L E A B C D= + + +

(D) ( )L AB CD E= +

MCQ 2.1.53 Which of the following statements is not correct ?(A) X XY X+ =

(B) ( )X X Y XY+ =

(C) X XY X+ =

(D) ZX ZXY ZX ZY+ = +

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MCQ 2.1.54 Consider the given circuit diagram of switching of light from two different switches.

The input conditions needed to turn on LED is(A) A B 1= = (B) A B 0= =

(C) ;A B1 0= = (D) Both (A) and (B)

MCQ 2.1.55 Which one of the following is the dual-form of the Boolean identity given below ? ( )( )AB AC A C A B+ = + +

(A) AB AC AC AB+ = +

(B) ( ) ( ) ( )( )A B A C A C A B+ + + = + +

(C) ( )( )A B A C AC AB+ + = +

(D) AB AC AB AC BC+ = + +

MCQ 2.1.56 What is dual of [ ( )]A B AC D+ + + ?(A) [ ( )]A B A C D+ + + (B) A B AC D+7 A

(C) [ ]A B A C D+ +_ i (D) [ ]A B A C D+_ i

MCQ 2.1.57 If x and y are Boolean variables, which one of the following is the equivalent of x y xy5 5 ?(A) x y+ (B) x y+

(C) 0 (D) 1

MCQ 2.1.58 The minimized form of X W Y Z XW5+ + l_ _i i is(A) ( )( )X W YZ Y Z XW+ + +l l l

(B) ( )XYZ XY Z WYZ WY Z+ + +l l l l

(C) WYZ WY Z XW+ +l l l

(D) WYZ WY Z+l l

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MCQ 2.1.59 Which of the following logic diagrams represents the original and simplified expression of the function, ( )( )F x y x y= + + l ?

MCQ 2.1.60 A copy machine generate a stop sign S , to stop the machine operation and energize and indicates light if according to either of the following conditions exists:(1) There is no paper in the paper feeder tray.

(2) The two micro switch in the paper path are activated, indicating a jam in the paper path.

The presence of paper in the feeder tray is indicated by a high at logic signal P as shown in figure.

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Which of the following represents the correct logic circuit so as to get HIGH output at S ?

MCQ 2.1.61 In the following circuit, the motor will turn on when DRIVE 1=

Which of the following give correct values of , , , , , , ,A A A A A A A0 1 2 3 4 5 6 ,A A7 8, and A9 in order to move motor ?

(A) A A A A A A A A A A 10 1 2 3 4 5 6 7 8 9= = = = = = = = = =

(B) ; ;A A A A A A A A A A1 00 1 2 3 4 5 6 9 7 8= = = = = = = = = =

(C) ;A A A A A A A A A A1 00 1 2 3 4 5 6 7 8 9= = = = = = = = = =

(D) ;A A A A A A A A A A1 00 1 2 3 4 5 6 7 8 9= = = = = = = = = =

MCQ 2.1.62 When two gates with open collector outputs are tied together as shown in the figure, the output obtained will be

(A) A B C D+ + + (B) A B C D+ + +

(C) ( ) ( )A B C D+ + + (D) ( ) ( )A B C D+ + +

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MCQ 2.1.63 The output of a two level AND-OR gate network is F . What is the output when all the gates are replaced by NOR gates ?(A) F

(B) F

(C) F D

(D) F D

where F D is the dual function of FWhich one of the gates labelled 1,2,3, and 4 in the network shown in the figure is redundant ?

(A) 1

(B) 2

(C) 3

(D) 4

MCQ 2.1.64 For the circuit shown in Figure, the Boolean expression for the output Y in terms of inputs P , Q , R , and S is

(A) P Q R S+ + +

(B) P Q R S+ + +

(C) ( )( )P Q R S+ +

(D) ( )( )P Q R S+ +

MCQ 2.1.65 Which of the following circuit implement the Boolean expression X AB CD= + ?

GATE EE 2002


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(D) None of the above.

MCQ 2.1.66 Consider the logic circuit shown below.

Using NOR gates only, the circuit can be realised as

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MCQ 2.1.67 Which of the following represent the correct realization of the given circuit using NAND gate only ?


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MCQ 2.1.68 The logic operations of two combinational circuits given in Figure - I and Figure - II are

(A) Entirely different (B) Identical

(C) Complementary (D) Dual

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EXERCISE 2.2

QUES 2.2.1 The minimum number of NAND gates required to implement the Boolean function A AB ABC+ + is _____

QUES 2.2.2 The Boolean expression ( , , )Y A B C A BC= + is to be realized using 2-input gates of only one type. The minimum number of gates required for the realization is _____

QUES 2.2.3 The number of different sets of input conditions that produces a high output from a five-input OR gate is _____

QUES 2.2.4 A Boolean function of two variables X and Y is defined as follows :

( , )F 0 0 ( , ) ( , ) ; ( , )F F F0 1 1 1 1 1 0 0= = = =Assuming complements of X and Y are not available, a minimum cost

solution for realizing F using 2-input NOR gates and 2-input OR gates

(each having unit cost) would have a total cost of _____ unit.

QUES 2.2.5 To implement Y ABCD= using only two-input NAND gates, minimum number of requirement of NAND gates is _____

QUES 2.2.6 In circuit shown below, for what input at the terminal A the output is X 1= ?

QUES 2.2.7 If X 1= in logic equation [ { ( )}] [{ ( )}A Z Y Z XY X Z X Y 1+ + + + + = then Z is _____

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QUES 2.2.8 The minimum number of NOR gates required to implement ( )( )A A B A B C+ + + is equal to ______

QUES 2.2.9 In the following circuit the output Z is _____

QUES 2.2.10 The number of distinct Boolean expressions of 4 variables is _____

QUES 2.2.11 The number of duals of distinct Boolean expressions of 4 variables is _____

QUES 2.2.12 To implement Y ABCD= using two-input NAND gates and NOR gates, minimum number of requirement of gates is _____

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EXERCISE 2.3

MCQ 2.3.1 The NAND gate can perform the invert function if the inputs are(A) Connected together (B) Left open

(C) Either (A) or (B) (D) None of these

MCQ 2.3.2 Which of the following gate corresponds to the action of parallel switches for the input ?(A) AND (B) NAND

(C) OR (D) NOR

MCQ 2.3.3 Which of the following gate corresponds to the action of series switches for the input ?(A) AND (B) NAND

(C) OR (D) NOR

MCQ 2.3.4 Which of the following gate is called universal gate ?(A) AND (B) OR

(C) XOR (D) NAND

MCQ 2.3.5 In positive logic, (A) a HIGH 1= , a LOW 0=

(B) a LOW 1= , a HIGH 0=

(C) Only HIGHs are present

(D) Only LOWs are present

MCQ 2.3.6 The output of an AND gate is LOW(A) All the time

(B) When any input is LOW

(C) When any input is HIGH

(D) When all inputs are HIGH

K SHASHIDHAR214/12

K SHASHIDHAR214/13

K SHASHIDHAR214/14

K SHASHIDHAR214/15

K SHASHIDHAR214/16

K SHASHIDHAR214/17


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MCQ 2.3.7 The output of an OR gate is LOW when(A) All inputs are LOW

(B) Any INPUT is LOW

(C) Any input is HIGH

(D) All inputs are HIGH

MCQ 2.3.8 If a three-input AND gate has eight input possibilities, how many of those possibilities will result in a HIGH output?(A) 1 (B) 2

(C) 7 (D) 8

MCQ 2.3.9 If a three-input OR gate has eight input possibilities, how many of those possibilities will result in a HIGH output?(A) 1 (B) 2

(C) 7 (D) 8

MCQ 2.3.10 The output of NOT gate is HIGH when(A) the input is LOW

(B) the input is HIGH

(C) power is applied to the gate’s IC

(D) power is removed from the gate’s IC

MCQ 2.3.11 The output of an AND gate with three inputs, A, B , and C , is HIGH when(A) A 1= , B 1= , C 0=

(B) A 0= , B 0= , C 0=

(C) A 1= , B 1= , C 1=

(D) A 1= , B 0= , C 1=

MCQ 2.3.12 The output of an OR gate with three inputs, A, B, and C , is LOW when(A) A 0= , B 0= , C 0=

(B) A 0= , B 0= , C 1=

(C) A 0= , B 1= , C 1=

(D) All of the above

K SHASHIDHAR214/18

K SHASHIDHAR214/19

K SHASHIDHAR214/20

K SHASHIDHAR214/21

K SHASHIDHAR214/22

K SHASHIDHAR214/23

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MCQ 2.3.13 If a three-input NAND gate has eight input possibilities, how many of those possibilities will result in a HIGH output?(A) 1 (B) 2

(C) 7 (D) 8

MCQ 2.3.14 If a three-input XOR gate has eight input possibilities, how many of those possibilities will result in a HIGH output?(A) 2

(B) 4

(C) 6

(D) 8

MCQ 2.3.15 A two-input NOR gate is equivalent to a(A) negative-OR gate

(B) negative-AND gate

(C) negative-NAND gate

(D) none of the above

MCQ 2.3.16 The exclusive-OR gate’s output is HIGH if(A) All inputs are low

(B) all inputs are HIGH

(C) the inputs are different


MCQ 2.3.17 The exclusive-NOR gate’s output is HIGH if(A) the inputs are the same

(B) one input is High, and the other input is LOW

(C) the inputs are different


MCQ 2.3.18 How many two-input NOR gates does it take to produce a two-input NAND gate ?(A) 1 (B) 2

(C) 3 (D) 4

K SHASHIDHAR215/25

K SHASHIDHAR215/27

K SHASHIDHAR215/32

K SHASHIDHAR215/34

K SHASHIDHAR216/35

K SHASHIDHAR216/38


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MCQ 2.3.19 Boolean algebra can be used to(A) Simplify any algebraic expressions

(B) Minimize the number of switches in a circuits

(C) Solve the mathematical problems

(D) Perform arithmetic calculations.

MCQ 2.3.20 De Morgan’s theorems state that(A) .A B A B+ = and . .A B A B=

(B) A B A B+ = + and . .A B A B=

(C) .A B A B+ = and .A B A B= +

(D) A B A B+ = + and .A B A B= +

MCQ 2.3.21 The gate ideally suited for bit comparison is a(A) Two input Exclusive NOR gate

(B) Two input Exclusive OR gate

(C) Two input NAND gate

(D) Two input NOR gate

MCQ 2.3.22 A buffer is(A) always non-inverting

(B) always inverting

(C) inverting or non-inverting

(D) none of above

MCQ 2.3.23 Symbol in figure given below is IEEE symbol for

(A) AND (B) OR

(C) NAND (D) NOR

MCQ 2.3.24 As per Boolean Algebra, inputs can be interchanged in(A) OR gates (B) AND gates

(C) both OR and AND gates (D) none of above

V K PURI94/1

V K PURI95/13

V K PURI95/16

B.R. GUPTA73/521

B.R. GUPTA83/522

B.R. GUPTA85/522

Chap 2


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MCQ 2.3.25 In which function is each term known as minterm(A) SOP (B) POS

(C) Hybrid (D) both SOP and POS

MCQ 2.3.26 For a certain two-input logic gate, the output is ‘1’ for like inputs and ‘0’ for unlike inputs. The logic gate is(A) Ex-OR (B) NAND

(C) NOR (D) Ex-NOR

MCQ 2.3.27 In general, logic gates whose all output entries are logic ‘1’ except for one entry that is logic ‘0’ are(A) AND, OR

(B) NAND, NOR

(C) NAND, OR

(D) NOR, AND

MCQ 2.3.28 A logic gate with four inputs can have(A) 16 possible input combinations

(B) 4 possible input combinations

(C) 8 possible input combinations

(D) None of these

MCQ 2.3.29 The dual of a Boolean expression is A B+ . The expression is(A) A B: (B) A B:l l

(C) A B+l l (D) A B+

MCQ 2.3.30 Complement of complement of A B A B: :+l l is(A) A B A B: :+ l l

(B) A B A B:+ +l l_ _i i

(C) A B A B: :+l l

(D) None of these

MCQ 2.3.31 The operation A A: =(A) A 2 (B) A2

(C) 1 (D) A

B.R. GUPTA94/522

MAINI1/102

MAINI4/103

MAINI8/103

MAINI4/200

MAINI5/200


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MCQ 2.3.32 The operation A A+ =(A) A 2 (B) A2

(C) 0 (D) A

MCQ 2.3.33 The operation A A+ =(A) 1 (B) A

(C) 0 (D) A

MCQ 2.3.34 The operation A A: =(A) 1 (B) A

(C) 0 (A) A

MCQ 2.3.35 The AND, OR, and NOT gates are called(A) universal gates

(B) basic gates

(C) hexadecimal gates

(D) decimal number gates

MCQ 2.3.36 The gate shown in Fig. is an alternative symbol of

(A) AND gate (B) OR gate

(C) NAND gate (D) NOR gate

MCQ 2.3.37 The gate shown in Fig. is an alternative symbol of

(A) AND gate

(B) OR gate

(C) NAND gate

(D) NOR gate

ChakravortyM4.10/111



ChakravortyM6.1/170

ChakravortyM6.6/171

ChakravortyM6.7/171

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MCQ 2.3.38 The gate shown in below is an alternative symbol of

(A) AND gate (B) OR gate

(C) NAND gate (D) NOR gate

MCQ 2.3.39 The gate shown below is an alternative symbol of

(A) AND gate

(B) OR gate

(C) NAND gate

(D) NOR gate

MCQ 2.3.40 In a positive logic circuit,(A) Logic 0 and 1 represented V0 (ground) and positive voltage

VCC+_ i respectively

(B) Logic 0 and 1 represented by negative and positive voltages respectively

(C) Logic 0 voltage level is higher than logic 1 voltage level

(D) Logic 0 voltage level is lower than logic 1 voltage level

MCQ 2.3.41 In negative logic, the logic 1 state corresponds to(A) Ground level

(B) High voltage level

(C) Negative voltage level

(D) Low voltage level

MCQ 2.3.42 A NAND gate is called a universal logic element because(A) All digital computers use NAND gates

(B) All the minimisation techniques are applicable for optimum NAND gate realisation

(C) Every body use this gate

(D) Any logic function can be realised by NAND gates alone

Chakravorty

M6.8/171

ChakravortyM6.9/171

MANDAL1/72

MANDAL2/72

MANDAL3/72


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MCQ 2.3.43 Boolean algebra is different from ordinary algebra in which way ?(A) Boolean algebra can represent more than 1 discrete level between

0 and 1.

(B) Boolean algebra have only 2 discrete levels : 0 and 1

(C) Boolean algebra can describe up to levels of logic levels

(D) They are actually the same

MCQ 2.3.44 The voltage levels for positive logic system(A) must necessarily be positive

(B) must necessarily be negative

(C) may be positive or negative

(D) must necessarily be 0 V and 5 V

MCQ 2.3.45 Knowledge of binary number system is required for the designers of computers and other digital systems because(A) it is easy to learn binary number system

(B) it is easy to learn Boolean algebra

(C) it is easy to use binary codes

(D) the devices used in these systems operate in binary

MCQ 2.3.46 Which of the following statements is true ?(A) OR and NOT gates are necessary and sufficient for realization of

any logic function.

(B) AND and NOT gates are necessary and sufficient for realization of any logic function.

(C) NAND gates are not sufficient to realize any logic function.

(D) NOR gates are sufficient to realize any logic function.

MCQ 2.3.47 For the gate shown in the figure, the output will be HIGH

(A) if and only if both inputs are HIGH

(B) if and only if both the inputs are LOW

(C) if one of the inputs is LOW

(D) if one of the inputs is HIGH

MANDAL17/73

ANAND KU-MAR10/21

ANAND KU-MAR1/65

ANAND KU-MAR51/136

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MCQ 2.3.48 In a digital computer binary subtraction is performed(A) in the same way as we perform subtraction in decimal number

system

(B) using 2’s complement method

(C) using 9’s complement method

(D) using 10’s complement method

MCQ 2.3.49 The most suitable gate to check whether the number of 1s in a digital word is even or odd is(A) X-OR (B) NAND

(C) NOR (D) AND, OR, and NOT

MCQ 2.3.50 Which of the following operations is commutative but not associative ?(A) AND (B) NOR

(C) OR (D) X-OR

MCQ 2.3.51 ...A AB ABC ABCD ABCDE+ + + + + =(A) 1 (B) A

(C) A AB+ (D) AB

MCQ 2.3.52 ....A AB A BC A B CD+ + + + =(A) ...A B C+ + + (B) ...A B C D+ + + +

(C) 1 (D) 0

MCQ 2.3.53 The number of table entries needed for a five input logic circuit is(A) 4 (B) 8

(C) 16 (D) 32

MCQ 2.3.54 The dual of a Boolean expression is obtained by(A) interchanging all 0s and 1s

(B) interchanging all 0s and 1s, all + and ‘ : ’signs

(C) interchanging all 0s and 1s, all + and ‘ : ’ signs and complementing all the variables

(D) interchanging all + and ‘ : ’ signs and complementing all the variables

ANAND KU-MAR25/67

ANAND KU-MAR63/137

ANAND KU-MAR65/138

ANAND KU-MAR1/192

ANAND KU-MAR2/192

ANAND KU-MAR15/192


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MCQ 2.3.55 The complement of a Boolean expression is obtained by(A) interchanging all 0s and 1s

(B) interchanging all 0s and 1s, all + and ‘ : ’ signs

(C) interchanging all 0s and 1s, all + and ‘ : ’ signs and complementing all the variables

(D) interchanging all + and ‘ : ’ signs and complementing all the variables

MCQ 2.3.56 All Boolean expressions can be implemented with(A) NAND gates only

(B) NOR gates only

(C) combinations of NAND and NOR gates

(D) Any of these

MCQ 2.3.57 Which of the following logic gates will have an output of 1 ?

MCQ 2.3.58 Boolean algebra is essentially based on(A) symbols (B) logic

(C) truth (D) numbers

MCQ 2.3.59 X XY+ is reduced to(A) X (B) X Y+

(C) X Y+ (D) X Y+

MCQ 2.3.60 A carry look ahead adder is frequently used for addition, because it(A) is faster (B) is more accurate

(C) uses fewer gates (D) costs less

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ANAND KU-MAR16/192

SEDHA7/118

SEDHA1/183

SEDHA15/184

KHARATE7/197

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SOLUTIONS 2.1

SOL 2.1.1 Correct option is (B).From the Boolean properties, we know that

So, its equivalent logic will be

i.e. AND-Invert = Invert-ORBy converting AND Invert logic to equivalent Invert-OR logic in the given circuit diagram, we get

So, the output Z is

Z AB CD EF= + +

ALTERNATIVE METHOD :Expression of output can be directly obtained from given circuit as

Z AB CD EF= _ _ _i i i

Using De-Morgan’s theorem, we have

Z AB CD EF= + +

SOL 2.1.2 Correct option is (D).From the Boolean properties, we know that


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So, its equivalent logic will be

i.e. AND-Invert = Invert-ORApplying the property, we have the modified logic circuit as

So, the output X is

X MNQ MNQ MNQ= + + MQ N N MNQ= + +_ i

MQ MNQ= +

Q M MN= +_ i

Q M N= +_ i

SOL 2.1.3 Correct option is (A).We convert the AND-Invert logic to equivalent Invert-OR logic as

or

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So, the output Z is given as

Z AB E C D= + +_ i

SOL 2.1.4 Correct option is (C).By using the Boolean properties, we minimize the given Boolean expression as

X Y X Y X Y+ + +_ _ _i i i X Y X X XY X Y Y Y: := + + + +_ _i i

X Y XY X Y= + +_ _i i

XY XY= + XY=

SOL 2.1.5 Correct option is (D).From the given logic diagram, expression of the output can be written as

Z A AB BC C= + + +_ i

A A B B C C= + + + + +

A B C

ABC

= + +

=4

From the above logic function, we can observe that options (A) and (B) are matched. Now, we check the expression given in option (C).

Z AB BC AC= + + A B B C A C= + + + + + A B C= + +Hence, all the options are same, and equal to the output Z of the given logic circuit.

SOL 2.1.6 Correct option is (B).Given that

AB AC BC+ + AB AC= +From Consensus Theorem, when a particular variable is associated with some variable and it’s complement is associated with another variable and next term is formed by the leftover variables, then the last term becomes redundant.


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term

AB AC BCredundant

+ +S

AB AC= +

It’s dual also exists. Taking dual of the expression, we get

A B A C B C+ + +_ _ _i i i A B A C= + +_ _i i

Hence, A C B C A B+ + +_ _ _i i i A B A C= + +_ _i i

SOL 2.1.7 Correct option is (A).Expression of output for the circuit is given by

X A B A B5 := +_ _i i

AB AB AB= +_ _i i

AB=

SOL 2.1.8 Correct option is (B).Expression of the output for the circuit is given by

Y A B C5 := _ i

AB AB C:= +_ i

AB AB C= + +_ i {Using De Morgan’s theorem}

AB A B C= + +_ i {A B A B9 5= or A B A B5 9= }

A B AB C= + +

SOL 2.1.9 Correct option is (C).Expression of the output Z for the circuit is given by

Z A A A B C: : := +_ i

ABC= {A A 1+ = }

SOL 2.1.10 Correct option is (A).Expression of the output Z for the circuit is given by

Z A B B C: := +_ _i i

A B B ABC: := + ABC= {B B 0: = }

SOL 2.1.11 Correct option is (A).The expression of the output Z for the circuit is given by

Z A B BC:= +_ i

AB BC:= {Using De-Morgan’s theorem}

ABC=

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SOL 2.1.12 Correct option is (C).Expression for X from given table is obtained by writing logic for X corresponding to 0 output. i.e.

X A BC ABC= + A A BC= +_ i {A A 1+ = }

BC=

SOL 2.1.13 Correct option is (A).Given expression is A BC+ . Using distributive law, we have

A BC+ A B A C= + +_ _i i

This law states that ANDing of several variables and ORing the result with a single variable is equivalent to ORing that single variable with each of the several variables and then ANDing the sums. It can be verified from the table below.

A B C A B+ A C+ A B A C+ +_ _i i A BC+

0 0 0 0 0 0 0

0 0 1 0 1 0 0

0 1 0 1 0 0 0

0 1 1 1 1 1 1

1 0 0 1 1 1 1

1 0 1 1 1 1 1

1 1 0 1 1 1 1

1 1 1 1 1 1 1

SOL 2.1.14 Correct option is (B).The expression of Z from given truth table can be written for logic 1 or indirectly we can solve for Z and then take complement. The expression for Z is given by , writing logic expression for 0 output as,

Z A BC=Taking complement, we get

Z Z= A BC= {Using De-Morgan’s theorem}

or Z A B C= + +Now, we check the result for the given options. From expression given in option (B), we get same minimized result.

A B B C+ +_ _i i A B B C= + + +_ _i i

A B C= + +


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SOL 2.1.15 Correct option is (A).From truth table, the expression of the function f is given by

f ABC ABC= + B AC AC= +_ i

B A C A C= + +_ _i i

SOL 2.1.16 Correct option is (D).The given Boolean expression is rewritten as

AC BC+ AC B B BC A A= + + +_ _i i

or AC BC+ ABC ABC ABC ABC= + + +

SOL 2.1.17 Correct option is (D).The given expression is A AB A BC A B CD A B C DE+ + + +On simplification of the expression using Boolean algebra, we get

A AB A BC A B C D A B C DE+ + + +

A A B B C C D DE= + + + +_ i8 B# - ...(1)Using redundant literal rule, we have

A AB+ A B= +or A A B C+ +_ i A B C= + +Applying this rule in equation (1), we get

A AB A BC A B C D A B C DE+ + + + A A B B C C D E= + + + +_ i7 A# -

A A B B C D E= + + + +_ i# -

A A B C D E= + + + +_ i

A B C D E= + + + +

SOL 2.1.18 Correct option is (B).Given logic function is

Y A B C AB AC= + +_ i# -

On simplification, we get

Y AB AC A B A C= + + +_ _i i7 A

AB AC A A C A B B C= + + + +_ i

AB=

SOL 2.1.19 Correct option is (D).Given logic expression is

Y AB AB:= _ _i i

On simplification by using Boolean algebra, we get

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Y AB AB:= _ _i i (Using De-Morgan’s theorem)

A B A B= + +_ _i i

AA A B AB BB= + + +_ i

A B AB= +

SOL 2.1.20 Correct option is (B).

Given that Z XY XY= +So, we simplify the given function as

XZ XZ+ X XY XY X XY XY= + + +_ _i i

X XY X Y XY= + +_ i

XY XY= +

Y X X= +_ i

Y=

SOL 2.1.21 Correct option is (A).

Given that XY 0=Since, we know that

X Y5 XY XY= + X Y5 X Y9=So, by using the given condition, we get

X Y5 XY XY XY X Y= + = +_ i

or X Y5 X Y X Y= = + (XY 0= )

SOL 2.1.22 Correct option is (C).Rearranging the given expression, we get

Z A EF BC D A D E BC D F= + + + + + +7 7A A

A BC EF D A BC D E F= + + + + + +_ i7 7A A

A BC EF D A BC D EF= + + + + + +_ _ _ _i i i i7 7A A

Let A BC+ X=and EF D+ Y=So, we may write Z X Y X Y= + +_ _i i

X XY XY= + + X Y Y1= + +7 A

X= A BC= +Given that A 0= , then

Z BC=


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SOL 2.1.23 Correct option is (C).There are Four inputs (let A, B , C , D ) to a OR gate. So, we have

Total no. of input conditions 2 164= =Now, the output of OR gate is given by

Z A B C D= + + +i.e. the output is High, if any one out of 4 input is high; and output will Low, only for one condition (0 0 0 0). Thus, output will high for 15 input conditions.

SOL 2.1.24 Correct option is (C).The expression for the output of given circuit is

F A B A A B A B A:= + + + + + +_ _ _i i i7 7A A

Let A B+ X= and A A B Y+ + =_ i

So, the expression for output can be minimized as

F Y X Y= +_ i

Y XY Y X Y1= + = + =_ i

A A B= + +_ i

A A B:= +_ i

AA AB= + AB=Thus, we may conclude that

F 1= for A 0= and B 1=

SOL 2.1.25 Correct option is (A).We check the given requirements for the circuits given in the options. Consider the circuit of option (A).

1. For B C= :

P B C 05= =and X A A0= + =i.e. Output X will equal A when control input B and C are the same.

2. For B C! :

P B C 15= =and X A 1 1= + =i.e. X will remain HIGH when B and C are different.Hence, the circuit satisfies both the requirements.

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SOL 2.1.26 Correct option is (A).We check the circuits in given option for the required condition. The output of the logic circuit will be high only when both inputs of last AND are high. Now, we have the two conditions:1. Given that A and B are both High. For A and B as logic High,

one input of last AND gate is high for the circuits given in options (A) and (B).

2. Given that C and D are either both LOW or both HIGH. For the circuit given in option (A), if C and D inputs are either both high or both low, i.e. C D= applied to XNOR gate then

C D9 1= for C D= i.e. another input of last AND gate will be High.

Thus, the circuit given in option (A) is HIGH whenever A and B are both HIGH as long as C and D are either both LOW or both HIGH.

SOL 2.1.27 Correct option is (D).Consider a 2-input OR gate shown below.

Now, we check the correctness of the given two statements.1. Given that output waveform X_ i is same as the any one input

(let A). For this condition, we may have the following two state diagrams.

From the above state diagram, we may observe that it is not necessary that B should be permanently Low to satisfy the required condition. Therefore, statement-1 is False.

2. Given that output wave form X_ i is always high. Again, we may draw the state diagram for the condition.


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From the above state diagram, we observe that it is not necessary that any one input should be permanently high. Therefore, statement-2 is False.

SOL 2.1.28 Correct option is (A).Given Boolean function is

Z ABC=To obtain the Boolean expression in form of NAND gate output and NOR gate output, we rewrite the expression as

Z ABC ACB AC B= = = +Let AC D=then Z D B= +Therefore, one NAND gate and one NOR gate is required to implement the Boolean function as shown below.

Hence, the minimum cost for the implementation is 2 units.

SOL 2.1.29 Correct option is (C).Given Boolean function,

Z ABC=To implement the function using using only NAND gates, we draw the logic circuit as

Now, we convert each gate to its NAND implementation.

Thus, the minimum cost for implementation of the function using NAND gate will be 5 units.

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SOL 2.1.30 Correct option is (D).For the LED circuit, we know the following points:1. Output of NAND gate must be Low for LED to emit light.

2. Both inputs to NAND must be High for Low output.

3. If any one of the switches is closed, output of AND gate will be Low.

4. If Both switches are open, output of XOR gate will be Low.

So there can not be both input High to NAND. Therefore, LED does not emit light irrespective of the switch positions.

SOL 2.1.31 Correct option is (D).For the given circuit, we have

Output of 1 st XOR X X X1 1: := + = Output of 2 nd XOR X X5= X X XX 1= + = Output of 3 rd XOR X15= X X X1 1: := + = and so on.

Hence, after 2, 4, 6, 8, .......20 XOR (i.e. even number of XOR gates),

output will be 1.

SOL 2.1.32 Correct option is (C).For the given network, we obtain

Output of gate 1 X X0 1= Output of gate 2 X X X0 1 2= + Output of gate 3 X X X X0 1 2 3= +_ i

X X X X X0 1 3 2 3= +Similarly, we may deduce

Output of gate 4 X X X X X X0 1 3 2 3 4= + + Output of gate 5 X X X X X X X0 1 3 2 3 4 5= + +_ i

X X X X X X X X X0 1 3 5 2 3 5 4 5= + +Hence, the output of gate n would be

......... ......... .......... ........F X X X X X X X X X X X X X X Xn n n n n0 1 3 5 2 3 5 4 5 7 1= + + + + -

SOL 2.1.33 Correct option is (C).Given that G1 has delay of 10 ns and G2 has delay of 20 ns. Let output of G1 is X . So, we get the output waveform for the given circuit as shown below.


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SOL 2.1.34 Correct option is (D).From the circuit diagram, we have

X PQ= Y P Q= +and Z X Y PQ P Q:= = +_ _i i

P Q P Q= + +_ _i i

PQ PQ= + P Q5=and M1 Z R5=Hence, M1 P Q R5 5= _ i

M1 XOR XORP Q R= _ i

SOL 2.1.35 Correct option is (A).XOR logic using 2-input NAND gates is implemented as

Now, we may prove that the above logic circuit implements an XOR gate

Z XY X XY Y:= _ _i i$ $. .

XY X XY Y= +_ _i i

X Y X X Y Y= + + +_ _i i

XY XY X Y5= + =Thus, 4 NAND gates are required

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SOL 2.1.36 Correct option is (A).In negative logic system, Low-level or more negative represent the logic 1 and HIGH level or less negative represent the logic 0, as illustrated in figure below.

SOL 2.1.37 Correct option is (D).In positive logic system Low-level or more negative represents the logic 0 and HIGH level or less negative represents the logic 1.

SOL 2.1.38 Correct option is (C).Ex-OR gate output is given by

Y A B5= (A and B are inputs)

AB AB= +To make inversion of a input using XOR gate, we consider one input, let A. So, we must have the output

Y A=For the required output, we should take another input at logic 1 (High). i.e.

Y A A1 1: := + A=

SOL 2.1.39 Correct option is (B).We know that, XOR output is logic 1 when both inputs are not equal and logic 0 when both inputs are same. Hence, we have

A B5 0= for A B= A B5 1= for A B! i.e. (a 2" ) and d 1"_ i

Again, XNOR output become logic 0, if any one input of XNOR is logic 1 (high), i.e.

A B+ 0= for A 1= or B 1= or A B 1= = i.e. b 3"_ i

Also, we have

A B: 0= for A 1= or B 0= i.e. c 4"_ i

Therefore, the correct match in the list is

(a 2" ), b 3"_ i, c 4"_ i, d 1"_ i


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SOL 2.1.40 Correct option is (A).A NAND gate output can be expressed as

Y ORA B A B A B:= = + =So, NAND gate is equivalent to an OR gate with its inverted inputs.

Again, the NOR gate output can be expressed as

Y ANDA B A B A B:= + = = _ i

Hence, NOR gate is equivalent to an AND gate with its inverted input.

Therefore, statements (1) and (2) are correct.

SOL 2.1.41 Correct option is (B).For given logic circuit, expression for output X is

X A B B:= +_ i A B B= + +_ i

A B B= + +^ h A B= +Output waveform for the given input waveforms is

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SOL 2.1.42 Correct option is (C).The expression of the output for the given logic circuit is

X AB A B A B9= + =So, we may conclude that

X A B 19= = for A B= 0= for A B!

Therefore, we obtain the output waveform for the given input waveforms as

SOL 2.1.43 Correct option is (D).The expression of the output for the given logic circuit is

X A B B= + +_ i

A B B:= +_ i

A B B: := _ i

0=Hence, the output for the circuit will remain zero irrespective of the input.

SOL 2.1.44 Correct option is (C).According to the given problem, we represent the fruits as A = apple; B = banana; M = Mango; O = orangeSo, the logical expression that specifies the fruit available for desert is

, , ,f A B M O_ i st Choice nd Choice rd Choice1 2 3= + +_ _ _i i i

O A OA MA OB= + + + +_ _ _i i i

A O MA BO= + + +_ i

A M O B1 1= + + +_ _i i

A O= +


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SOL 2.1.45 Correct option is (C).The wired AND in open-collector is given by

Since, for the given circuit, we have

C A= and D B=Hence, the output of the circuit is given as

F AB A B:= AB AB= + XORA B A B5= = _ i

SOL 2.1.46 Correct option is (C).Given Boolean expression is w x w x yz w y+ + + +l l l_ _ _i i i

On simplification, we obtain

w x w x yz w y+ + + +l l l_ _ _i i i w x yz w xy= + + +l l l_ _i i

ww w xy xw xxy yz w yz xy= + + + + +l l l l l l l

w xy xy xw yz w= + + +l l l l

w xy w x yz1= + + +l l l_ _i i

xy wx wyz= + +l l

SOL 2.1.47 Correct option is (A).The elevator door will open in the following two cases.Case 1: If the elevator is stopped, it is level with the floor, and the timer has not expired.Since, we have the representations

Elevator is stopped S= ;

Level with the floor F= ;

Time has not expired T= l

So, the given condition is expressed as

X1 SFT= l

Case 2: If the elevator is stopped, it is level with the floor, and a button is pressed.Again, we have the representations

Elevator is stopped S=and Level with the floor F=and Button is pressed B=So, the given condition is expressed as

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X2 SFB=Since, the door will be open is case-1 or case-2. Therefore, we may express the condition for elevator door to be open as

D ORX X1 2=or D SFT SFB= +l

SOL 2.1.48 Correct option is (D).Given logic circuit is

So, the output Z is given by

Z X X Y= + + X X Y X X Y: := + = +_ i

X XY= + X Y1= +_ i X= X=In option (D), the circuit provides the output X as shown below.

Hence, the circuit given in option (D) is minimized form of the logic circuit.

SOL 2.1.49 Correct option is (B).We redraw the given logic circuit as

Output Z of the logic circuit is

Z AB CD ABCD A D= + +


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AD B C BC A D= + +^ h

AD B C A D9= +_ i

AD B C A D5= +_ i

SOL 2.1.50 Correct option is (D).Given Boolean expression is AD ABCD ACD AB ACD A B+ + + + +On minimization using Boolean algebra, we get

AD ABCD ACD AB ACD A B+ + + + +

AD BC C C AB A B1= + + + + +_ i

AD AB A B= + + AD A B B= + +_ i AD A= + A A D A= + +_ _i i A D= +

NOTE :Here, it must be noted that, we got first the expression AD A+^ h, and this is also given in option (B). At first glance it seems to be Answer but it is not. It can be minimized further into A D+^ h.

SOL 2.1.51 Correct option is (C).We redraw the given digital circuit as

Output Y is given by

Y AB AB= + XORA B A B5= = _ i

SOL 2.1.52 Correct option is (A).We have the switching circuit as

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Now, we consider the parallel switches as shown below.

The logic expression for parallel switches is obtained as

L A B= +Again, we consider the series connected switches

The logic expression for series connected switches is

L A B:=Hence, the logic expression for given circuit is

L A B C D E: := + +_ _i i

SOL 2.1.53 Correct option is (A).We have to check the correctness of each options.

Option (A)

On minimizing L.H.S. of the equation, we have

X XY+ X X X Y= + +_ _i i X Y= + X!

or X XY+ X!

Option (B)


X X Y+_ i XX XY= + XY=or X X Y+_ i XY=Option (C)


X XY+ X Y1= +_ i X=or X XY+ X=Option (D)


ZX ZXY+ Z X XY= +_ i Z X Y= +_ i ZX ZY= +or ZX ZXY+ ZX ZY= +


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SOL 2.1.54 Correct option is (D).We have the switching circuit diagram as

From the circuit diagram, we deduce that LED will glow when LowZ 0= _ i, and Z will be low only when X or Y or both will be

High. Now, we consider the different input conditions as1. For A B 1= = ,

X 1= and Y 0= Z 0& = ; LED glows2. For A B 0= = ,

X 0= and Y 1= Z 0& = ; LED glows3. For A 0= , B 1= ;

X 0= and Y 0= Z 1& = ; LED doesn’t glow4. For A 1= , B 0= ;

X 0= and Y 0= Z 1( = ; LED doesn’t glow

SOL 2.1.55 Correct option is (C).We have the Boolean identity

AB AC+ A C A B= + +_ _i i

Dual form of any identity can be found by replacing all AND function to OR and vice-versa. Hence, dual form of the expression is given as

A B A C:+ +_ _i i A C A B: := +_ _i i

SOL 2.1.56 Correct option is (D).Dual form of any identity can be found by replacing all AND functions to OR functions and vice-versa. Now, we have the Boolean expression as

A B AC D+ + +_ i7 A

So, the dual form of the expression is given as

A B A C D: : :+_ i7 A

or A B A C D:+_ i7 A

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SOL 2.1.57 Correct option is (B).We have the Boolean expression as

Z x y xy5 5=On minimizing the expression, we have

Z x y xy5 5= 7 A

x yxy yxy5= +7 A

x y x y 05= + +_ i7 A

x yx 05= +7 A

x yx x yx: := + x y x xy= + +_ i x xy xy= + +

x y xy1= + +_ i x xy= +

x y= +

SOL 2.1.58 Correct option is (C).We have the Boolean expression as

X W Y Z XW5+ + l_ _i i

On simplification and minimization of the Boolean expression, we get

X W Y Z XW5+ + l_ _i i X W YZ Y Z XW= + + +l l l_ _i i

XYZ XY Z WYZ WY Z XW= + + + +l l l l l

From consensus theorem, we have

AB AC BC+ + AB AC= +So, eliminating the redundant term in the expression, we get

i.e. the minimized expression of X W Y Z XW5+ + l_ _i i is WY Z XW WYZ+ +l l l

SOL 2.1.59 Correct option is (B).We have the Boolean expression

F x y x y= + + l_ _i i ...(1)On simplification, we get the expression

Fsimplified x xy xy yy= + + +l l

x y y1= + +l_ i

x= ...(2)Hence, the logic diagram for the expression (1) and (2) is shown below.


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SOL 2.1.60 Correct option is (C).To get output at High state, i.e. to stop the Machine operation; either P is low (no paper in paper feeder) or Q and R are high (jam in paper path). Hence, logic expression for output S is

S P Q R:= +So, the logic circuit for the given condition is drawn as

SOL 2.1.61 Correct option is (B).We redraw the given logic circuit as

DRIVE is active-HIGH, and it will go high only when

X Y 0= =X will be LOW only when either andA A8 9 is HIGH.

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Y will be LOW only when andW A0 07= =W will be LOW only when A0 through A6 are all HIGH.Putting this all together, we have the condition for DRIVE to be high as

A0 A A A A A A 11 2 3 4 5 6= = = = = = = A7 0=and either A8 or A9 or both are 1

SOL 2.1.62 Correct option is (A).We have the wired-OR logic circuit as shown below.

For the logic circuit, the output is

Y A B C D= + + +_ _i i

SOL 2.1.63 Correct option is (C).We have the two level AND-OR gate as shown below.

Now, all the gates are replaced by NOR gate. So, we get the modified circuit as

Hence, the output of the modified network is

Z A B C D= + + +_ _i i

A B C D:= + +_ _i i

= dual of F FD=


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SOL 2.1.64 Correct option is (C).The output function for the given circuit is

f xyz wyz wxz= + +Let y A= ; x B= ; w C=then f Z AB AC BC= + +_ i

Using consensus theorem, we conclude that BC term is redundant. So, we have

f Z AB AC= +_ i

or f xyz wyz= +Hence, gate 3 is redundant.

SOL 2.1.65 Correct option is (B).We have the logic circuit as shown below

From the Boolean algebra, we have

By using the above conversion, we redraw the given logic circuit as

Hence, the output of the logic circuit is

Y P Q R S= + + +

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SOL 2.1.66 Correct option is (A).All the given circuit in the options include NOR gate. So, we implement the given expression using NOR gate as

X ( )( )AB CD A B C D= + = + +

( ) ( )A B C D= + + +

SOL 2.1.67 Correct option is (B).In order to convert the given circuit into all NOR, we apply the bubbles at the input terminals of gates as shown below.


and

Therefore, by using the above conversion, we get the logic circuit with NOR gates.


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SOL 2.1.68 Correct option is (D).In order to convert the given circuit using only NAND gate, we apply bubbles at the input terminal of each gates as shown below.


and

Therefore, by using the above conversion, we get the logic circuit with NAND gates as

SOL 2.1.69 Correct option is (A).Figure IWe have the combinational circuit in Figure - I as

So, the output of the circuit is

F1 ( )X X Y= + + ( )X X Y= + XX XY= + XY=Figure IIWe have the combinational circuit in Figure - II as

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So, the output of the circuit is

F2 X Y$=Hence, we have

F1 F2!

i.e. the output of the given two circuits are entirely different.

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SOLUTIONS 2.2

SOL 2.2.1 Correct answer is 0.Given Boolean function is

F A AB ABC= + + A B BC1= + +_ i A=Therefore, no gate is required to implement this function.

SOL 2.2.2 Correct answer is 3.As the given expression is to be realized using one type of 2-input gates. So, we may use universal gates (NAND, NOR) for realization. Now, we implement the given function using NAND and NOR gates.1. NAND Implementation: For NAND implementation, we rewrite the given expression

Y A BC A BC A BC:= + = + = _ _i i

So, the logic circuit can be implemented as

2. NOR Implementation: For NOR implementation, we rewrite the given expression as

Y A BC A B A C= + = + +_ _i i; [Distributive

property]

or Y A B A C= + +_ _i i

A B A C= + + +_ _i i

Thus, to implement given circuit, minimum 3 gates are required.

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SOL 2.2.3 Correct answer is 31.We know that, if any one input of the OR gate becomes high logic (1), OR gate gives the high logic (1) output. The output is High only for the case when all the inputs are at Low logic (0). Now, for 5-inputs, we have

Total number of input conditions 2 325= =Out of the 32 conditions, all inputs are zero (0) for only one condition. i.e. for only one condition the output is low.Hence, 31 input conditions produce the high output from a five-input OR gate.

SOL 2.2.4 Correct answer is 2.The Boolean function of two variables x and y are defined as

,f 0 0_ i , ,f f0 1 1 1 1= = =_ _i i and ,f 1 0 0=_ i

For the Boolean function, we obtain the truth table as

x y f

0 0 1

0 1 1

1 0 0

1 1 1

From the truth table, we define the function f as

f xy=So, f xy x y= = +Hence, the function f_ i can be implemented using 2 input NOR and 2-input OR gate as shown below.

Thus, the total cost for the logic circuit will be 2 units.

SOL 2.2.5 Correct answer is 6.The circuit is as follows


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SOL 2.2.6 Correct answer is 011.For given logic circuit, output X 1= , if all inputs to AND gate are High. The output for the circuit can be expressed as

X A B B C C5 : 9 := _ _i i

Also, we have

A B5 1= if A B!

and B C9 1= if B C=Hence, for X 1= , the required conditions are

C must be High

B C 1= = A 0= (since A B! )

SOL 2.2.7 Correct answer is 0.Given the logic equation,

X Z Y Z XY X Z X Y+ + + + +_ _i i7 A# #- - 1=and X 1=So, by substituting X 1= and X 0= in the logic equation, we get

Z Y Z Y Z Y1 1 0 1:+ + + + +_ _i i7 8A B# - 1=or Z1 1_ i7 8A B 1=Hence, we have Z 1= or Z 0=

SOL 2.2.8 Correct answer is 0.Given logic expression is A A B A B C+ + +_ _i i

On solving the expression, we have

A A B A B C+ + +_ _i i AA AB A B C= + + +_ _i i

A AB A B C= + + +_ _i i

A AB A AB A B B AC ABC: : := + + + + + A AB AC ABC= + + + A B C BC1= + + +_ i A=Therefore, no gate is required to implement this function.

SOL 2.2.9 Correct answer is 1.From the given circuit, we can observe that input to last XNOR gate is same. So, the XNOR output is given by (Let input is X )

Z X X X X X X 1: := + = + =i.e. the output will be High (logic 1), irrespective of the inputs A and B .

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SOL 2.2.10 Correct answer is 65536.The number of distinct Boolean expressions of n variables is 2 2 n . Since, we have

n 4=Hence, the number of distinct Boolean expressions is

2 2 n 2 2 655362 164= = =

SOL 2.2.11 Correct answer is 256.The number of duals of distinct boolean expressions of n variables is 2 2 n 1- . Since, we have n 4= . Hence, the number of duals of distinct Boolean expressions is

2 2 n 1- 2 2 2 2562 2 84 1 3= = = =-

SOL 2.2.12 Correct answer is 3.To implement the given function using NAND and NOR gates, we rewrite the given function as

Y ABCD ABCD AB CD= = = +So, the equivalent circuit for the Boolean function is

Therefore, two NAND gates and one NOR gate is required to implement the function Y ABCD= .

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SOLUTIONS 2.3

SOL 2.3.1 Correct option is (A).NAND gate output Y A B:=Where, A and B are inputs, if inputs are connected together, i.e. A B= Y A A A:= =

SOL 2.3.2 Correct option is (C).


SOL 2.3.4 Correct option is (D).




SOL 2.3.8 Correct option is (A).AND gate output Y A B C: :=If any one of the inputs is LOW then output becomes LOW. Output will HIGH only when all the inputs are HIGH.For 3-inputs, 8 input possibilities are there, out of which only one case has all inputs high.


OR gate output Y A B C= + +If any one input is HIGH, output will be HIGH. Output will be LOW

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only when all three inputs become LOW.Out of 8 input possibilities, seven cases have one or more inputs high results in HIGH.




SOL 2.3.13 Correct option is (C)


SOL 2.3.15 Correct option is (B).Output of two input ,A B_ i NOR gate, Y A B= +Using De’morgan theorem, Y A B:= = negative-

AND gate



SOL 2.3.18 Correct option is (D).Two-input NAND gate using two-input NOR gate is realized as :


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SOL 2.3.21 Correct option is (A).The Ex-NOR gate output is HIGH only when both input bits of it are equal.Hence, Ex-NOR gate is suitable for bit comparison.




AND : Y A B B A: := = OR : Y A B B A= + = +


SOL 2.3.26 Correct option is (D).The truth table for Ex-NOR gate is,

Inputs Output

A B Y A B9=

0 0 1

0 1 0

1 0 0

1 1 1

The output is ‘1’ for like inputs and ‘0’ for unlike inputs.

SOL 2.3.27 Correct option is (C).The truth table for NAND and OR is,

Chap 2


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Inputs Outputs

A B X A B:= Y A B= +

0 0 1 0

0 1 1 1

1 0 1 1

1 1 0 1

For both NAND and OR gates, all output entries are logic ‘1’ except for one entry.



SOL 2.3.30 Correct option is (C).Taking of two times complement results the original function.

Y AB AB= +

Complement of Y Y AB AB= = +

Complement of Y Y Y AB AB AB AB= = = + = +







Y A B A B$= + = = NAND gate logic


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Y .A B A B= = + = NOR gate logic


Y .A B A B A B= = + = + = OR gate logic


Y A B A B$= + = = AND gate logic







SOL 2.3.46 Correct option is (D).NAND and NOR gates are universal gates. Any logic function can be realized using only NAND or only NOR gates.So, AND, OR and NOT gates are not necessary to realize any logic function.


X .A B A B= = + = NOR gate logicHence, output will be HIGH if and only if both the inputs are low.

Chap 2


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SOL 2.3.49 Correct option is (A).When the no. of inputs in the XOR gate is even then output is ‘0’ and when the no. of inputs is odd then output is ‘1’.

SOL 2.3.50 Correct option is (B).NAND and NOR gates do not follow the associative property.

Now check for NOR gate, ( )A B C+ + is equal to or not equal to

( )A B C+ + .

or ( )A B C+ + ( )A B C! + +or ( )A B C+ + ( )A B C! + +


....A AB ABC ABCD ABCDE+ + + + +

( ...)A B BC BCD BCDE1= + + + + + ( )A X A1= + =


...A AB A BC A B CD+ + + + ( ...)A A B BC BCD= + + + + ( )A A X= + ( )( )A A A X= + + A X= + ...A B BC B CD= + + + + and so on.

...A B C= + + +

SOL 2.3.53 Correct option is (D).The number of combinations for five inputs is 2 325= = .





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SOL 2.3.57 Correct option is (C).Output of each option is(A) .Y 0 1 0= = (B) Y 0 1 1 0= + = =

(C) Y 0 1 0 1$= = = (D) Y 0 1 09= =




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eighth edition gate - 2018 · eighth edition gate ... gate multiple choice questions, ... ic logic...

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