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G12M - AM3894 Q7 CPU Module Hardware User Manual

iWave Systems Technologies Pvt. Ltd.


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Document Revision History

Revision Date Change Description

Author

1.0 14th Mar ‘12 Initial Release SVM

1.1 04th Sep ‘12 Updated Mechanical Dimensions section RD

PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do not read this document further if you are not the intended recipient. Any review, use, distribution or disclosure by others is strictly prohibited. If you are not the intended recipient (or authorized to receive for the recipient), you are hereby notified that any disclosure, copy or distribution or use of any of the information contained within this document is STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.”

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Table of Contents

1. INTRODUCTION .............................................................................................................. 6 1.1 Overview ......................................................................................................................................................... 6 1.2 Reference Documents ..................................................................................................................................... 6 1.3 Terminology .................................................................................................................................................... 7

2. AM3894 Q7 CPU MODULE ARCHITECTURE ...................................................................... 8 2.1 Features ........................................................................................................................................................... 9

3. FUNCTIONAL DESCRIPTION .......................................................................................... 11 3.1 AM3894 Q7 CPU Module .............................................................................................................................. 11 3.2 AM3894 Q7 CPU Module boot setting Description....................................................................................... 13

4. AM3894 Q7 CPU MODULE EXTERNAL INTERFACES ........................................................ 14 4.1 JTAG Connector ............................................................................................................................................. 14 4.2 Micro SD Connector ...................................................................................................................................... 15 4.3 Two 80 pin Expansion connector .................................................................................................................. 17 4.4 Expansion connector 1 .................................................................................................................................. 19 4.5 Expansion Connector 2 .................................................................................................................................. 20 4.6 Q7 Edge connector ........................................................................................................................................ 22 4.7 Board Edge Connector (PCB Edge TOP Side) ................................................................................................. 23 4.8 Board Edge Connector (PCB Edge BOTTOM Side) ......................................................................................... 28

5. POWER ON SEQUENCE ................................................................................................. 33

6. MATING CONNECTOR DETAILS ..................................................................................... 34 6.1 Edge Connector ............................................................................................................................................. 34 6.2 Expansion connectors ................................................................................................................................... 34

7. MECHANICAL DRAWING .............................................................................................. 35

8. ORDERING INFORMATION ........................................................................................... 39

9. TECHNICAL SUPPORT ................................................................................................... 40

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Table of Figures FIGURE 1: AM3894 Q7 MODULE BLOCK DIAGRAM .................................................................................. 8

FIGURE 2: AM3894 Q7 CPU MODULE TOP VIEW ................................................................................. 11

FIGURE 3: AM3894 Q7 CPU MODULE BOTTOM VIEW ............................................................................ 12

FIGURE 4: LOCATION OF JTAG CONNECTOR ............................................................................................ 14

FIGURE 5: LOCATION OF MICRO SD CONNECTOR ..................................................................................... 16

FIGURE 6: LOCATION OF EXPANSION CONNECTORS ................................................................................... 18

FIGURE 7: POWER ON SEQUENCE ......................................................................................................... 33

FIGURE 8: MECHANICAL DRAWING OF AM3894 Q7 CPU MODULE-TOP ................................................... 35

FIGURE 9: MECHANICAL DRAWING OF AM3894 Q7 CPU MODULE-BOTTOM ........................................... 36

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List of Tables TABLE 1: REFERENCES ........................................................................................................................... 6

TABLE 2: TERMINOLOGY ........................................................................................................................ 7

TABLE 3: BOOT MODE SETTINGS .......................................................................................................... 13

TABLE 4: JTAG HEADER PIN ASSIGNMENTS ............................................................................................ 15

TABLE 5: MICRO SD CONNECTOR PIN ASSIGNMENTS................................................................................ 17

TABLE 6: 80 PIN EXPANSION CONNECTOR 1 ............................................................................................ 19

TABLE 7: 80 PIN EXPANSION CONNECTOR 2 ............................................................................................ 20

TABLE 8: PCB EDGE TOP SIDE PIN ASSIGNMENTS ................................................................................... 23

TABLE 9: PCB EDGE BOTTOM SIDE PIN ASSIGNMENTS ........................................................................... 28

TABLE 10: MATING CONNECTOR FOR EDGE CONNECTOR ........................................................................... 34

TABLE 11: MATING CONNECTOR FOR EXPANSION CONNECTOR .................................................................... 34

TABLE 12: ORDERING INFORMATION ..................................................................................................... 39

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1. INTRODUCTION

1.1 Overview

AM3894 Q7 CPU Module offers Highly integrated, programmable platform that meets the processing needs of the application like Single-Board Computing, Network and Communications Processing, Industrial Automation, Human Machine Interface, and Interactive Point-of-Service Kiosks. Etc. The device combines. High performance ARM processing with highly integrated peripheral set The peripheral set includes HD video processing subsystem, two Gigabit Ethernet MAC’s(10/100/1000 Mbps) ,PCIe port x2 lane GEN 2 complaint interface etc. AM3894 Q7 CPU module allows customers to scale as needed across to TI Sitara, C6-Integra, and DaVinci brands while saving their investment since these device are pin-pin and software compatible. This manual provides a general module overview and description of components and basic operation of AM3894 Q7 CPU Module.

1.2 Reference Documents

Following documents have been referred while preparing the user manual

Table 1: References

Document Description

AM3894 Datasheet http://www.ti.com/lit/ds/symlink/am3892.pdf

AM3894 User Manual http://www.ti.com/lit/ug/sprugx7/sprugx7.pdf

Q7 R1.2 Specification http://www.secoqseven.com/website_objects/Qseven-Spec_1.20.pdf

Generic Q7 Development Kit http://www.iwavesystems.com/?q=node/147

http://www.ti.com/lit/ds/symlink/am3892.pdf

http://www.ti.com/lit/ug/sprugx7/sprugx7.pdf

http://www.secoqseven.com/website_objects/Qseven-Spec_1.20.pdf

http://www.secoqseven.com/website_objects/Qseven-Spec_1.20.pdf

http://www.iwavesystems.com/?q=node/147

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1.3 Terminology

The following is a list of commonly occurring acronyms and abbreviations used throughout this document.

Table 2: Terminology

Term Definition

CMOS Complementary metal oxide semiconductor

CPU Central Processing Unit

DDR3 Double Data Rate3

EMAC Ethernet MAC

GPIO General Purpose Input Output

GPMC General purpose memory controller

I2C Inter-IC bus

IO Input Output

JTAG Joint Test Action Group

LED Light Emitting Diode

LVDS Low voltage differential signal

MB Mega Byte

MAC Media Access Control

McASP Multi channel Audio Serial Port

NC No connection

OS Operating System

PCIe Peripheral component interconnect express

PCB Printed Circuit Board

PWM Pulse width modulation

RTC Real Time Clock

RX Receive

SPI Serial peripheral interface

SATA Serial Advanced Technology Attachment

SDRAM Synchronous Dynamic Random Access Memory

TX Transmit

TI Texas instrument

UART Universal Asynchronous Receiver/Transmitter

USB Universal Serial Bus

WD Watch dog

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2. AM3894 Q7 CPU MODULE ARCHITECTURE

This section is designed to provide the developer detailed information about the electronics design and practical considerations that went into the Q7 Module. This section describes the

high level block diagram and features of the processor.

Figure 1: AM3894 Q7 Module Block Diagram

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2.1 Features

The AM3894 CPU Module supports the following features:

TI ‘s Processor: AM3894 @ 1.2GHz

1GB DDR3 SDRAM

128MB NAND Flash

Micro SD Slot

JTAG for Debug

230 pin Edge connector

Expansion Connector-2Nos

5V, Input from carrier board

Typical power consumption:<5W

Form Factor: 70 mm x 70mm

Operating Temperature: 0C to +70°C

The following interfaces are supported through MXM edge connector o PCIE Lanes – 2

o SATA Channels – 2

o USB 2.0 HOST–4

o USB 2.0 Device – 1

o LVDS Channel – 1

o HDMI Port – 1

o Audio Port– 1

o 4-bit SD/SDIO – 1

o I2C Bus – 1

o SPI Bus – 1

o Watchdog Trigger – 1

o UART – 1

The following interfaces are supported through the expansion connectors. o Audio Ports – 2

o EMAC -1

o UART Ports – 3 (CMOS 3.3V IF)

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o GPIOs -13 No’s

o Analog video out Port

o Video IN port 0 – 16bit

o Video IN port 1 – 8bit

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3. Functional Description

3.1 AM3894 Q7 CPU Module

Top view of AM3894 Q7 CPU Module is shown in Figure 2

Figure 2: AM3894 Q7 CPU Module TOP view

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The bottom view of CPU module is as shown in Figure 3

Figure 3: AM3894 Q7 CPU Module Bottom view

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3.2 AM3894 Q7 CPU Module boot setting Description

3.2.1 Boot Setting Switch

The boot sequence is started automatically after each device-level global reset. Boot modes, pin configurations, and register configurations required for booting the device. In the Module Dip switch (SW1) is used for boot order selection between NAND Flash & SD card. Refer Table 3 for settings.

Table 3: Boot Mode Settings

SW1 Boot Device

ON SD

OFF NAND

Note: By default NAND boot mode is supported.

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4. AM3894 Q7 CPU Module External Interfaces

4.1 JTAG Connector

A 20pin 50mil pitch berg stick type connector is provided for processor JTAG interface for debugging/development purpose. The JTAG connector location is given below

Figure 4: Location of JTAG Connector

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The pin details of JTAG connector are given below.

Table 4: JTAG Header Pin Assignments

Pin No. Signal name IO Level Pin No. Signal name IO Level

1 TMS 3.3V 2 TRSTn 0V

3 TDI 3.3V 4 GND 0V

5 VCC_3V3 3.3V 6 NC -

7 TDO 3.3V 8 GND 0V

9 RTCK 3.3V 10 GND 0V

11 TCLK 3.3V 12 GND 0V

13 EMU0 3.3V 14 EMU1 3.3V

15 EMU_RSTn 3.3V 16 GND 0V

17 EMU2 3.3V 18 EMU3 3.3V

19 EMU4 3.3V 20 GND 0V

4.2 Micro SD Connector

Micro SD connector is provided for connecting the micro SD card for mass storage. Expandable up to 32GB and it can also be used for booting or for OS Storage.. The location of Micro SD connector is given in below figure.

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Figure 5: Location of Micro SD connector

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The pin details of micro SD connector is given below

Table 5: Micro SD Connector Pin Assignments

Pin No. Signal name

IO Level Pin No.

Signal name

IO Level

1 DAT2 3.3V 2 CD/DATA3 3.3V

3 CMD 3.3V 4 VDD 3.3V

5 CLK 3.3V 6 GND 0V

Note: The Micro SD signals are shared with MXM edge connector also

4.3 Two 80 pin Expansion connector

The CPU module supports two 80-pin Expansion connectors. These two connectors are used to bring out the interfaces of the processor which are not supported by the Q7 edge connector. The Expansion connector1 supports below interface

o Audio Port 0 (McASP0)– 1

o UART Ports – 3 (UART0 is full functioned)

o GPIOs -13 No’s

o Video Input port0 (16 bit)

o GP Timer

The expansion connector 2 supports below interface

o Audio Port 1 (McASP1)– 1

o EMAC1

o Analog Video out port

o Video Input port1 (8 bit)

Expansion connector Part No on the Q7 CPU Module is: DF17(2.0)-80DP-0.5V(57). The mating

part No is given in below Table 11

The expansion connector location is given in Figure 6

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Figure 6: Location of Expansion connectors

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The expansion connector pin assignments are given below

4.4 Expansion connector 1

Table 6: 80 pin Expansion Connector 1

Pin No Signal Name Pin No

Signal Name

1 GND 2 UART0_TXD

3 MCA0_AXR5 4 UART0_RXD

5 MCA0_AXR4 6 NC

7 MCA0_AXR3 8 MCA0_AFSR

9 MCA0_AXR2 10 MCA0_AHCLKR

11 MCA0_AXR1 12 MCA0_ACLKR

13 MCA0_AXR0 14 MCA0_ACLKX

15 GP0[24] 16 MCA0_AFSX

17 GP0[8] 18 MCA0_AHCLKX

19 TIM7_OUT 20 MCA0_AMUTE

21 GP0[15] 22 GP0[6]

23 GP1[29] 24 UART0_DSRn/GP1[17]

25 SATA_ACT1#/GP1[31] 26 UART0_CTSn/GP1[28]

27 GND 28 UART0_DCD/GP1[18]

29 UART0_RTSn/GP1[27] 30 UART0_DTRn/GP1[16]

31 GP0[26] 32 GND

33 VIN[0]A_D[9] 34 VIN[0]A_D[11]

35 VIN[0]A_D[10] 36 VIN[0]A_D[12]

37 GND 38 GP1[22]

39 GND 40 GP0[19]

41 GP0[27] 42 GND

43 UART0_RINn/GP1[19] 44 GND

45 VIN[0]A_D[13] 46 VIN[0]A_D[14]

47 VIN[0]A_D[15] 48 NC

49 GND 50 UART2_TXD

51 UART2_CTSn 52 UART2_RXD

53 UART2_RTSn 54 GND

55 GP1[20] 56 GP0[7]

57 GP1[21] 58 GP0[18]

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59 GND 60 UART1_RXD

61 UART1_CTSn 62 UART1_RTSn

63 UART1_TXD 64 NC

65 VIN[0]A_CLK 66 VIN[0]A_HSYNC

67 NC 68 VIN[0]A_VSYNC

69 VIN[0]A_D[0] 70 VIN[0]A_D[1]

71 VIN[0]A_D[2] 72 VIN[0]A_D[3]

73 VIN[0]A_D[4] 74 VIN[0]A_D[6

75 VIN[0]A_D[7] 76 VIN[0]A_D[5]

77 VIN[0]A_D[8] 78 NC

79 NC 80 GND

4.5 Expansion Connector 2

The expansion connector 2 (U18) pin assignment

Table 7: 80 pin Expansion Connector 2

Pin No Signal Name Pin No Signal Name

1 NC 2 NC

3 NC 4 NC

5 GND 6 GND

7 MCA1_AHCLKR 8 MCA1_ACLKR

9 MCA1_AHCLKX 10 MCA1_AMUTE

11 MCA1_ACLKX 12 MCA1_AFSR

13 MCA1_AXR1 14 MCA1_AFSX

15 GND 16 GND

17 EMAC1_RXER 18 EMAC1_TXD0

19 EMAC1_CRS 20 EMAC1_TXD1

21 EMAC1_RXD7 22 EMAC1_TXD2


25 EMAC1_COL 26 EMAC1_TXCLK

27 EMAC1_RXD1 28 EMAC1_RXD4


31 EMAC1_RXCLK 32 EMAC1_RXD6

33 GND 34 GND

35 EMAC1_TXEN 36 MDIO_MDIO

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37 EMAC1_TXD5 38 EMAC1_RXDV

39 EMAC1_TXD7 40 EMAC1_RXD2

41 MCA1_AXR0 42 EMAC1_RXD0

43 EMAC1_TXD4 44 EMAC1_GMTCLK

45 MDIO_MDCLK 46 GND

47 GND 48 VIN[1]A_D[1]

49 VIN[1]A_D[0] 50 VIN[1]A_D[3]

51 VIN[1]A_D[2] 52 VIN[1]A_D[5]

53 VIN[1]A_D[4] 54 VIN[1]A_D[6]

55 VIN[1]A_D[7] 56 VIN[1]A_HSYNC

57 VIN[1]A_VSYNC 58 VIN[1]A_CLK

59 GND 60 GND

61 IOUTF 62 IOUTC

63 NC 64 GND

65 IOUTE 66 IOUTA

67 NC 68 GND

69 IOUTD 70 IOUTB

71 NC 72 GND

73 IOUTG 74 NC

75 RFOUT 76 NC

77 GND 78 GND

79 NC 80 NC

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4.6 Q7 Edge connector

The processor standard IO interfaces are taken through the PCB edge connector as per Q7 R1.20 specification. It is a two row with 230 fingers in PCB. The mating connector will be a female 230-pin MXM connector. The following interfaces are supported through MXM edge connector

o PCIE Lanes – 2

o SATA Channels – 2

o USB 2.0 HOST–4

o USB 2.0 Device – 1

o LVDS Channels – 1

o HDMI Port – 1

o Audio Port– 1

o 4-bit SD/SDIO – 1

o I2C Bus – 1

o SPI Bus – 1

o Watchdog Trigger – 1

o UART – 1

o RESET

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Board Edge connector pin assignments are given below

4.7 Board Edge Connector (PCB Edge TOP Side)

Table 8: PCB Edge TOP Side Pin Assignments

Pin No Signal Name

Direction w.r.t CPU Module

Description

1 GND

3 NC

5 NC

7 NC

9 NC

11 NC

13 NC

15 NC

17 WAKE#/ GP0[4]

Input Optional GP0[4] from processor is connected

19 NC

21 NC

23 GND

25 GND

27 NC

29 SATA0_TXP Output SATA0 Transmitter pair

31 SATA0_TXN Output

33 SATA_ACT# Output SATA0 Activity Indicator

35 SATA0_RXP Input SATA0 Receiver pair

37 SATA0_RXN Input

39 GND

41 NC

43 SD_CD Input SD Card detect input (used with on board Micro SD)

45 SD_CMD Input/Output SD command output (used with on board Micro SD)

47 SD_POW Output SD card power enable

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output

49 SD_DATA0 Input/output SD Data0 (Used with onboard Micro SD)

51 SD_DATA2 Input/output SD Data2 (Used with onboard Micro SD)

53 NC

55 NC

57 GND

59 MCA[2]_AFSX Output McASP2 Transmit Frame Sync I/O

61 RESET OUT Output Processor Reset out signal

63 MCA[2]_ACLKX Output McASP2 Transmit Bit Clock I/O

65 MCA[2]_AXR[1] Input McASP2 Receive Data

67 MCA[2]_AXR[0] Output McASP2 Transmit Data

69 NC

71 NC

73 GND

75 NC

77 NC

79 NC

81 NC

83 NC

85 USB_2_3_OC# Input Over current detect input2. This pin is used to monitor the USB power over current of the USB Ports 2 and 3.

87 USB_P3- Input/output Universal Serial Bus Port 3 differential pair.. 89 USB_P3+ Input/output

91 USB_CC Input By Default Not Connected. Connected to GPIO (GP1[10])

93 USB_P1- (Client) Input/output Universal Serial Bus Port 1

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95 USB_P1+ (Client) Input/output differential pair. This port may be optionally used as USB client port.

97 GND

99 LVDS_A0+ Output LVDS primary channel differential pair 0. 101 LVDS_A0- Output



111 LVDS_PPEN Output LCD panel power enable. Connected to GPIO. (GP1[11])


117 GND

119 LVDS_A_CLK+ Output LVDS primary channel differential pair Clock lines.

121 LVDS_A_CLK- Output

123 TIM4_OUT Output Connected to processor TIM4_OUT.

125 LVDS_DID_DAT Input/output I2C1 Clock I/O

127 LVDS_DID_CLK Input/output I2C1 Data I/O

129 NC

131 HDMI_TMDSCLKP Output

HDMI Clock Output 133 HDMI_TMDSCLKN Output

135 GND

137 HDMI_TMDSDP1 Output HDMI Data 1 output

139 HDMI_TMDSDN1 Output

141 GND



147 GND



153 HDMI_HPDET Input HDMI Hot Plug Detect

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Input. Signals the Connection / removal of an HDMI cable.

155 PCIE_CLK_REF+ Output PCI Express Reference Clock. (100MHz LVDS)

157 PCIE_CLK_REF- Output

159 GND

161 NC

163 NC

165 GND

167 NC

169 NC

171 NC

173 PCIE_TXP1 Output PCIE Transmit Data Lane 1

175 PCIE_TXN1 Output

177 NC

179 PCIE_TXP0 Output PCIE Transmit Data Lane 0

181 PCIE_TXN0 Output

183 GND

185 NC - Optional GPIO (GP0[21]) connected

187 NC

189 NC

191 NC

193 VCC_RTC Input RTC Backup supply(3V)

195 TIM7_OUT Output By default Not Connected. Connected to Processor TIM7_OUT

197 GND

199 SPI_MOSI Output SPI Data SPI_D[1]

201 SPI_MISO Input SPI Data SPI_D[0]

203 SPI_SCK Output SPI Clock I/O

205 NC

207 NC/TCLK Input By Default Not connected. Connected to Processor JTAG test clock input

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209 UART0_TX/TDO Output By Default UART2 TX pin connected /JTAG test port data output

211 VCC_5V Input

5V Input

213 VCC_5V Input

215 VCC_5V Input

217 VCC_5V Input

219 VCC_5V Input

221 VCC_5V Input

223 VCC_5V Input

225 VCC_5V Input

227 VCC_5V Input

229 VCC_5V Input

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4.8 Board Edge Connector (PCB Edge BOTTOM Side)

Table 9: PCB Edge BOTTOM Side Pin Assignments

Pin No Signal Name

Direction w.r.t CPU module

Description

2 GND

4 NC

6 NC

8 NC

10 NC

12 NC

14 NC

16 SUS_S5# Output Connected to 3.3V via 10K pull up. Can be used for enabling Carrier card power

18 SUS_S3# Output Connected to 3.3V via 10K pull up. Can be used for enabling Carrier card power.

20 NC

22 NC

24 GND

26 PWRGIN Input Optional (Can be used to power on the CPU Module)

28 RSTBTN# Input Reset Button Input

30 SATA1_TXP Output SATA1 Transmit pair

32 SATA1_TXN Output

34 GND

36 SATA1_RXP Input SATA1 Receive pair

38 SATA1_RXN Input

40 GND

42 SD_CLK Output SD Clock output (Used with onboard Micro

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SD)

44 SD_LED Output Connected to GPIO(GP0[5])

46 SD_WP Input SD Card Write Protect input

48 SD_DAT1 Input/output SD Data1 (Used with onboard Micro SD)

50 SD_DAT3 Input/output SD Data3 (Used with onboard Micro SD)

52 NC

54 NC

56 RSVD/GPIO By default not used connected to Optional GPIO (GP0[22)

58 GND

60 NC

62 NC

64 NC

66 I2C0_CLK Input/output I2C0 Clock I/O

68 I2C0_DAT Input/output I2C0 Data I/O

70 WDTRIG# Input Connected to GPIO (GP0[25])

72 WDOUT

74 GND

76 NC

78 NC

80 USB_4_5_OC# Input Over current detect input 3. This pin is used to monitor the USB power over current of the USB Ports 4

82 USB_P4- Input/output Universal Serial Bus Port 4 differential pair. 84 USB_P4+ Input/output

86 USB_0_1_OC# Input Over current detect input

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1. This pin is used to monitor the USB power over current of the USB Ports 0 and 1.


92 USB_ID Input By Default Not used. Connected to GPIO (GP1[9])


98 GND

100 NC

102 NC

104 NC

106 NC

108 NC

110 NC

112 LVDS_BLEN Output LCD panel Backlight enable. Connected to GPIO. (GP1[12])

114 NC

116 NC

118 GND

120 NC

122 NC

124 RSVD/GPIO By default Not connected .Optional GPIO (GP0[23])

126 LVDS_BLC_DAT Input/output I2C1 Clock I/O

128 LVDS_BLC_CLK Input/output I2C1 Data I/O

130 NC

132 NC

134 NC

136 GND

138 NC

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140 NC

142 GND

144 NC

146 NC

148 GND

150 HDMI_SDA Input/output HDMI I2C Serial Data I/O

152 HDMI_SCL Output

154 NC

156 PCIE_WAKE#(GPIO) By default Not connected. PCI Express Wake Event. Connected to GPIO (GP1[14])

158 PCIE_RST# Output Processor Reset out signal

160 GND

162 NC

164 NC

166 GND

168 NC

170 NC

172 NC

174 PCIE_RXP1 Input PCIE Receive Data Lane 1

176 PCIE_RXN1 Input

178 NC

180 PCIE_RXP0 Input PCIE Receive Data Lane 0

182 PCIE_RXN0 Input

184 GND

186 NC

188 NC NC NC

190 NC NC NC

192 NC NC NC

194 TIM6_OUT Output Connected to Processor TIM6_OUT

196 TIM5_OUT Output Connected to Processor TIM5_OUT

198 GND

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200 SPI_CS0# Output SPI Chip Select 0

202 SPI_CS1# Output SPI Chip Select 1

204 NC/TRSTn Input By Default Not connected. Connected to Processor JTAG test reset input

206 NC

208 UART0_RX/TDI Input By Default UART2 RX pin connected /JTAG test data input

210 NC/TMS Input By Default Not connected. Connected to Processor JTAG test port mode select input

212 VCC_5V Input

5V Input

214 VCC_5V Input

216 VCC_5V Input

218 VCC_5V Input

220 VCC_5V Input

221 VCC_5V Input

222 VCC_5V Input

224 VCC_5V Input

226 VCC_5V Input

228 VCC_5V Input

230 VCC_5V Input

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5. Power ON sequence

Main power input: Typically 5V @1A is required for the Q7 module All Carrier card/Main Board peripheral power supplies should be powered ON only after the CPU Module is powered ON completely. i.e after SUS3_# signal is driven high. This is sequence is not as per Q7 standards but as per TI processor requirement since processor pins are not fail-safe. VCC _5V input is given from the edge connector to the CPU module, then all other voltages generated in the Q7 module. After all the CPU voltages are stable, then SUS3_# is driven high to enable the carrier board power. The PCIe reset out signal is driven by Q7 module to various devices on board through optional buffer. This reset out signal remains asserted until all the supplies on Q7 module and carrier card are stable.

Refer the below power on sequence diagram.

Figure 7: Power ON sequence

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6. Mating Connector Details

6.1 Edge Connector

The following connector can be used as a mating connector for the edge connector on the carrier card.

Table 10: Mating connector for Edge Connector

Manufacturer Part Number Specification Stacking Height

MXM connector Height

ACES 88882-2D0K MXM 230 pins 0.5 mm pitch Edge Card connector SMT R/A STD

5.0mm 7.5mm

Foxconn AS0B326-S78N-7F MXM 230 pins 0.5 mm pitch Edge Card connector SMT R/A STD

5.0mm 7.8mm

Carrier board component placement below the Q7 CPU module is only permitted when using a MXM connector with a resulting height between carrier board and Q7 CPU module of 5.0mm and no carrier board component shall exceed a height of 2.2mm+/-0.1 Using carrier board topside components up to 2.2mm allows a gap of 0.3mm between carrier board topside components and the Q7 CPU module bottom side components. This may not be sufficient in some situations. In carrier board applications in which vibration or board flex is a concern, then the carrier board component height should be restricted to a value less than 2.2mm that yields a clearance that is sufficient for the application

6.2 Expansion connectors

The following connector can be used as a mating connector for the expansion connector on the carrier card.

Table 11: Mating connector for expansion connector

Manufacturer Part Number Specification Stacking Height Connector Height

Hirose Electric Co Ltd

DF17(3.0)-80DS-0.5V(57)

80 pin 0.5mm pitch SMD W/FT

5mm 3.5mm

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7. Mechanical Drawing

The mechanical drawing of the AM3894 Q7 CPU Module is shown in Figure 8

Figure 8: Mechanical Drawing of AM3894 Q7 CPU Module-TOP

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Figure 9: Mechanical Drawing of AM3894 Q7 CPU Module-BOTTOM

Please contact iWave for 3D & 2D files of AM3894 Q7 CPU module.

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Below figures shows the mechanical spec of Q7 CPU modules. For more information refer Qseven spec 1.20 “Qseven-Spec_1.20.pdf”

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8. Ordering Information

Table 12: Ordering Information

Part Number Temp. Range Specification

iW-G12M-Q7XXC 0C to +70C AM3894 @ 1.2GHz 1GB DDR3 SDRAM 128MB NAND Flash Micro SD Connector Processor JTAG XX- No OS /OS is customer specific

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9. Technical Support

iWave Systems Technologies Pvt. Ltd. # 7/B, 29th Main, BTM Layout 2nd Stage, Ban galore - 560 076 Phone : +91-80-26683700, 26786245 Fax : +91-80-26685200 Email :[email protected] Web : www.iwavesystems.com

mailto:[email protected]

http://www.iwavesystems.com/