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CASS: 2013-2014 DLP Program UT Austin

Fundamentals on ContinuousFundamentals on Continuous--TimeTimeFundamentals on ContinuousFundamentals on Continuous Time Time SigmaSigma--Delta ModulatorsDelta Modulators

DLP Series, sponsored by the CASSDLP Series, sponsored by the CASS

Jose SilvaJose Silva--MartinezMartinezAmesp02.tamu.edu/~jsilvap / j

[email protected] of ECE

Texas A&M Universitye as & U e s ty

September 19, 2013

- 1 -J. Silva-Martinez


Outline Introduction Fundamentals of Sigma-Delta Modulators

Stability Clock Jitter Blockers Tolerance

Quantizer Issues Voltage Mode versus Current Mode

Improving blocker tolerancep g Efficient non-invasive filtering Saturation detector

Current Research Projects Current Research Projects TAMU: Where we are? Conclusions



Introduction: ConnectivityWLANWLAN

UWB, 802.15.3a

WI-FIMAN

Wi-Max, 802.16a,e

GPS

802.16a,e

BLUETOOTH

Connectivity to EVERYTHING

PAN, 802.15BLUETOOTH

Increasing number of wireless standards

Support of multiple-standards on the same chip


Advances in Integrated RF design towards universal devices

Software Radio: easy addition of new standards


Direct Conversion Multi-Standard Receiver

System issues in broadband systems:High frequency filtering is especially critical in broadband applicationsRejection of Blockers: ADC filtering must be complemented by LP filteringRejection of Blockers: ADC filtering must be complemented by LP filteringNeighbor channels are quite relevant even if heavy filtering is used

Trade‐offs:


Light filtering in front demands an ADC with higher SNR and higher SDRHigher SNDR‐ADC implies more power and more circuit complexity


State of the artState of the art

1.E+06

1.E+07ISSCC 2010ISSCC 1997-2009VLSI 1997 2009

State of the artState of the arts)

1 E+03

1.E+04

1.E+05VLSI 1997-2009FOM=100fJ/conv-stepFOM=10fJ/conv-step

10mW @10MHz10mW @10MHzs(p

Joul

es

1.E+01

1.E+02

1.E+03

VideoVideo

10mW @10MHz10mW @10MHz

Pow

er/f

s

1.E-01

1.E+00

10 20 30 40 50 60 70 80 90 100 110 120

VideoVideo

B. Murmann, http://www.stanford.edu/~murmann/adcsurvey.html.SNDR (dB)SNDR (dB)

Challenge 1: Jitter Tolerance


Challenge 1: Jitter Tolerance


Challenge 2: Co-existenceSimultaneous Usage of Radio Bands

Bm

)Po

wer

(dB

Outpu

t

(G )

RF Interference: Frequency Overlap, O t f B d E i i R i S t ti

* Plot courtesy of Camille Chen/IntelFrequency (GHz)


Out‐of‐Band Emissions, Receiver Saturation


SigmaSigma--Delta Modulators:Delta Modulators:

Practical Design IssuesPractical Design Issues



Conventional (Conventional (NyquistNyquist) ADC) ADC

SQNR=6 02*n+1 76SQNR=6 02*n+1 76


SQNR=6.02*n+1.76SQNR=6.02*n+1.76


Basic concepts in Basic concepts in ModulatorsModulators

Vin

T 1H(s) A/D

Data Out

DACs

s FT

)s(HSTF NTF

1


)s(H1 )s(HNTF

1


Fundamentals of Oversampled A/D ConversionFundamentals of Oversampled A/D ConversionqEFilter

1

1

1

ZZ

q

ZY ZX

Filter

Ch k th i t t t t j t i

DAC

11 2221

T

eeeeZzH

T

TjTjTjTje

Check the input-output trajectoriesOriginal E(z) is shaped by NTF

O i i l E( ) i Spot SQNR

222 TsinjezH

Tj

e Original E(z) is

amplified here!

21

zHzEZzXSQNR

Spot SQNR

22 TsinzHe

2

2 1

T*zEzXSQNR

zHzE e


2

2

TsinzE


Oversampled A/D Conversion Oversampled A/D Conversion qEFilter

OSR***.SQNR N2

32 31251

1

1

1

ZZ

q

ZY ZX

DAC

Filter

Si l t Q ti ti 221 zXZzX

SQNR

dBOSRlog*.N*..SQNR 103025026761 DAC

Signal to Quantization

Noise Ratio (SQNR)

0

2

0

2 dfzHzEdfzHzESQNR

f

e

f

e

bb

N=number of bits

OSR=fs/2fb

SQNR improves by 30dB when

0

2

2

22

1

thffbIf

dfTsin*

zEzXSQNR

f b

SQNR improves by 30dB when

OSR increases by 10

Or 9dB SQNR improvement

2

3

2

2

26

2

212

21

f*f

f**

V

VSQNR

then,fsfbIf

S

b

Sq

N


when doubling OSR

2

32 31251

212

OSR***.SQNR

ff

*V

N

S

S

q


System Design ConsiderationsSystem Design Considerations

150

B) Filter order=5Dashed lines are for 2 bit quantizer

125

e R

atio

(dB

Filter order=4Quantizer Bits=1

Quantizer Bits=1Dashed lines are for 2-bit quantizerDashed=Solid+6.02

75

100

tion

Noi

se


Q

50

o Q

uant

iza


0

25

Sign

al to


0

0 10 20 30 40

Oversampling Ratio (OSR)


Design Considerations: 3Design Considerations: 3rdrd order looporder loop

20

) 3rd order loop

16

18

ts (E

NO

B)

4-bit quantizer

3-bit quantizer

3rd order loop

12

14

ber o

f Bit 3-bit quantizer

1-bit Quantizer

8

10

tive

Num

b

2-bit Quantizer

761)dB(SNDR

4

6

Effe

ct

02.676.1)dB(SNDRENOB


4 8 12 16 20 24 28 32 36 40

Oversampling Ratio (OSR)


Oversampled A/D ConversionOversampled A/D ConversionFeedforwardFeedforward Architecture Architecture

Eq stands for the quantization noise

Ed stands for DAC non-idealities (jitter + thermal noise) Ed stands for DAC non idealities (jitter + thermal noise)

Filter’s thermal noise is accounted in Eh

The modulator’s output becomes

E*NTFEEX*STFY sZOH*sH

The error signal (Filter’s input) is qhd E*NTFEEX*STFY

1

1

1

Z*sZOH*sHSTF

1


11

Z*sZOH*sHNTF qhde E*ZEEXZOH)s(H*NTFV 1


Oversampled A/D Conversion: EffectsOversampled A/D Conversion: Effects of ZOHof ZOH

S

Tj

TzPhaseeZ S

1

Notice that

S

fdB

0

‐5

0

fi

SffcsinfZOH

dB

‐15

‐10

‐5

‐20

‐15

‐10

S

Sff

sin

f

fcsin

1 dB4 dB

‐30

‐25

‐20

‐30

‐25

20

Sf

f20 dB


0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10.1 1

Sf

f


Stability Issues:Stability Issues: ModulatorsModulators NotNot very difficult to stabilize the loop if very difficult to stabilize the loop if

the unity gain frequency is below Fs/4! the unity gain frequency is below Fs/4! (not very Low OSR); e.g. around (not very Low OSR); e.g. around 100Mhz if clock frequency is 400MHz100Mhz if clock frequency is 400MHz

NoticeNotice that larger OSR allow you to that larger OSR allow you to reduce the filter gain at highreduce the filter gain at high--frequency frequency

OutOut ofof Band noise is distributedBand noise is distributed inin OutOut--ofof--Band noise is distributedBand noise is distributed in in wider bandwidth, hence smaller noise wider bandwidth, hence smaller noise density but same integrated noisedensity but same integrated noise

ADC

Freq0

L(f)

fH

H(f) fS0.5fS

Loop Hard toHard toL(f)

2

3

Loop Phase

Hard to Hard to implement H(s) implement H(s)

SplitSplit the filter in the filter in 2 parts2 parts


Sf

f2

22 parts2 parts

Loop filter and Loop filter and fast pathfast path


Effect of the blockersEffect of the blockers on loop operationon loop operation Remarks on Filter’s operation: Filter’s input signalRemarks on Filter’s operation: Filter’s input signal

E*ZEEXV

qhde

1

sLe

1

X(f)

InbandInband signal is usually very small: Nice propertysignal is usually very small: Nice property

ADC

H(f)

1/(1+L) InbandInband signal is usually very small: Nice propertysignal is usually very small: Nice property

TransitionTransition band is more critical for filter’s linearity band is more critical for filter’s linearity (neighbor channels); (neighbor channels);

Filter must be designed for the blockersFilter must be designed for the blockers

0 dBFsNTF Freq

( )


Blocker tolerance is a major issue in broadband Blocker tolerance is a major issue in broadband applications (LTE)applications (LTE)

ZOH(f)


System Optimization: Tuning Filter ParametersSystem Optimization: Tuning Filter Parameters

Input Signature

Amplitude/Phase Comparators Filter tuning

schemeFilter tuning scheme

Calibration Algorithm

l

ADC

DAC

cal

op

cal

High-Order LP Filter

DAC

0 f0f

Effect of PVT VariationsEffect of PVT Variations FilterFilter TuningTuning;; reconfigurationreconfiguration oror

Calibration of (standalone) building blocks:Calibration of (standalone) building blocks:Does not guarantee loop stability (excess loop delay)Does not guarantee loop stability (excess loop delay)

MasterMaster slaveslave techniquestechniques couldcould bebe usedused


Does not guarantee loop stability (excess loop delay) Does not guarantee loop stability (excess loop delay) Does notDoes not guarantee best NTF (Coefficient adjustments)guarantee best NTF (Coefficient adjustments)


System Optimization: Global Tuning SchemeSystem Optimization: Global Tuning Scheme

Linear model Linear model used to findused to findused to findused to findNTFNTF

Model used to Model used to calibrate NTFcalibrate NTFcalibrate NTFcalibrate NTF

Loop response Loop response to calibration to calibration tones istones istones is tones is analyzed in analyzed in digital domaindigital domain


F. Silva-Rivas, et. al., “Digital Based Calibration Technique for Continuous-Time Bandpass Sigma-Delta Analog-to-Digital Converters,” Analog Integrated Circuits and Signal Processing, April-09.

C.Y. Lu, et. al., “A Sixth-Order 200MHz IF Bandpass Sigma-Delta Modulator With over 68dB SNDRin 10MHz Bandwidth,” IEEE J. Solid-State Circuits, June 2010.


Global Tuning Scheme for NTF Parameters: Global Tuning Scheme for NTF Parameters: DigitalDigital

A set of strategic tones are usedA set of strategic tones are used to optimize:Loop StabilityBest NTF


Bandwidth


Digitally assisted calibration schemeDigitally assisted calibration scheme

f

Test Tones

N-channel

Wideband Programmable Filter

Dout

Quantizer

-1/2Vi

Calibration

ff0

Freq calibration

Software Platform

N channel digital

receiver

z-1/2

Programmablez-1/2

Vin

Filter's control

DSPNRZ DACArray of DACs

DACs Control

Calibration Algorithm

Data control


A 6th-Order 200MHz IF Bandpass Sigma-Delta Modulator With over 68dB SNDR in 10MHz Bandwidth, C.Y. Lu, et.al., IEEE J. Solid-State Circuits, June 2010.


ADC Calibration: Experimental resultsADC Calibration: Experimental results



Design Examples



ADC Architecture Employing a TDC as ADC Architecture Employing a TDC as QuantizerQuantizerQQ

Dout

P(t)

Conventional Time domain Quantizer-DAC

• Multi-level quantizer and Digital to Analog Converter (DAC) are replaced by PWM generator and Time to Digtal Converter (TDC)

• Width of p(t) is proportional to the amplitude of the signal in a given• Width of p(t) is proportional to the amplitude of the signal in a given clock period

• Output code (Dout) represents “quantized pulse” edges with a


quantization step size = TQ

ISSCCISSCC--09, JSSC09, JSSC--2011 (March)2011 (March)


Output Spectrum: Output Spectrum: --5dB Input5dB Input

Output spectrum for 5dB 4MHzfor -5dB 4MHzInput signal

• SNR=62dB• SNR=62dB • THD=-65dB



Second ADC:Second ADC:System Architecture:System Architecture: Injection LockingInjection LockingSystem Architecture: System Architecture: Injection LockingInjection Locking

Φ1

Φ2

Φ3

RF

RQ

C C C

RC

5th d 3 bitOUT Φ4

Φ5

Φ6

Φ

+-

+-

RF

RF

RQ

C C

C C+- +

-

RF

Rin

Rin

OUTBP

OUTLP+-

RgC

C

+-

Rg

RC

IN IN• 5th-order 3-bit feedforward architecture

b5 3-Bit Two-StepQuantizer

Vin

Di it lBP

LP

2nd-Order Filter

Φ7

T s0

T s/7

2Ts/7

3Ts/7

4Ts/7

5Ts/7

6Ts/7

+-

BP

LP

2nd-Order Filter LP

1st-Order

• Local feedback is to compensate the excess loop delay

b1

b2

b4

Σb3

DigitalOutput

3-Bit NRZ DAC

Complementary Injection-4

excess loop delay

• LC-VCO+CILFD are used to generate

Level-to-PWM

VCO

1-B

it PW

M D

AC

Complementary InjectionLocked Frequency Divider

Programmable Delay

CILFD

gclean reference clocks


Converter11

“25MHz Bandwidth (BW) Continuous-Time Lowpass ΣΔ Modulator with Time-Domain3-bit Quantizer and DAC” Cho-Ying Lu, et.al., Sept 2010, JSSC


33--bit Algorithmic bit Algorithmic QuantizerQuantizer

The output is composed by 1 MSB + 3LSB+ 3LSB The MSB is determined first



LCLC--VCO + CILFDVCO + CILFDb5Vin 2nd-Order + 2nd-Order 1st-Order

b1

b2

b4

b5

Σb3

VCO

3-Bit Two-StepQuantizer

Vin

DigitalOutput

3-Bit NRZ DAC

BPFilter

Complementary Injection-Locked Frequency Divider

-BP

Filter

4

LP

Level-to-PWM Converter

VCO

Programmable Delay

11

CILFD

Ph i f VCO iPh i f VCO i 119dB /H @ 1MH119dB /H @ 1MH Jitter among phases


Phase noise of VCO is Phase noise of VCO is --119dBc/Hz @ 1MHz119dBc/Hz @ 1MHz CILFD phase noise is CILFD phase noise is --136dBc/Hz @ 1MHz136dBc/Hz @ 1MHz

Jitter among phases is highly correlated


Output Spectrum of the Modulator-2.2dBFS @ 5.08MHz

Peak SNR= 68.5dB @25MHz BW@ Peak SNDR= 67.7dB @25MHz BW SFDR>70dB



*Current-mode Quantizer

C. J. Park, **M. Onabajo, H. M. Geddada, J. Silva-Martinez, and A. I. KarsilayanMartinez, and A. I. Karsilayan

Paper under evaluation

*Partially sponsor by SRCPartially sponsor by SRC

** Currently with Northeastern University



Typical Typical QuantizerQuantizer: : Flash Flash ArchitectureArchitectureypyp QQ S/H operates at clock rate

Huge input capacitance if N>6 Huge input capacitance if N>6Kick back noise

Requires a precise low- Requires a precise lowimpedance resistive ladder: Power-accuracy-Speed tradeoff

Limited by comparatorSpeed and accuracyOff t ltOffset voltage

Hard to improve its resolution


State of the art: State of the art: ~ >2.4 ~ >2.4 GS/s 6 bits resolution GS/s 6 bits resolution


Conventional ADC ArchitectureConventional ADC Architecture

A CTSD modulator with feed-forward (FF) compensation. Summing Stage + Quantizer

DA

C2

DA

C1

Summing stage and quantizer in the conventional continuous- Summing stage and quantizer in the conventional continuoustime sigma-delta modulator with feed-forward compensation.

Excess loop delay (in addition to z-1) should be minimized. The direct path around the quantizer should be very fast


The direct path around the quantizer should be very fast. The summing amplifier must have a high unity-gain frequency.


Voltage Mode Voltage Mode QuantizerQuantizer

Performance summary of prior Adder-Quantizer in CT ΣΔ Modulators

Flash ADC architecture generally achieve the highest sampling rate and is usedas integrated quantizers in sigma-delta modulator

[23] [29] Technology

(nm) 180nm CMOS 180nm CMOS

Supply voltage 1.8V 1.8V

QuantizerQuantizer Resolution 3 bits 4 bits

Sampling rate 400MHz 800MHz

Input range 400mVpp 3Vpp

PowerAdder* 10mW Adder* 8.5mW

* Power consumption of the summing amplifier only.** 3-bit two-step Flash ADC.

[23] C.-Y. Lu, M. Onabajo, V. Gadde, Y.-C. Lo, H.-P. Chen, V. Periasamy, and J. Silva-Martinez, “A 25MHz bandwidth 5th-ordercontinuous-time lowpass sigma-delta modulator with 67 7dB SNDR using time-domain quantization and feedback ” IEEE J Solid-State

Power Flash ADC** 24mW Flash ADC N/A

continuous time lowpass sigma delta modulator with 67.7dB SNDR using time domain quantization and feedback, IEEE J. Solid StateCircuits, vol. 45, no. 9, pp. 1795-1808, Sep. 2010.[29] V. Singh, N. Krishnapura, S. Pavan, B. Vigraham, D. Behera, and N. Nigania, “A 16MHz BW 75dB DR CT ΣΔ ADC compensated formore than one cycle excess loop delay,” IEEE J. Solid-State Circuits, vol. 47, no. 8 pp. 1884-1895, Aug. 2012.

Demand for low power consumption


p p

Make the architecture robust to process-voltage-temperature (PVT) variations


Conventional VoltageConventional Voltage--Mode Summing and Flash ADCMode Summing and Flash ADC

12

14

16

mS)

CL=50fFCL=100fFCL=150fFCL=200fF

4

6

8

10

Tran

scon

duct

ance

(m

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

2

4

Beta

The loop gain is determined by the resistive feedback as well as the load TheThe minimumminimum transconductancetransconductance requiredrequired

AVloop ωGm

1RF

RLeq1 sRLeq CL

The loop gain is determined by the resistive feedback as well as the loadcapacitance.

RFF1 RFF2 … RFF RFRF

Th f th i lifi t DAC t i th

TheThe minimumminimum transconductancetransconductance requiredrequiredisis usuallyusually dictateddictated byby thethe valuevalue ofof DCDC looploopgaingain requirementrequirement

The response of the summing amplifier to a DAC step requires more thanfive loop time constants for a settling accuracy of 0.5%.

GBWGm

1RF AV DC 4

AsAs anan example,example, thethe casecase ofof 2626dBdB DCDC looploopgaingain withwith RRFFFF11||||....||R||RFFNFFN ==500500ΩΩ demandsdemands


GBW FCL

_

RLeq CL Tclk /2gg FFFF11|||| |||| FFNFFNGGmm>>4040mA/VmA/V


Conventional VoltageConventional Voltage--Mode Flash ADCMode Flash ADC

Conventional 3-bit voltage-mode flash ADC

The input signal (Vin) iscompared to seven referencevoltage levels using sevencomparators followed by latches.

To minimize the impact of PVT, large area resistors (R) and intricatelayout matching techniques are required

To minimize the effects of the kickback noise relative small values are

Larger transistor dimensions would be counterproductive with regards tothe maximum achievable speed


To minimize the effects of the kickback noise, relative small values arepreferred for the resistors (R) at the expense of larger static powerconsumption


Proposed CurrentProposed Current--Mode Flash Mode Flash ADC Architecture ADC Architecture

Incoming signals are added at the source of a common-gate stage

Input signals are replicated through NMOS current mirrors and compared with reference currents at high impedance nodeswith reference currents at high impedance nodes

The difference between input signal replicas and reference currents are converted to voltages at high impedance nodes


The different voltages are processed by seven comparator-latch combinations


CurrentCurrent--Mode AdderMode Adder--QuantizerQuantizer Minimum input impedance

Easy to interface it with loop filter and easy to implement the addition of filter coefficients

Two relevant parasitic poles limit its frequency response: Still can operate at GHz Resolution is limited by current mirror mismatches

Main design challenges:

Iq_REF1+IDC

VDD

Iq_REF2+IDC Iq_REF7+IDC

IBIAS2VBP0 VBP1

MP1 MP2 MP7MP0

Freset

Fsampleq1

Freset

Fsampleq2

Freset

Fsampleq7

VBP2

+-AV(s)

VCM

MXMCP1 MCP2 MCP7

MCP0B1 B2 B7

RFF1

RFF2

VFF1

V Comparator & Latch

VDD/2

Yout1

VDD/2

Comparator & Latch Yout2

VDD/2

Comparator & Latch Yout7

+CM

VBN2

MCN1 MCN1 MCN1MCN1MCN0

A

RFFN

VFF2

VFFN

IIn_AC


IBIAS1 IIn_AC+IDC IIn_AC+IDC IIn_AC+IDC IIn_AC+IDC

VBN1

VBN2

IDC=IIBIAS2-IIBIAS1

MN1 MN1 MN1MN1MN0

IDAC2

37


VoltageVoltage--Mode Summing Mode Summing vs. Currentvs. Current--Mode SummingMode Summing

Table II. Voltage-Mode Summing vs. Current-Mode Summing.

Voltage-Mode Current-Mode

vs. Currentvs. Current Mode SummingMode Summing

Voltage Mode Summing

Current ModeSumming

Technology (nm) 90nm CMOS 90nm CMOS Power Consumption(mW) 6.6mW* 3.1mW**

Input referred integrated noise 31 2 V 39 Vp g(in 20MHz) 31.2µV 39µV

Delay (@VLSB/4) 0.396ns 0.35ns * Power consumption of the summing amplifier only. ** Power consumption includes common-gate (CG) stage, Gm-boosting block and current

The most remarkable advantages of the Current-Mode approach: Superior performance with <50% power consumption. L ili

mirroring stages.

Less silicon area

In the Voltage-Mode case: Additional power should be added to account for the reference voltages generator


voltages generatorThe dual differential pair required at the input of each comparator.


Chip MicrophotographChip Microphotograph

The ADC area including bias gcircuitry: 0.0276mm2

The thermometer-to-binary encoder: 0.0072mm2.

m

Decoupling Capacitor

ESDESDESD ESD ESD

0.23mm

0.12

mm

Encoder

- 39 -J. Silva-Martinez 39


State of the artState of the art

Performance summary of the Proposed Current-Mode Adder-Quantizer and comparison with prior Quantizer in CT ΣΔModulators

[23] [29] This Work Technology

(nm) 180nm CMOS 180nm CMOS 90nm CMOS

Supply voltage 1.8V 1.8V 1.2VSupply voltage 1.8V 1.8V 1.2V

Quantizer Resolution 3 bits 4 bits 3 bits

Sampling rate 400MHz 800MHz up to 2GHz

Input range 400mVpp 3Vpp ±40App (equivalent to 400mVpp) * *

* Power consumption of the summing amplifier only.** 3-bit two-step Flash ADC.

Power Adder* 10mW Adder* 8.5mW Adder 1.1mW

Flash ADC** 24mW Flash ADC N/A Flash ADC 3.04mW

[23] C.-Y. Lu, et.al., “A 25MHz bandwidth 5th-order continuous-time lowpass sigma-deltamodulator with 67.7dB SNDR using time-domain quantization and feedback,” IEEE J. Solid-StateCircuits, vol. 45, no. 9, pp. 1795-1808, Sep. 2010.

[29] V Si h N K i h S P B Vi h D B h d N Ni i “A 16MH BW


[29] V. Singh, N. Krishnapura, S. Pavan, B. Vigraham, D. Behera, and N. Nigania, “A 16MHz BW75dB DR CT ΣΔ ADC compensated for more than one cycle excess loop delay,” IEEE J. Solid-StateCircuits, vol. 47, no. 8 pp. 1884-1895, Aug. 2012.


State of the artState of the art[20] * [21] ** This Work

Technology CMOS 0.13µm CMOS 0.18µm CMOS 90nm

Supply voltage 1.2VAnalog: 1.8V

1.2VDigital: 2.1-2.5V

Resolution 5 bits 4 bits 3 bits

Sampling rate up to 3.2GS/s up to 4GS/s up to 2GS/s

Input range 400mVpp ± 460mVpp ±40µApp

Power 120mWAnalog 78mW Analog 3.34mW

Digital (Including Clock Buffer) 530mW Digital (Including Clock Buffer) 8.94mW

DNL (After Calibration) -0.24LSB~ 0.18LSB (@3.2GS/s) - 0.14LSB ~ 0.15LSB (@4GS/s) - 0.206LSB ~ 0.138LSB (@1.48GS/s)

INL (After Calibration) -0.29LSB~ 0.39LSB (@3.2GS/s) - 0.24LSB ~ 0.20LSB (@4GS/s) - 0.056LSB ~ 0.206LSB (@1.48GS/s)PowerPower consumptionconsumption ifif extrapolatedextrapolated toto55 bitsbits isis lessless thanthan 1616mWmW forfor currentcurrent modemode

FoM 3.07pJ/conversion-step (2GS/s)

4.3pJ/conversion-step (3.2GS/s)

10.25pJ/conversion-step

(fin = 10MHz, 4GS/s)

1.37pJ/conversion-step

(fin = 10MHz, 1.48GS/s)

ENOB4.44 bits (2GS/s)

4 54 bits (3 2GS/s)

3.89 bits (4GS/s, 10MHz input)

3.48 bits (4GS/s, 100MHz input)

2.6 bits (1.48GS/s, 10MHz input)

2.6 bits (1.48GS/s, 44.4MHz input)

55 bitsbits isis lessless thanthan 1616mWmW forfor currentcurrent--modemoderealizationrealization

* Power consumption of output buffer was not included. ** Includes power consumptions for analog circuitry and digital encoder For the FoM calculation the digital power

4.54 bits (3.2GS/s)3.47 bits (3.4GS/s, 800MHz input) 2.54 bits (1.48GS/s, 118.4MHz input)

Area 0.18mm20.88mm2

(excluding resistor ladder)

ADC: 0.0276mm2

(excluding encoder)


Includes power consumptions for analog circuitry and digital encoder. For the FoM calculation, the digital power consumption for 4GS/s.

[20] Y.-Z. Lin, et. al, "A 5-bit 3.2-GS/s flash ADC with a digital offset calibration scheme," IEEE Trans. Very Large Scale Integration Systems, vol. 18, no. 3, pp. 509-513, March 2010. [21] S. Park, et. al, “A 4-GS/s 4-bit Flash ADC in 0.18μm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp.1865-1872, Sep. 2007.


A Blocker Tolerant Continuous-Time ADC f B db d A li i * ADC for Broadband Applications*

H. M. Geddada, C. J. Park, H.-J. Jeon**, J. Silva-Martinez, and A. I. Karsilayan

*Sponsored by SRC



Effect of the blockersEffect of the blockers on loop operationon loop operation Remarks on Filter’s operation: Filter’s input signalRemarks on Filter’s operation: Filter’s input signal

E*ZEEXV

qhde

1

sLe

1

X(f)

InbandInband signal is usually very small: Nice propertysignal is usually very small: Nice property

ADC

H(f)

1/(1+L) InbandInband signal is usually very small: Nice propertysignal is usually very small: Nice property

TransitionTransition band is more critical for filter’s linearity band is more critical for filter’s linearity (neighbor channels); (neighbor channels);

Filter must be designed for the blockersFilter must be designed for the blockers

0 dBFsNTF Freq

( )


Blocker tolerance is a major issue in broadband Blocker tolerance is a major issue in broadband applications (LTE)applications (LTE)

ZOH(f)


Clock Jitter Sensitivity (SJNR)Clock Jitter Sensitivity (SJNR) The main effects of clock jitter is present at the input of the

quantizer and DAC.

Jitter induced noise at DAC output is processed according to the STF, which is a serious problem for continuous-time sigma-delta modulators

Clock Jitter in quantizer

is not very relevant:

processed by NTF.

Clock jitter introduce Clock jitter introduce

uncertainty at the DAC

output (jitter induced


noise) processed by STF.


Jitter Issues: High Clock FrequencyJitter Issues: High Clock FrequencyJitt d

Vin

Loop FilterDout

Jittered Clock

QuantizerVDAC

Re-timed Data

Multi-Bit DAC

Flip-Flops

The DAC error due to clock jitter:

Error FunctionError FunctionJittered Clock

DAC

The DAC error due to clock jitter:

In the frequency domain: Convolution of Differential of Dout and Jn()

TtTnDnDnE outoutj

1

noutS

noutj JDT

sinJDZE2

21 1


In-band signal is shaped by , then it is not very criticalOut-of-Band quantization noise and blockers convolve with the clock jitter

11 Z


Jitter tone around Fsconvolve with images ofinband signal and producei b d i tin-band noise tones

Jitter and blocker convolves, producing in-b d i tband noise tones.

Jitter also convolves with OOB quantization noise

0

No jitter tone 20

0

fj =80.26Mhz, f

b =75.27Mhz

and downconverts into in-band noise.

-60

-40

-20

SNRJitter = 67.2dB

dBFS

)

jJitter tone at 497.43Mhz

-60

-40

-20

SNR = 39.3dB

SNR = 71 2dBdBFS

)

Ideal

-100

-80 SNRIdeal = 71.2dB

Pow

er (

d

-100

-80

SNR = 71.2dB

Pow

er (

d

- 46 -J. Silva-Martinez10-1 100 101 102-140

-120

Frequency (MHz)

10-1 100 101 102-140

-120

Frequency (MHz)


Blocker Sensitivity: Feedforward ADC

0.6

0.7

V in (v

)

0.1 0.2 0.3 0.4 0.5 0.60.5

0.5

1

0.1 0.2 0.3 0.4 0.5 0.6-1

-0.5

0

DO

UT

Ti ( )

Loop filter, ADC, DAC Inherent antialiasing

Time ( sec)

STF=FF/(1+LG) 1(in-band); NTF=1/(1+LG)(Noise shaping) Quantizer can have relaxed specifications FF architecture is power and area efficient


Dynamically more stable

OOB peaking in STF


Another Major Issue: Another Major Issue: Loop SaturationLoop Saturation

10

20

30

-8

-4

r (dB

FS)

-20

-10

0

10

Gai

n (d

B)

BP 16

-12

able

blo

cker

pow

er

60

-50

-40

-30

G BP1LP1BP2LP2

-20

-16

Max

imum

allo

wa


107 108-60

Frequency (Hz)

Blocker Tolerance

0 20 40 60 80 100 120 140 160 180-24Frequency (MHz)


Blocker and Jitter Tolerant Wideband ModulatorsH. M. Geddada, et.al.H. M. Geddada, et.al.Re-evaluation TVLSI

TransientTransient responseresponse ofof thetheADCADC toto thethe 88..77dBFSdBFS blockerblockeratat 100100MHzMHz inin thethe presencepresence

OutputOutput spectrumspectrum ofofthethe ADCADC withwith andandwithoutwithout thethe 99dBFSdBFS

0 5

1

VIN

40

‐20

0

Vin = -6dBFS @ 5MHzNo blocker

ppofof aa --66dBFSdBFS inin--bandband signalsignalatat 55MHzMHz

withoutwithout thethe --99dBFSdBFSblockerblocker atat 4040MhzMhz

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2x 10-6

0

0.5V

1

T ‐120

‐100

‐80

‐60

‐40

Pow

er (

dBFS

)SNR = 75.1dB

0 8

0.9

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2x 10-6

0

0.5VDET

=0.5u sec

10‐1

100

101

102

120

Frequency (MHz)

-60

-40

-20

0

(dB

FS)

Vin = -6dBFS @ 5MHzBlocker = -9dBFS @ 40MHzAttenuation factor = 12dBStable Operation

- 50 -J. Silva-Martinez0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2x 10-6

0.4

0.5

0.6

0.7

0.8

Time (sec)

VOUT

10-1 100 101 102

-120

-100

-80

-60

Frequency (MHz)

Pow

er (

SNR = 46.5dB


Proposed minimally invasive LPF

0

-15

-10

-5

)

STF (Vx/Vin)NTF (Vx/Vn,r1)NTF( Vx/Vn,op)

10dB

Signal & Noise transfer functions

-30

-25

-20G

ain(

dB) , p

10dB attenuation at 60MHz In band noise 15 µV rms which is

- 51 -J. Silva-Martinez 100 101 102 103-40

-35

Frequency (MHz)

Signal bandwidth In-band noise 15 µV-rms which is

well below the ADC noise level


Measurement results

40

-20

0

With input signalWithout Input signal

RBW = 15.2KhzVin: -2.86dBFS @2.75 MHzHD2: -78.3dBFS @5.5MHzHD3: -73dBFS @8.25MHz

-80

-60

-40

Pow

er (d

BFS

)

HD3HD25th Order CT LP ADC,

10-1

100

101

102-120

-100

60

70

SNRSNDR

Active area < 0.43mm2

In 20MHz BW, Input of -2.86dBFS at 2.75 MHz

P k SNR 66dB P k SNDR

Frequency (MHz)

30

40

50

SN

DR

(dB

)

SNDR

Peak SNR= 66dB, Peak SNDR= 64 dB

HD3= -73 dBFS, HD2= -78.3 dBFS

10

20

30

SN

R &

S


dBFS DR=69dB-70 -60 -50 -40 -30 -20 -10 0

0

Input Power (dBFS)

Dynamic Range = 69dB


Summary: Blocker Tolerance LPF provides blocker rejection especially at the critical

frequencies. Overload detector and PGA prevents the ADC saturation

during transients. Blocker reduction techniques Blocker reduction techniques

Power overhead < 6% Area overhead < 20 %

Advantages L Less power Loop parameters are not disturbed so fast settling times Protects the ADC from instantaneous/temporary blockers


Protects the ADC from instantaneous/temporary blockers Moderate SNR is better than no communication or no SNR


Performance Summary of the ADC

[9] [10] [11] This work

Fs [Mhz] 250 64 160 500Fs [Mhz] 250 64 160 500BW [MHz] 10 1 5 20

SNDR/SNR [dB] 65/68 NA/75.5 69.5 64/66Dynamic Range [dB] 71 65# 76 69Dynamic Range [dB] 71 65# 76 69

Blocker reduction [dB]adjacent/alternate channels

8/15 9.5/20+ 10 15/18

Settling time (µsec)* 51 - - < 0.3

Power consumption [mW] 18 4.1 6 17.1

Area(mm2) 1 35 0 14 0 56 0 43Area(mm ) 1.35 0.14 0.56 0.43Technology (nm) 130 180 130 90


# fixed input resistor * switching input resistors* * Blocker adaptation time+ Extracted from a plot comparing measured and simulated performance, no in-band signal


Fundamentals on MASHFundamentals on MASH architecturesarchitecturesE

Analog Intensive

1qE

DAC

ZY1 ZX ZH1

ZH2 Analog Intensive MASH topology

DAC ZH2

2qE

ZY

Schreier-Temesq

ZY2

ADC

Leslie and SinghISCAS-1990

22413

2413 0

qENTF*HXSTF*HzYThen

STF*HNTF*HIf

2

1

2

2

2

1

22413

q

q

X*STFSTFESQNR


1122

qq E*NTFNTFESQNR


Fundamentals on MASHFundamentals on MASH architecturesarchitectures

Analog Intensive Pseudo-MASH

High-Resolution Pipeline ADC

N-bitsPseudo MASH topology

Software Pl tf

RIN

kLP2

kBP24-Bits

_Active-RC

4th order

PlatformVin

kBP1

Filter

NR

ZA

C2

Clock Generator

DA

C

kLP1CLK

DELAYDigital signals (D1-D7)

N DD

Todd Brooks, et. al., JSSC D 1997


JSSC, Dec 1997


Target: SNDR Improvement by 3 bits0

O t t With C l ti

-40

-20X: 5.005e+006Y: -6.02

Output With CancelationOutput Without Cancelation

80

-60

-40

dBFS

) SNR = 79.516dB SNR = 105.803dB

-100

-80

Pow

er (

d

-140

-120

SQNR improvement should be around 18dB (3 bits)

105 106 107 108-160

Frequency (Hz)


SQNR improvement should be around 18dB (3 bits)

Power overhead, area overhead < 20%


ConclusionsConclusions Minimization of filtering functions in the receiver

h i d d i ti ADC l tichain demands innovative ADC solutions;

SNDR > 80 dB will be frequently needed in wireless applications;applications;

Jitter and Blocker tolerant architectures are needed;;

DAC calibration techniques for fast and high-resolution applications;

Global tuning strategies (for stability)

Advanced LTE applications require high-resolutionf i l BW hi h 200MH


for signal BW as high as 200MHz


Recommended Readings

S. Norsworthy, R. Schreier and G. Temes, Delta-Sigma Data Converters: Theory, Design and Simulation, IEEE Press

R. Schreier and G. Temes, Understanding Delta-Sigma Data Converters, IEEE Press

J. Cherry, M. Snelgrove,Theory, Practice, and Fundamental Performance Limits of High-Speed Data Conversion Using Continuous-Time Delta-Sigma Modulators, Kluwer Academic Press.

J. M. de la Rosa, Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey, TCAS-I, Jan 2011.

Other tutorials: IECE-2012


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