ARTICLE IN PRESS

Microelectronics Journal 39 (2008) 1534–1537

Contents lists available at ScienceDirect

Microelectronics Journal

0026-26

doi:10.1

� Corr

E-m

journal homepage: www.elsevier.com/locate/mejo

Low power and high gain current reuse LNA with modified input matchingand inter-stage inductors

S. Toofan �, A.R. Rahmati, A. Abrishamifar, G. Roientan Lahiji

Electrical Engineering Department, Iran University of Science and Technology, Narmak, Tehran, Iran

a r t i c l e i n f o

Article history:

Received 24 January 2008

Accepted 31 July 2008Available online 23 September 2008

Keywords:

RF CMOS LNA

Inductive degenerative LNA

Receiver front-end

Current reuse LNA

Inter-stage inductor

Modified architecture

92/$ - see front matter & 2008 Elsevier Ltd. A

016/j.mejo.2008.07.073

esponding author. Tel.: +98 9125948476; fax

ail address: S_toofan@iust.ac.ir (S. Toofan).

a b s t r a c t

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified

input matching circuitry and inductive inter-stage architecture in 0.18mm CMOS technology. To reduce

the large spiral inductors that actually require larger surface area for their fabrication, two parallel

LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by

parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this

configuration we used two cascoded transistors to have a good output swing suitable for low voltage

technology compared to other current reuse configurations. This configuration provides better input

matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete

analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9 dB NF, 50O input

impedance, 1 GHz 3 dB power bandwidth, 20.5 dB power gain (S21), high reverse isolation (S12)o�48 dB,

�18.5 dB input matching (S11) and �21.3 dB output matching (S22), while dissipating as low power as

2 mW at 1.8 V power supply.

& 2008 Elsevier Ltd. All rights reserved.

1. Introduction

In the past few years, wireless local area networks (WLAN)have been deployed all over the world as office and homecommunication infrastructures, where LNAs are important com-ponents in these systems [1]. Price and other market require-ments force RF receivers to be integrated in standard CMOStechnology along with the rest of digital signal processing units [2].Integrating large amount of circuits for sure requires low powerconsumption design techniques; therefore wide attention hasbeen paid to the low power fully integrated LNA designs.

Besides power consumption, there are many other parametersof importance that are used as part of the trade-off among the LNAdesigns. Some of these parameters are: input impedance match-ing, noise figure, power gain, stability, linearity and increasing thefrequency of operation [3,4]. In order to increase the frequency ofoperation, LNA designers, take advantage of some circuit techni-ques such as unilateralization and neutralization methods besidethe widely used single-stage cascode topology [5,6].

LNA actually amplifies the weak signals coming from theantenna and duplex filter, and delivers them to the next stage withminimum amount of added inherent noise. To minimize thereflections from LNA to the antenna and duplex filter, impedance

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matching is required [7]. Providing sufficient transconductancegain with acceptable linearity and power consumption is part ofan LNA design in order to overcome the noise of subsequentstages. Linearity in LNA is typically measured in terms of IIP3which is required to be maximized. To impose a suitable trade-offs among the LNA parameters, we presented a fully integratedCMOS LNA circuit [8]. In order to decrease the total noise figureand to increase the sensitivity of receiver, its power gain isincreased by the application of current reuse structure.

Several works have been reported on the current reusetechniques in LNAs [9,10]. In [9] a current reuse two-stage LNAtopology is proposed, which adopts a series inter-stage resonanceto enhance the gain. But, using a three transistor in cascode formdecreases the output swing which is not suitable for low voltagetechnology and introduces additional noise. Ref. [10] reports again controlled differential current reuse LNA for IEEE 802.11aWLAN application. Despite using a current reuse structure, it hashigh power consumption and low power gain compared to othersimilar topologies. Furthermore, they use on-chip spiral inductorsthat take a large area which is costly and needs to be avoided.

The emphases of this paper are reducing the power consump-tion and inductors area, improving the power gain of CMOS LNAwhile still retaining acceptable noise performance, better inputmatching and sufficient linearity. The above improvements havebeen achieved by the implication of cascode current reusestructure with using two parallel LCs instead of inter-stageinductor and input matching inductor. After discussing the input

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S. Toofan et al. / Microelectronics Journal 39 (2008) 1534–1537 1535

impedance matching techniques, we explain the details of ourdesign process. The simulation results of the designed LNA andcomparison with other works are presented in detail.

2. Input impedance matching

In Fig. 1 of [3], four distinct methods of matching inputimpedances in LNAs were given, which includes adding a resistorat the input terminal, common gate configuration, a resistiveshunt-series feedback and inductive degeneration common sourceLNA. The inductive degeneration technique, depicted in Fig. 1, doesnot degrade the amplifier’s noise performance and it easilymatches the input impedance [3].

From Fig. 1(b), the input impedance of inductive degenerationCMOS LNA is expressed by [3,11]:

Zin ¼ RLg þ Rg þ Rnqs þgm1Ls

Cgsþ sðLg þ LsÞ þ

1

sCgs(1)

where Cgs is the gate–source capacitance of the transistor. Formatched input impedance, at desired frequency, the real andimaginary parts of (1) must be equal to Rs and zero, respectively.However, the on-chip spiral inductors take large area which iscostly. To alleviate this problem, several ways are presented forreducing Lg. One way is to increase the input transistor’s width W

so as to increase Cgs. Another way is to connect an additionalcapacitor in parallel with gate–source capacitance. Both of thesemethods degrade the quality factor of the input stage, which willin turn degrade LNAs performance. Another method is using aparallel LC network that is illustrated in Fig. 2.

For oooo1, where oo1 ¼ 1=ffiffiffiffiffiffiLCp

is the resonant frequency ofthe parallel LC network, its impedance (Z) can be modeled with aseries RL circuit, then

Z ¼ joLg þ Rg (2)

By a simple calculation we can write [12]:

Lg �L

1�o2LC¼

L

1� ðo=oo1Þ2

(3)

Rg �RsL

ð1�o2LCÞ2¼

RsL

ð1� ðo=oo1Þ2Þ2

(4)

where for simplicity, the inductor is simply modeled as an idealinductor L and a series parasitic resistance RsL. Hence, a smallparallel LC circuit can be modeled as a large inductance Lg [12]. In

sRgL

1M

sL

sRgL gRLgR

nqsR

gsC gsv+

−m1 gsg v

2oni

sL

LsR

sv

sv

Fig. 1. Common LNA input architecture, (b) equivalent circuit of (a).

LC Lg Rg

Fig. 2. Parallel LC network and its equivalent circuit for oooo1.

this work, we used this method to overcome the use of largeinductors.

3. Designing process

The designed LNA as illustrated in Fig. 3 has cascode currentreuse structure with parallel LC network in inter-stage and inputmatching network. The design process can be presented as follows:

The first step in our design was to calculate the optimum widthof the input transistor in order to obtain the best noise perfor-mance. The input transistor channel width is calculated by [13,14]

W1 ¼WoptjFminffi

3

2oLCoxRsQLop(5)

where Cox, Rs, o, QLop and L are the oxide capacitance, sourceresistance, the operating frequency, optimum quality factor ofinput circuit, and length of the transistor, respectively; whereQLopX2.598 [13]. The gate width of the cascode transistor M2 ischosen half or similar of the M1 size. This needs a trade-off inorder to suppress the noise introduced by M2 and the gainobtained by load. The value for the total gate to source capacitanceof transistor M1, Cgs1, can be taken as

Cgs1 ffi23W1LCox (6)

Transistor M3 forms a current mirror with M1 that biases thewhole LNA circuit. In order to minimize the noise and powerconsumption, its width must be set to a small fraction of M1’s. Inthis design we assumed W1 ¼10W3.

In order to limit the total power consumption the seconddesign step is the calculation of supply current or referencecurrent source. The supply current is

IVcc ¼ IDM1 þ IDM3 ¼ IDM2 þ IDM3 ¼ Pdis=Vcc ffi 1:1Iref (7)

where IVcc, IDMx and Iref are the supply current, the relatedtransistor drain current and amount of reference current source,respectively.

The third step is finding Lg and Ls, from Eqs. (8) and (9), whereLg represents the imaginary part of the equal impedance of Lg1Cg1.In this step we consider an amount for (RLg+Rg2+Rnqs2) and thenrepeat this step until the simulation results confirm the well doneinput matching. Rb1 and Rb2 have been used for mitigating theeffect of gate-source capacitor of transistor M3 and as a bias of M2,respectively. Arbitrarily, both are chosen to be 2–4 kO in 0.18mmtechnology [13].

oo ¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1

ðLs þ LgÞCgs1

s(8)

vsLs

Vcc

3M

Rb1

0.1Iref mA=

Rs

Lg1 M1

Lg2

M2

C1

C2

3C

Cd2

Ld2

Ld1

Rb2

Cd1

Cg1

x

y•

•

Fig. 3. Designed and simulated LNA structure.

ARTICLE IN PRESS

id2y

id1x

Led1 gm2vgs2vgs2Cgs2

Rnqs2

Rb2

Lg2

Fig. 4. Small signal equivalent of current reuse part of designed LNA.

Table 1Aspect ratio of transistors and the value of inductors

Frequency (W/L)1 (W/L)2 (W/L)3 Lg1 Lg2 Ls Ld1 Ld2

5.5 GHz 125m/0.18m 62.5m/0.18m 15m/0.18m 3.9n 6.25n 0.5n 4.4n 4.65n

20

19

18

175 5.5

S21

[dB

]

Frequency [GHz]

2.6

2.4

2.2

2

1.8 Noi

se F

igur

e (N

F) [G

Hz]

NF

S21

Fig. 5. LNA noise figure (NF) and power gain (S21).

-8

-10

-12

-14

-16

-18

5 5.5

S11

[dB

]

S22

[dB

]

Frequency [GHz]

-10

-15

-20

S22

S11

Fig. 6. LNA S11 and S12.

Table 2Simulation results of this proposed LNA and previously published LNAs

LNA This work Ref. [1] Ref. [7]a Ref. [10]

f0 (GHz) 5.5 5.2 5.7 5.7

NF (dB) 1.8–2.6 3 3.4 3.65

Current (mA) 1.1 3.2 2.2 8

Supply (V) 1.8 1.8 1.8 1.8

IIP3 (dBm) �6.2 �5 – �3.3

S11 (dB) �18.5 �17 �14 �15.2

S21 (dB) 20.5 12.4 11.45 14.5

S. Toofan et al. / Microelectronics Journal 39 (2008) 1534–15371536

RLg þ Rg2 þ Rnqs2 þgm1Ls

Cgs1¼ 50 (9)

In this paper, in order to reduce the area taken by Lg, we use asmall parallel Lg1Cg1 as an on-chip spiral inductor described inprevious section.

The fourth step is the design of inter-stage inductors. The valueof Lg2 is calculated to resonate in series with the input capacitanceof M2 [9]. Fig. 4 shows the small signal equivalent circuit of Fig. 3between x and y nodes, where Led1, Cgs2 and Rnqs2 are theequivalent inductance of Ld1Cd1, the gate–source capacitance, andthe non-quasi static effect of transistor M2, respectively. As wasmentioned before, the amount of Rb2 is larger than inputimpedance in gate M2. Then from Fig. 4, the current gain can beexpressed as

id2

id1ffi

gm2

sCgs2

sLed1

sLed1 þ sLg2 þ Rnqs2 þ 1=ðsCgs2Þ(10)

If sLed1 provides sufficiently high impedance, then

id2

id1ffi

gm2

sCgs2ffi

oT

o . (11)

This equation indicates that significant current gain can beobtained from the drain of M1 to that of M2, leading to high overallpower gain [12]. So, in our design in order to achieve higher powergain based on Eq. (11), we take the largest amount for Led1, andthen we design it with a small parallel Ld1Cd1 on-chip spiralinductor structure, as mentioned before in order to reduce thearea.

Obviously, because of the Miller Effect, the input matching willbe influenced by the inter-stage devices that in turn deterioratethe input matching that already was achieved. Then it may benecessary to go back to the third step and repeat the designprocess again.

At the output, an inductor Ld2 is placed at the drain primarilyfor two reasons: First, to resonate with the total drain capacitancein order to achieve the desired frequency range. Second, toprovide high enough impedance to allow for a good voltage gain.The largest amount of Ld2 is restricted by the total draincapacitance. Then the value of Ld2 and Cd2 are chosen bytrading-off between gain and bandwidth of the circuit. Of course,the minimum amount of Cd2 is defined by the load (e.g. mixer)and LNA output capacitances.

S12 (dB) o�48 – – –

S22 (dB) �21.3 �16 �17 �14

Technology (mm) 0.18 CMOS 0.18 CMOS 0.18 CMOS 0.18 CMOS

a Measurement results.

4. Simulation results

The designed circuitry has been simulated using HSPICE.Device dimensions and inductors values are given in Table 1.Fig. 5 shows the power gain (S21) and noise figure (NF), and Fig. 6shows the S11 and S22 for 5.5 GHz center frequency. Fig. 5 showsthat we achieve a high power gain and good input impedancematching with small on-chip spiral inductors. As indicated inTable 2, the NF and power consumption have been reduced, powergain increased, matching parameters (S11, S22) are in acceptableranges and approximately are equal to the amounts of other works[1,7,10]. It is concluded that the structure used for LNA not only

satisfies most of the parameter of importance in LNA but alsoallows better trade-off among the LNA defining parameters.

5. Conclusion

In this paper we designed and simulated a fully integratedCMOS low noise amplifier with on-chip spiral inductors in 0.18mm

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S. Toofan et al. / Microelectronics Journal 39 (2008) 1534–1537 1537

CMOS technology. Simulation results showed increased powergain with a small inter-stage spiral inductor. Moreover, powerconsumption is quite low compared to the other works [1,7,10].Designed LNA has good noise figure, lower power dissipation,better input impedance matching and also suitable power gain.All these became possible by employing a current reuse structurewith modified input matching and inter-stage inductor, whichalso allows good trade-off among the LNAs known parameters.

Acknowledgement

The author would like to thank the Iran TelecommunicationResearch Center (ITRC) for supporting this work.

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