(from ibm) low power issues in chip design

8/13/2019 (From IBM) Low Power Issues in Chip Design

1/74

ICCAD 03

Leakage Issues in IC Design: Part 3

Anirudh Devgan

[email protected]

IBM Research Austin


2/74

utline

Part1: Siva Narendra (Intel Corporation)

Device physics, process technology, leakage fundamentals

Part 2: David Blaauw (University of Michigan)

MTCMOS, Dual-Vt, estimation/optimization techniques for dual-Vt

Part3: Anirudh Devgan (IBM Corporation)

Process & Environmental variations, ABB, Vdd control

Part4: Farid Najm (University of Toronto) State dependence, sleep states, memory/cache circuits and architectures


3/74

eakage

Leakage power is becoming asignificant portion of total power.

Currently managed to 15-20% in

current IBM designs.

Expected to increase dramatically infuture designs & technologies.

In some cases (11S), predicted to

more than 50% of total power.

Leakage is the problem Emerging as the critical challenge in

VLSI Design.

Leakage depends super linearly with

Process variations, Temperature,Power supply voltage

Gate

S

ub-Threshol

d

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1990 1995 2000 2005 2010 2015 2

NTRS '97

ITRS '99

ITRS '01

International Technology Roadma


4/74

ariability: Leakage and Timing

Source: Intel, DAC 2003


5/74

eakage & Thermal Variations

L3Directory/Control

L 2 L 2 L 2

L S U L S UIF UB X U

ID U ID U

IF UB X U

F P U F P UFXU

FXUIS U IS U

Temperature varies with-in the chip

Chip Floorplan Chip Thermal Profile

Power 4 Server Chip: 2 CPU on a chip

The CPUs can be much hotter than the caches


6/74

ower Supply Variations

Vcrit

time

Voltage

VDD+

Rg

Rd

Cd

L

Package Grid

Decap Load

IDD

time

tp

LoadWaveform

DC Decap Package

~SameVDD Noise l tp Rg + L R2g Cd (1 e

-tp/)


7/74

ower Delivery

onnection

package

Connection to circuits

C4 balls


8/74

upply Voltage & Temperature

Leakage dependence on Vdd

Variation in both gate and sub-threshold leakage.

Need to combine Power supply

analysis with Leakage.

Leakage significantly affected by

temperature. With-in die temperature variations

need to be modeled.

0

0.5

1

1.5

2

2.5

3

0.6 0.7 0.8 0.9 1 1.1 1.2

Gate Subthreshold Sum

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

55 70 85 100 115

Temperature (deg C)

M ean LeakageM ax Leakage

M in Leakage


9/74

Power integrity & Package

Package design becoming increasingly complicated Large number of power/ground layers in current packages

Significant Power supply variations caused by the package

chipcapacitorcapacitor

chip carrier

Solder balls


10/74

ower Supply Variations Package Effects

C4s

Balls

lanes

VDD

GND

Power IR Drop by the package

Is usually non- uniform across the various

C4

Can be difficult to predict and analyze


11/74

Variability Real?

S. Nassif DAC 2003


12/74

ariability Time Scales

10 10-8 10-7 10-5 10-4 10-2 105 107

Risin

g/R

isin

g

Risin

g/F

alli

ng

nal Coupling SOI History

VDD/Package Noise

Temperature Process Line

S. Nassif DAC 200


13/74

ariability Distribution

Physical: Die to die variation

Imposedupon the design (constant regardless of design).

Well modeled via worst-case files. Within-die variation

Co-generatedbetween design and process (depends on details ofthe design).

Example: nested vs. isolated poly-silicon L.

Environmental:

Only makes sense within-die.


14/74

ariability vs. Uncertainty

Variability: known quantitative relationship to a source(readily modeled and simulated).

Designer has option to nullout impact.

Example: power grid noise.

Uncertainty: sources unknown, or model too difficult/costly to

generate or simulate.

Usually treated by some type of worst-case analysis.

Example: L within die variation.

Lack of modeling resources often transforms variability toLack of modeling resources often transforms variability to

uncertainty.uncertainty. Example: nearest neighbor noise coupling.Example: nearest neighbor noise coupling.


15/74

ithin-Die Variations?

Fundamentally different from die-to-die. Environmental components:

VDD & Temperature variations are natural byproducts of power

distribution analysis. Power distribution analysis unavoidable .

Physical components:

VT and L variations across the die. Lot, Wafer, and Die distributions.

Layout (design) dependent.


16/74

patial Variability

Die 1 Die 2

wafe

Param

eter

Posit

Facility, Line, Lot, Wafer &Die components.

Semi-periodic across wafer.

Wafer level and above arenot of interest to a designer.

Designer does not get to chooseDesigner does not get to choose

where on a wafer his design goes!where on a wafer his design goes!

S. Nassif DAC 2003


17/74

ources of Within-Die Variations

Poly line-width (LEFF

) variation comes from:

Mask, Exposure and Etch variations

Essentially identical to modeling required for OPC.

Mask & OPC biasMask & OPC bias

ResistResistPolyPoly

SiliconSilicon

Layout (designer view)

Lithography biasLithography bias

Etch biasEtch bias

S. Nassif DAC 2003


18/74

EFF variations via OPC

S. Nassif DAC 2003


19/74

ources of Within-Die Variations

Vertical variations are caused by chemical-mechanical

planarization (CMP) process.

polishes

faster

C1 C2

S. Nassif DAC 2003


20/74

eakage Modeling and Analysis

Gate

Sub-Th

reshold

Input pattern vector(state)

Process Variations

(L, VT, TOX, )

Operating Environment(Temperature, VDD, )

Topology

All effects need to be accurately modeled


21/74

Leakage Requirements

Need to include environmental and process variation

Channel lengthSupply voltage

Temperature

Standby leakage

Active & burn-in leakage

S. Narendra ICCAD 20


22/74

rocess Dependence

Leakage varies exponentially with process variations.

10X variation due to process vs. 10% variations due to different patterns.

Reason: sub-threshold current varies exponentially with process variations

0

0.05

0.1

0.15

0.2

0.25

1 2 3 4 5

Process Variation Parameter (NRN)

Leakage(mA)

M in Leakage

M ean Leakage

M ax Leakage

~10%

~10X IDDQ for typical chip


23/74

eakage & Process Variations

Process parameters (Leff, Vth) have great influence

Generate leakage performance statistics

Practical bounds for a given confidence level can be driven

Cumulative

Distribution for

Leakage

Within-chip(Deterministic)

Global variationsL

eff

distribution

Within-chip(Random)

+ +

Total Leakage

0.99

L3

=L0.99L-3 =L0.01

0.01


24/74

rocess Variations

Leakage is exponentially dependent on process variations

eII omeanLL

=

)(

Normal distribution of L leads to a LogNormal distribution of leakage.

S. Narendra ICCAD 2


25/74

rocess Variations: ACLV

-4 -3 -2 -1 0 1 2 3 4Global Sigma

NoofChip

s

-4 -3 -2 -1 0 1 2 3 4

ACLV Sigma

0.0

0.2

0.4

0.6

0.8

1.0

1.2

NoofTransistors

Chip

Mean

Leff

With-in Chip:ACLV

Chip to Chip Variation


26/74

Leakage modeling

o

n

n

no

p

p

p

l-leak I

k

wI

k

wI +=

Lower bound:

Assumes all devices in the die are nominal L

3

noffn

n3

poffp

p

u-leak

Ik

wI

k

wI

+

=

Upper bound:

Assumes all devices in the die are minimum L

Prior techniques



27/74


28/74

Applications

=

o

leak

I

I

w

kln2

A macroscopic standard

deviation () representing

parameter variation in a chip

2

n

2

2n

n

non

2p2

2p

p

pop

wleak ek

wI

ek

wI

+= Leakageestimation

Depends on parameters that can be estimatedS. Narendra ICCAD 2002


29/74

Measurement results0.18 um 32-bit microprocessors (n=960)

0

100

200

300

400

500

0.1 1 10 100

Ratio of measured to

calculated leakage

Nu

mberofsamples

: 0.65: 0.27

: 6.5 : 3.8

Ileak-l

Ileak-u

: 1.04 : 0.3Ileak-w

0

100

200

300

400

500

0.1 1 10 100

Ratio of measured to

calculated leakage

Nu

mberofsamples

: 0.65: 0.27

: 6.5 : 3.8

Ileak-l

Ileak-u

: 1.04 : 0.3Ileak-w

50% of the samples within 20% of the measured leakage

Compared 11% and 0.2% of the samples using other techniques



30/74

haracterizing the variation

Variations in channel length occur at both the intra-die (within-die) level and

inter-die (die-to-die) level

iintra,internominalitotal LLLL ++=,

Lintra

Linter

R. Rao,et al. ISLPED 200


31/74

mpirical Model

Using the following mathematical model

Eliminate Vth as an intermediate variable and use general form of SPICE modelto perform empirical fitting on channel length

Properties of this equation: Preserves exponential dependency of Ion L

Is easily invertible (simple quadratic equation formula)

Yields closed-form expressions for the PDF of I

Accurately fits over a wide range of values of L for NMOS/PMOS and transistor stacks

( ) ( )== + LheqI dd LqLq2

32

1

( )IgIqqqq

qL =

+

= 13222

3

ln421



32/74

oodness of fit

NMOS in 0.18m: Vgs=0, Vds=Vdd and 10% variation in Ld

Comparison of simulation datawith analytical expression

Comparison of experimental PDFwith PDF obtained analytically

SimulationAnalytical

BSIM3 Fit

SimulationAnalytical


f /


33/74

ccounting for inter/intra-die variations

We accommodate variation across both levels in our empirical

model

Assume L,total=15%. First determine the parameters for L,inter=0% and

L,intra=15% of nominal

Enumerate all inter-die variation points (Ex: 1%, 2% etc.,)

For each point, shift the mean by L,interand obtain the distribution of currents

around that average point using L,intra Perform weighted summation across the range of L,inter

iintra,internominalitotal

LLLL ++=,

222

intraL,interL,totalL, +=

WeightedSummation

R. Rao,et al. ISLPED

k PDF f diff t i t /i t di i ti


34/74

eakage PDF for different intra/inter-die variation


k M d li d A l i


35/74

eakage Modeling and Analysis

Gate

Sub-Th

reshold

Input pattern vector(state)

Process Variations

(L, VT, TOX, )

Operating Environment(Temperature, VDD, )

Topology

All effects need to be accurately modeled

ith hi i t l i ti


36/74

ower with on-chip environmental variations

Leakagepower(P0)

Dynamicpower(PD0)

Converge ?Stop

Thermalprofile

Voltage dropcontour

Leakage ModelPleak= P0f(dVdd, dT)

Dynamic powermodel ~ dVdd

2

N

Y

h l P fil C t ti


37/74

hermal Profile Computation

Full chip thermal model

Thermal system modeled is this paper is assumed to be static (i.e. not time-varying) Dynamic, time varying model can also be used if desired

Silicon

Substrate

SiO2

Si

Metal +

ILD

C4

Heat sinks

Package


38/74

Thermal Equations

0),,(),,(2 =+ zyxpzyxTk

Steady-state heat conduction equation:

wherep is the power density of the heat sources, kis the thermal conductivity

Boundary conditions

Isothermal (Dirichlet): T = fi(x,y,z)

insulated (Neumann): T/ ni

= 0

Convective (Robin): ki T/ ni=hi(T Ta)

h l M d l


39/74

hermal Model

dxdydz

p

dz

TTT

dy

TTT

dx

TTT zyxzyxzyxzyxzyxzyxzyxzyxzyx

k =++ +++++ +++

)( 21,,,,1,,

2

,1,,,,1,

2

,,1,,,,1 222

kdydzdx

iR =

Tx,y,z Tx+1,y,zTx-1,y,z

Tx,y+1,z

Tx,y-1,z

Tx,y,z+1

Tx,y,z-1

Thermal network

Model the circuit as a linear circuit

hdydzbR 1=

h l M d l


40/74

hermal Model

Analogy between thermal and electrical circuits:Thermal Electrical

T : Temperature (K) == V

Rh: Thermal res (K/W) == RQ : Heat flow (W) == I

Thermal System can be modeled as linear circuit

GV=I

However, thermal modeling of a typical chip leads to millions of nodes

Need to use specialized linear solvers

i it A l i f Th l/VDD i it


41/74

ircuit Analysis for Thermal/VDD circuits

General equation: Gx + Cx = B(t)

G conductance matrix.

Ccapacitance matrix.

x, x nodes voltages & KVL currents, time derivative.

B(t) time dependent current sources.

Analysis using SPICE-like simulators is not practical. Dimension ofx~ 105 to 107.

Standard circuit simulators cannot make use of any special properties of the

analysis.

l i A l ti


42/74

nalysis Acceleration

Make use of the linearity.

BE discretization: (G+C/h)x(t+h) = B(t)+(C/h)x(t).

System Solution:x(t+h) = (B(t)+(C/h)x(t))(G+C/h)1.

The matrix (G+C/h) is independent of time only needs to be inverted once.

Avoid data explosion.

One layout polygon translates to many resistors.

Retain geometrical description and leverage to reduce translation overhead.

Specialized Linear Solvers.

Algebraic multi-grid (AMG) solvers

lti G id M th d


43/74

ulti-Grid MethodsBasic idea:

Reduce original grid h to a coarser grid 2h. Map problem from original to coarser grid.

Solve problem at coarse grid (iterative solver).

Map solution back to fine grid and refine.

Systems:

Fine:Ahxh= bh Coarse: A2hx2h= b2h

Fine Coarse

eakage Variation


44/74

eakage Variation

1.159-1.2

1.016-1.196

Vdd (V)

-0.13675.5 89.11.122

-1.85080.8 110.39.601

Change in

Leakage

withvariations

(W)

T (C)Leakage

(No

variations)(W)

Chip

hermal & Power Grid Solver


45/74

hermal & Power Grid Solver

Power Grid

Power Grid

Power Grid

Thermal

Thermal

Analysis

2.1438.102.73M

1.3293.581.74M

0.4688.39630k

0.61139.17270k

0.4582.13170k

Mem (GB)Runtime

(sec)

Matrix Size

eakage Modeling


46/74

eakage Modeling

Leakage various super linearly with temperature and power supply voltageHowever, on chip variations of temperature and voltage are limited

Leakage as a function of temperature and voltage is modeled as second order

]

1)[0,0(),(

1

2

21

2

21

VTcVbVb

TaTaITVI

+++

++=

Gate and subthreshold leakage is modeled separately


47/74

esults: Thermal profile


48/74

esults: Thermal profile

Thermal map of 9mm x 9mm ASIC chip

esults: VDD Profile


49/74

esults: VDD Profile

VDD profile

esults: Leakage w/ VDD & Temp Variations


50/74

esults: Leakage w/ VDD & Temp Variations

Leakage considering environmental variations

Accurate leakage model of actual VDD and temperature profile

For this example, leakage is lower by 10%

omparison to Fixed Drop Analysis


51/74

omparison to Fixed Drop Analysis

Need to accurately captures the on-chip locality of power supplyand temperature and their influence on leakage

Reduce the optimism of the fixeddrop method

85

80.8 -

110.3

T (C)

-4.295.311.08Fixed

Drop

-1.857.751.016-

1.196

OCV

Change in

Leakage(W)

Leakag

e(W)

Vdd (V)Chip 1

i bl Th h ld CMOS (VTCMOS)


52/74

ariable Threshold CMOS (VTCMOS)

Body effect to change device Vt Standby leakage reduction with maximum reverse bias Triple well structure

N-isolation

P-sub

N-well P-well

VBBP VDD VSS VBBN

p+ p+ n+ n+

VDD

VSS

VBBP

VBBN

BBBBt0t 2V2VV +=

Body Effect:

TCMOS


53/74

TCMOS

Variable Threshold CMOS (from T. Kuroda, ISSCC, 1996) In active mode:

Zero or slightly forward body biasfor high speed

In standby mode:

Deep reverse body bias for lowleakage

Triple well technology required

Kaushik Roy, ECE, Purdue University

VTCMOS Example


54/74

C OS a p e

T. Kuroda, et al, A 0.9V, 150Mhz, 10mW, 4mm2, 2-DCT CProcessor with Variable Vt Scheme, JSSC Nov. 1996

VTCMOS principle applied to 4-mDCT core processor

SSB increases Vt (more reversebias)

SCI decreases Vt (Standby -> Sle Leakage reduction

0.1mA active -> 10nA sleep (2.8v V

4 orders of magnitude

Dynamically tunes Vt(by matchin

leakage current monitor) tominimize Vt variation

J Kao ICCAD 2002


55/74

VTCMOS Pros/Cons

PROS: Significant standby leakage reduction Memory elements retain state

No transistor sizing/ partitioning required Dynamically tunable Vt during runtime

CONS:

Requires expensive triple well process Body factor decreases with scaling

J Kao ICCAD 200

DVS vs DVTS


56/74

TSMC 250 nm BPTM 70nm( Vdd=2.5V, Vth=0.45V ) ( Vdd=0.9V, Vth=0.15V )

DVS vs. DVTS

ushik Roy, ECE, Purdue University

Speed Adaptive V CMOS


57/74

Speed Adaptive Vt CMOS

M. Miyazaki, et al, A 1.2-GIPS/W uProc Using Sp

Adapative Vt CMOS with Forward Bias, JSSC Fe2002.

Dynamically tune Vt so that critical pathspeed matched clock period

Reduces chip-to-chip parameter variation

Reverse bias:Operate only as fast as necessary (reduces ex

active leakage)

Forward bias:

Speeds up slow chips

Standby leakage with maximum reverse bi Also known as Adaptive Body Biasing (A

J Kao ICCAD 200

Adaptive Supply & Body Bias (ASB)


58/74

0

0.1

0.2

0.3

0.1 0.3 0.5 0.7 0.9

VDD [Volts]

P

ower[Watts

]

Ptotal

Pdynamic

Pleakage

Minimum point where

slope(leak) = - slope(dyn)

Power vs. VDD (implicit Vt) for fixed frequency

Dynamically tune both VDD & Vt as operating conditions change Trade-off between dynamic power (VDD knob), leakage power (Vt)

Minimize total ACTIVE power consumption

(higher active leakage current at expense of lowering dynamic power)

Adaptive Supply & Body Bias (ASB)

M. Miyazaki, et al, A 175mV Multiply-Accumulate Unit using an AdaptiveSupply Voltage and Body Bias (ASB)Architecture, ISSCC February 2002.

J Kao ICCAD 2002

Optimal VDD/VT Selection


59/74

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0.1 0.6 1.1 1.6 2.1

VDD [Volts]

Vt[Volts]

50 Mhz100 Mhz

150 Mhz

200 Mhz

250 Mhz

Vt-VDD Constant Performance Locus

0

0.5

1

1.5

2

2.5

3

0.1 0.6 1.1 1.6 2.1

VDD [Volts]

Power[Watts]

50 Mhz

100 Mhz150 Mhz

200 Mhz

250 Mhz

Minimum Power Point (Vt implicit)

Optimal VDD

& Vt

target changes with operating conditions

e.g. Varying Workload

Low frequencies high Vt more optimal

reduce leakage at expense of increased dynamic

High Frequencies low VDD more optimal

reduce dynamic at expense of increased leakage

Optimal VDD/VT Selection

J Kao ICCAD 200

V /V Optimi ation s DVS


60/74

0

0.5

1

1.5

2

2.5

3

0 50 100 150 200 250

Frequency [Mhz]

Power[Watts]

DVS (Vt=0.35)

DVS (Vt=0.14)

Optimal VDD/Vt Scaling

0

0.05

0.1

0.15

0.2

0.25

0 50 100 150

Fre quency [M hz]

Power[Watts]

DVS (Vt=0.35)DVS (Vt=0.14)

Optimal VDD/V tScaling

VDD/VT Optimization vs. DVS

Dynamic voltage scaling ignores VT influence DVS is sub-optimal over the frequency range

J Kao ICCAD 200

ASB A hit t


61/74

Variable

DC/DC ABB Generator

DSPCORE

VDD

VBBN

Powermonitor

Controller Vt Controller

ASB Architecture

VBBP

Decouple VDD/ Vt tuning loops

ABB (Auto Body Biasing)generator chooses Vt based onVDD/ Freq/ etc.

Simple VDD sweep to searchminimum active power point

Architecture ensures minimumpower for any operatingcondition

M. Miyazaki, J. Kao, A. Chandrakasan, A 175mV Multiply-Accumulate Unit using an Adaptive SupplyVoltage and Body Bias (ASB) Architecture, ISSCC February 2002.

J Kao ICCAD 20

ctive Well vs VDD Scaling


62/74

ct e e s Sca g

Reverse Body bias (Active Well) is a more effective leakage minimization technique

than VDD scaling

Total Power savings depends on ratio of leakage to total power

Vdd scaling reduces dynamic power much more than Active Well

Leakage Power (for 65nm) Total Power (for 65nm)

B. Chatterjee, et al ISLPED 2003

ackground: Active Well vs VDD Scaling


63/74

ackground: Active Well vs VDD Scaling

VDD scaling

Less effective than Active Well to reduce leakage

Causes higher degradation in performance

More effective in reducing dynamic power

Active Well

More effective in reducing leakage

Does not work with SOI

Effectiveness reducing in newer technologies but still more effective than VDD scaling till 65


otal Power and VDD Scaling


64/74

otal Power and VDD Scaling

Total Power (for 65nm)Total Power (for 130nm)

VDD scaling is very effective in current technologies to reduce dynamic power

VDD scaling is more attractive if total power is dominated by dynamic power.


Vth hopping scheme (Variable Vth)


65/74

Vth hopping scheme (Variable Vth)

K. Nose, JSSC 02Kaushik Roy, ECE, Purdue University

Vth hopping scheme


66/74

K. Nose, JSSC 02

Vth hopping scheme

aushik Roy, ECE, Purdue University

he DVTS Scheme


67/74

he DVTS Scheme

Frequency

PMOS

body bias

NMOS

ody bias

Vth

Fmax

0.9 V

2.7 V

-1.8 V

0

0.15 V

0.45 V

time


Implementation overview


68/74

Implementation overview

Schematic of the DVTS system

Charge PumpsFeedback Alg.

VCON

Counter

+

-Counter

CLK

+

SystemPMOS body bias

NMOS body bias

error[n] = Fclock[n] Fvco[n]


Forward Body-Biasing (50nm)


69/74

Previous techniques: use circuit/arch. to lower leakage

This technique: use dev/ckt/arch opt. to lower leakage

Main idea: high Vt device + forward body-biasing

0.E+00

2.E-04

4.E-04

6.E-04

8.E-04

1.E-03

0 0.2 0.4 0.6 0.8 1 1.2

Gate voltage (V)

Drain

Current(A/um) Super high Vt + FBB

Super high Vt

+ ZBB

Nominal Vt + ZBB

17%3%

Nominal Vt=270mV

Super high Vt=350


x32 Forward Body-Biased Subarray


70/74

y y

...

..

...

...

..

0.4V powersupply

SUBSL

32

32

WL0

WL31

VPW

ELL

M3

M2

M1

... MN

MA MP


Body Transition Delay Hiding


71/74

Subarray turned on ahead of time using SUBSL

Extra time for body-bias transition to complete

SUBSL

VPNWE

LL

WL

Standby activestandby

A[N-1:0]


Body Transition Energy Reduction


72/74

32KB L1 inst. cache, SimpleScalar, 500M cycles

93% of the accesses hit the same subarray in the next access:locality of reference

Transition energy wasted only in 7% of accesses

SPEC2000


95% 92%91%

96%

90%

94% 95% 93%

0%

20%

40%

60%

80%

100%

vpr

gcc

gzip

mcf

perlb

mk

vortex

bzip

2

averag

ePerc

entageofconsecutiv

e

acce

ssestosa

mesubarray

tline Performance Under Iso-Leakage0 12


73/74

SBSRAM delay penalty: 3 transistor stack

FBSRAM delay penalty: + diffusion capacitance

FBSRAM is 7.3% faster than SBSRAM under iso-leakage

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0 40 80 120 160 200Time (ps)

Diffe

rentialvo

ltage(V)

ConventionalFBSRAMSBSRAM

SenseAmp

activates

t=138ps

t=164ps

VBL

VBLB

Vdiff

t=152ps


ummary


74/74

y

Leakage is critically dependent on process and environmental variations

Leakage control through two promising techniques Power supply control

Threshold voltage control

Leakage will be the key design variable in next generation ICs

(from ibm) low power issues in chip design

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