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TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t

he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony

are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack,

ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ

Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks

of Freescale Semiconductor, Inc. All other product or service names are the property

of their respective owners. © 2011 Freescale Semiconductor, Inc.

June 2011

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore

and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a

Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc.

All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.

2

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• Introduction to Integrated Flash Controller (IFC)

• Evolution of the local bus

• Difference between eLBC and IFC

• IFC architecture

• NOR controller

• NAND controller

• GPCM controller

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• Role of IFC

− After the power is turned on, a typical system:

1. Starts execution from non-volatile memory, typically NOR/NAND

flash memory

2. Copies the code to main memory (DDRx)

3. Starts the execution from the main memory

Core

FlashU-boot/

BIOS

Main Memory

DDRx

1

Storage

ROM/Hard Drive

2

3

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• A system must be able to talk to non-volatile memory without any software configuration steps

• IFC is the controller that does this initial booting job

− IFC has three controllers:

1. NOR controller

− Standard and page mode NOR flash

− Support Booting

2. NAND flash control machine (FCM)

− NAND memory for storage

− Support Booting

3. GPCM

− Normal GPCM: Legacy, standard NOR flash

− Generic ASIC: FPGA

− No Booting

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• MPC8xx Memory Controller (1995)

• GPCM: ROM, SRAM

• UPM: DRAM

• MPC82xx Memory Controller (1998)

• GPCM

• UPM

• SDRAM controller

• Improvement: Dedicated SDRAM controller

• MPC83xx/MPC85xx Local Bus Controller (2003/2004)

• GPCM

• UPM

• SDRAM controller

• Improvement: Dedicated DDR controller supported outside of LBC

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• QorIQ P10xx/P20xx/P40xx eLBC(Enhanced LBC) (2008)

GPCM

UPM

FCM: NAND Flash Control Machine

Improvement: Remove SDRAM controller

Add NAND controller (small page, 2K page)

• QorIQ P1010 (IFC – Integrated Flash Controller) (2011)

GPCM (Normal GPCM, Generic ASIC)

NOR

FCM: NAND Flash Control Machine

Improvement: Remove UPM

Improve GPCM

Add NOR controller

Improve FCM, add 4K page support

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Machine Features IFC eLBC

NAND Flash

Support for ONFI 2.0 Yes Not sure

Error correction 4 and 8 bit 1- bit

Flexible timing control allows interfacing

with proprietary NAND devices

Yes Limited capability

Max page size 4KB 2KB

Provide cache, copy-back and multi-

plane command support

Yes No

Programmable command and data

transfer sequences

Up to 15 Up to 8

BBI page position Configurable between (2nd and

last page)

First two pages of

each block

Configurable block size constraint to

multiple of 32 pages, up to 1024 pages

Yes No

Internal SRAM size 16KB 5KB

Max boot block size for NAND flash 8KB 4KB

SRAM access while NAND operation is

on

Not-Allowed Allowed

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Machine Features IFC eLBC

NOR Flash

Compatible with latest NOR flash interface Yes No

Support True-Address Data-Muxed devices Yes No

Flexible timing control allows interfacing with variety of

NOR devices

Yes Limited capability

Other

UPM No Yes

Write protection feature Yes Minimal support

GASIC Yes No

GPCM Yes (with enhanced

timing control)

Yes

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Name IFC eLBC

Address/Data IFC_AD LAD

Address IFC_ADDR LA

Address Valid IFC_AVD LALE/LFALE

Chip Select IFC_CS_B LCS

Write Enable IFC_WE_B LWE_B

Command Latch Enable IFC_CLE LFCLE

Output Enable IFC_OE_B LOE_B

Write Protect IFC_WP_B LFWP_B

Ready/Busy IFC_RB_B/IFCTA_B LFRB_B

Buffer Control IFC_BCTL LBCTL

Parity IFC_PAR[0:1] LDP[0:1]

Parity Error IFC_PERR Not Available

Clock IFC_CLK LCLK

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• Support standard asynchronous NOR

flash

• Same as GPCM

• Support page mode NOR flash

• This is the improvement from

GPCM for higher bandwidth

• No support for synchronous

burst mode NOR flash

• Supports address data multiplexed

ADV-type NOR device

NOR Flash Type

Complexity

Pe

rfo

rma

nc

e

Standard

Page Mode

Burst Mode

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• Standard NOR flash vs. Page Mode NOR

tACC = 100 ns, tPACC = 25ns

For 16-bit interface and a 32-byte cache line read

Standard flash: 100ns x 16 = 1600 ns

Page mode: 100ns + 15*25ns= 475ns

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Numonyx M29EW family

Address is driven before CE#

Set CSORn[NOR_MODE]=0

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Numonyx P30 family

Address is driven along with ADV# assertion

Set CSORn[NOR_MODE]=1

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DQ[15:0]

A[24:1]

ADV#

OE#

WE#

CE#

WP#

RST#

WAIT

CLK

IFC_AD[0:15]

IFC_ADDR[16:24]

IFC_AVD

IFC_OE#

IFC_WE#

IFC_CS#

IFC_WP#

IFC_AD[0:15]

IFC_ADDR[16:23]

HRESET

NC

GND

IFC NOR flash

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• cfg_ifc_flash_mode

This configuration pin is on IFC_WE.

0: ADV type NOR flash

1: Normal addressing NOR flash

• If NOR is configured as boot device, hardware automatically sets:

CSORn[ADM_SHFT_MODE]=0

CSORn[ADM_SHFT]= 00111, shift by 7-bits

axi_addr 7 … 22 23 … 31

IFC_ADDR[16:24] 16 … 24

IFC_AD[0:15] 0 … 15

For example, axi_addr=0xffff1234

IFC_ADDR[16:24]=0x034

IFC_AD[0:15]=0xff89.

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• External latch is not needed for the address bus.

Address is latched internally inside NOR flash.

• IFC_ADDR[24] must be left out for the 16-bit port.

• After power on reset, CSORn[PGRD_EN] is set to 0.

Software must set this bit to enable page read mode.

• When choosing the page-mode flash, the page size must be the same as the cache line, i.e., 32 bytes.

• In order to take advantage of the page mode

- Use DMA to copy the code from NOR flash to DDR

- Enable cache

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• Overview of NAND flash• Higher-density / lower-cost than regular flash (NOR flash)

• IO device using commands to read/write

• No address bus

• Page-oriented, not suitable for random access

• Possible bit error

• Usually a certain number of blocks are marked bad by the manufacturer

• During the operation, more blocks can go bad

• ECC is a must

• No execute in place (XIP)

• Long wait time for random address

• Possible bit error only known after the whole page read and ECC

• check

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• Support x8/x16 NAND devices

• Device can boot from x8 or x16 with 512B, 2K, 4K-page size

• ONFI-2.0 asynchronous interface with mandatory commands

• BCH coding for 4/8 bit error correction per block

• Page size: Support 512 bytes, 2K and 4K

• Advance NAND commands like cache, copy-back, and multi-plane programming

• Configurable block size, from 32 to 2048 pages per block

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• Market trend toward NANDs with bigger page sizes

eLBC: 512 Bytes, 2K page

IFC: 512 Bytes, 2K page, 4K page

• Increase in flash density with higher number of ECC bits per page

eLBC: Hamming code, Detect 2-bits error. Correct 1-bit error.

IFC: 4-/8-bit BCH. Detect & correct 4-/8-bits error per 520/528 bytes sector

• Programming model change

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• CSPRn, AMASKn, CSORn

CSPRn: Base Address, Port Size, Controller Select

AMASKn: Bank Size

CSORn: ECC mode/enable, Page size, Row Address Length,

Spare region size

• FTIM0-3_CSn

Control the AC timing of the NAND interface

• ROW0-3, COL0-3

For controlling the address value during the address phase

• NAND_FCR0-1

For controlling the command value during the command phase

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• NAND_BC

Byte count. If 0, it means whole page plus the spare region

• NAND_CSEL

Which IFC_CSn is asserted during the NAND operation?

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• NAND_FIR0-2 • 0x00: NOOP

0x01~0x04: CA0-3

0x05~0x08: RA0-3

0x09~0x10: CMD0-7

0x11~0x18: CW0-7

0x19: WBCD

0x1A: RBCD

0x1B: BTRD

0x1C: RDSTAT

0x1D: NWAIT

0x1E: WFR

0x1F: SBRD

0x20: UA

0x21: RB

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• NANDSEQ_STRT

Setting to 1 triggers the operation. It is self-cleared after the operation.

NAND_FIR_STRT: Execute the sequence in the NAND_FIR0-2

AUTO_ERS: Automatic erase operation. {CW0, RA0, CMD1, NOOP}

AUTO_PGM: Automatic program. {CW0, CA0, RA0, WBCD, CMD1, NOOP}

AUTO_CPB: Automatic copy back.

{CW0, CA0, RA0, CMD1, CW2, CA1, RA1, CMD3,CW4, RDSTAT, NOOP}

AUTO_RD: Automatic read. 512byte page: {CW0, CA0, RA0, RBCD, NOOP}

2K/4K page: {CW0, CA0, RA0, CMD1, RBCD, NOOP}

AUTO_STAT_RD: Automatic status read. {CW0, RDSTAT, NOOP}

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For eLBC

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• GPCM supports two modes:

Normal GPCM, Generic ASIC

• To enable GPCM and select mode

CSPRn[MSEL]: 0b10 for GPCM

CSORn[GPMODE]: 0 for Normal GPCM

1 for Generic ASIC

• Normal GPCM is similar to the eLBC GPCM with the new programming model

• Generic ASIC is a new function

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• Normal GPCM can be used to generate standard NOR flash interface compatible control signals.

• ALE timing controlled by FTIM0_CSn

TACSE: Address to CS assertion

TEADC: Pulse width of ALE

TEAHC: ALE to address hold time

• WE timing for read controlled by FTIM2_CSn

TCS: CS to WE assertion time

TWP: WE pulse width

TCH: WE negation to CS negation

GPCM Write

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• ALE timing controlled by

FTIM0_CSn

TACSE: Address to CS

assertion

TEADC: Pulse width of ALE

TEAHC: ALE to address hold

time

• OE timing for read controlled by

• FTIM1_CSn

TACO: CS to OE time

TRAD: OE pulse width

GPCM Read

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• Option for external termination by IFCTA

CSORn[RGETA], CSORn[WGETA]

0: Terminated by the internal TRAD counter for the read or TWP for the

write

or IFCTA if it is asserted earlier than the internal timer expiration

1: Only terminated by the assertion of IFCTA, not the internal timer.

• This feature is useful if the response time is variable.

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31

• A simple interface useful for talking to FPGA

• IFC supports the following features on GASIC interface:

• Support for x8/16 bit device

• Address and Data are shared on AD I/O bus. Dedicated address pins are not used

• Following Address and Data sequences will be supported on I/O bus

• 16-bit I/O: AADD

• 8-bit I/O : AAAADDDD

• Configurable Even/Odd Parity on Address/Data bus supported

• Parity Error detection supported

• GASIC interface does not support:

• Boot from GASIC not supported

• Burst transaction not supported

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34

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• Questions

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