fpga defect tolerance: impact of granularity anthony yuguy lemieux december 14, 2005

FPGA Defect Tolerance: Impact of

GranularityAnthony YuAnthony Yu Guy LemieuxGuy Lemieux

December 14, 2005December 14, 2005

2Field-Programmable Technology (FPT) '05

OutlineOutline

Introduction and motivationIntroduction and motivation Previous worksPrevious works New architecturesNew architectures

Coarse-grain redundancy (CGR)Coarse-grain redundancy (CGR) Fine-grain redundancy (FGR)Fine-grain redundancy (FGR)

Experimentation ResultsExperimentation Results ConclusionsConclusions


Introduction and Introduction and MotivationMotivation

Scaling introduces Scaling introduces new new typestypes of defectsof defects

Smaller feature sizes Smaller feature sizes susceptible to susceptible to smaller smaller defectsdefects

Expected resultsExpected results Defects per chip increasesDefects per chip increases Chip yield declinesChip yield declines

FPGAs are mostly FPGAs are mostly interconnectinterconnect

FPGAs must tolerate FPGAs must tolerate multiple interconnect multiple interconnect defectsdefects to improve yield to improve yield (and $$$)(and $$$)


General Defect Tolerant General Defect Tolerant TechniquesTechniques

Defect-tolerant techniques minimize Defect-tolerant techniques minimize impact (cost) of manufacturing defectsimpact (cost) of manufacturing defects

FPGA defect-tolerance can be loosely FPGA defect-tolerance can be loosely categorized into three classes:categorized into three classes: Software Redundancy – use CAD tools to map Software Redundancy – use CAD tools to map

around the defectsaround the defects Hardware Redundancy – incorporate spare Hardware Redundancy – incorporate spare

resources to assist in defect correction (eg. resources to assist in defect correction (eg. Spare row/column)Spare row/column)

Run-time Redundancy – protection against Run-time Redundancy – protection against transient faults such as SEUs (eg. TMR)transient faults such as SEUs (eg. TMR)


Previous work – 1 – XilinxPrevious work – 1 – Xilinx Xilinx’s Defect-Tolerant ApproachXilinx’s Defect-Tolerant Approach

Customer (knowingly) purchases “less that perfect” Customer (knowingly) purchases “less that perfect” partsparts

Customer gives Xilinx configuration bitstreamCustomer gives Xilinx configuration bitstream Xilinx tests FPGA devices against bitstreamXilinx tests FPGA devices against bitstream

Sells FPGA parts that “appear” perfectSells FPGA parts that “appear” perfect Defects avoid the bitstreamDefects avoid the bitstream

Limitation:Limitation: Chips work only with given bitstream – no changes!Chips work only with given bitstream – no changes!


Previous work – 2 – Previous work – 2 – AlteraAltera

Altera’s Defect-Tolerant ApproachAltera’s Defect-Tolerant Approach Customer purchases “seemingly perfect” partsCustomer purchases “seemingly perfect” parts

Make defective resources inaccessible to Make defective resources inaccessible to useruser

Coarse-grain architectureCoarse-grain architecture Spare row and column in array (like memories)Spare row and column in array (like memories)

Defective row/column must be bypassedDefective row/column must be bypassed Use the spare row/column insteadUse the spare row/column instead

Limitation:Limitation: Does not scale well (multiple defects)Does not scale well (multiple defects)


ObjectiveObjective ProblemProblem

FPGA yield is on decline because of aggressive FPGA yield is on decline because of aggressive technology scalingtechnology scaling

Proposed SolutionsProposed Solutions Defect-tolerance through redundancyDefect-tolerance through redundancy

Important ObjectivesImportant Objectives Interconnect defects important (dominates area)Interconnect defects important (dominates area) Tolerate multiple defects (future trend)Tolerate multiple defects (future trend) Preserve timing (no timing re-verification)Preserve timing (no timing re-verification) Fast correction time (production use)Fast correction time (production use) Understand the factors that influence yieldUnderstand the factors that influence yield

BackgroundBackground


Island-style FPGAIsland-style FPGA


Directional Switch BlockDirectional Switch Block

Course-grain Course-grain Redundancy Redundancy

(CGR)(CGR)


Coarse-grain Coarse-grain Redundancy (CGR)Redundancy (CGR)

Row

Dec

oder

Fault Free

Spare Row

Wire Extensions

Faulty

Defect

Row

Dec

oder

BypassedRow

F. Hatori et al., “Introducing Redundancy in Field Programmable GateArrays,” presented at Custom Integrated Circuits Conference, 1993.


So…what’s wrong with it?So…what’s wrong with it?

Spare Row and Column

0

0.2

0.4

0.6

0.8

1

1.2

1 10

Number of Defects

Yie

ld

32x32

64x64

128x128

256x256


Improving yield for CGR –Improving yield for CGR –Adding Adding Multiple GlobalMultiple Global

SparesSpares Add multiple Add multiple

globalglobal spare to spare to traditional CGRtraditional CGR

Global spares can Global spares can be used to repair be used to repair any defective any defective row/column in the row/column in the arrayarray

Wire extensions Wire extensions are now longerare now longer


Yield Impact of Multiple Global Yield Impact of Multiple Global SparesSpares

Global Spare Rows+Columns (32x32)

0

0.2

0.4

0.6

0.8

1

1.2

1 10Number of Defects

Yield

Baseline2 Global4 Global


Increasing Area+Delay Increasing Area+Delay OverheadOverhead

1 GLOBAL SPARE

2 GLOBAL SPARES

4 GLOBAL SPARES MAY BE IMPRACTICAL

!!!

NO SPARES

MORE SPARES MORE MUX OVERHEAD IN EVERY SWITCH

ELEMENT


Improving yield for CGR –Improving yield for CGR –Adding Adding Multiple LocalMultiple Local

SparesSpares Divide FPGA into Divide FPGA into

subdivisionssubdivisions

Each subdivision has Each subdivision has locallocal spare(s)spare(s)

DistributesDistributes spares across spares across chipchip Reduces mux area overheadReduces mux area overhead

(of Global scheme)(of Global scheme)

Limitation:Limitation: Spare(s) can only repair defect Spare(s) can only repair defect

withinwithin the subdivision the subdivision


Yield Impact of Multiple Local Yield Impact of Multiple Local SparesSpares

(not as good as Global with same # (not as good as Global with same # spares)spares)

Local Spare Rows+Columns (32x32)

0

0.2

0.4

0.6

0.8

1

1.2

1 10Number of Defects

Yield

Baseline2 Global4 Global2 Sub, 1 Spare4 Sub, 1 Spare

Fine-grain Fine-grain Redundancy Redundancy

(FGR)(FGR)


Fine-grain Redundancy Fine-grain Redundancy (FGR) – Defect Avoidance (FGR) – Defect Avoidance

by Shiftingby ShiftingDefectSpare

a) Original b) Corrected

+1

+1 -1-1

-1+1


Defect-tolerant Switch Defect-tolerant Switch BlockBlock

-1 0-2

+1 0+2

-10

-2

+10

+2

-1 0-2

+1 0+2

-10

-2

+10

+2

omux

imux

a) Original b) Defect-tolerant


Switch Implementation Switch Implementation OptionsOptions

• Several detailed implementations are possible• Trade off area / delay / yield(repairability)


Minimum Fault-free Radius Minimum Fault-free Radius (MFFR)(MFFR)


Experimentation ResultsExperimentation Results

Switch implementationSwitch implementation Array sizeArray size Wire lengthWire length AreaArea SummarySummary


Switch ImplementationSwitch Implementation

* Assumes all bridging defects


Fixed Array Size (32x32) – Fixed Array Size (32x32) – Global SparingGlobal Sparing


Fixed Array Size (32x32) – Fixed Array Size (32x32) – Local SparingLocal Sparing


Increasing Array SizeIncreasing Array Size


Yield for Varying Wire Yield for Varying Wire LengthLength


Estimated Area overhead at Estimated Area overhead at equal yield (80%)equal yield (80%)

* CGR-G1 can only tolerate 1-2 defects


Limitations of Study & Limitations of Study & ArchitecturesArchitectures

Logic and power/ground shorts were Logic and power/ground shorts were not considerednot considered

Assumed that all defects are randomly Assumed that all defects are randomly distributeddistributed

Assumed that all defects can be Assumed that all defects can be corrected with a single row/columncorrected with a single row/column

Switch area was not accounted for our Switch area was not accounted for our yield modelyield model

Area results for CGR are Area results for CGR are approximatedapproximated


ConclusionsConclusions

CGR CGR is effective for 1 or 2 defects effective for 1 or 2 defects FGR meets desired objectives:FGR meets desired objectives:

Tolerates Tolerates multiplemultiple randomly randomly distributed defectsdistributed defects

Defect correction Defect correction does not perturb does not perturb timingtiming

Tolerates an Tolerates an increasing numberincreasing number of of defects as array size increasesdefects as array size increases

Correction can be applied Correction can be applied quicklyquickly

Thank you!Thank you!

[email protected]@ece.ubc.ca


SummarySummary As the density of FPGAs increase, they becoming As the density of FPGAs increase, they becoming

in susceptible to manufacturing defectsin susceptible to manufacturing defects Fault-redundant techniques alleviate this Fault-redundant techniques alleviate this

growing problemgrowing problem Depending on the desired level of protection, we Depending on the desired level of protection, we

can apply different techniquescan apply different techniques At low defect rates, the spare row and column At low defect rates, the spare row and column

approach has lower overhead than the fine-grain approach has lower overhead than the fine-grain approachapproach

At large array sizes, the spare row and column At large array sizes, the spare row and column approach requires more area overhead to approach requires more area overhead to tolerate the same number of defects as the fine-tolerate the same number of defects as the fine-grain approachgrain approach

fpga defect tolerance: impact of granularity anthony yuguy lemieux december 14, 2005

Documents

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perfect defects

results defects

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