fpga-based dynamic duty cycle and frequency controller for ... · generator electronic load...

1 / 48 Sanghyeon Park, SUPER Lab, Stanford University, USAMay 21, 2018 IPEC-Niigata 2018

FPGA-basedDynamic Duty Cycle and Frequency Controller

for a Class-E2 DC-DC Converter

May 21st, 2018

Sanghyeon Park and Juan Rivas-Davila

[email protected]

SUPER Lab, Stanford University, USA


Basic structure of ac-dc converters

60Hz,

110V

Rectifier

Unregulated

DC DC-DC

Converter

Regulated

DC

galvanic

isolation


The scope of this work

60Hz,

110V

Unregulated

DCRegulated

DCDC-DC

ConverterRectifier

galvanic

isolation


Class-E2 dc-dc converter :It consists of a class-E inverter (left) and a class-E rectifier (right).

Class-E Inverter

a

Class-E RectifierLsLinv Lrect

Cinv Crect

VoutVin

Cs

Q D

Iout

[1] N. O. Sokal and A. D. Sokal, "Class E-A new class of high-efficiency tuned single-ended switching power amplifiers," IEEE Journal of

Solid-State Circuits, vol. 10, no. 3, pp. 168-176, Jun 1975.

[2] R. Zulinski and J. Steadman, "Class E Power Amplifiers and Frequency Multipliers with finite DC-Feed Inductance," IEEE Transactions

on Circuits and Systems, vol. 34, no. 9, pp. 1074-1087, September 1987.

[3] M. K. Kazimierczuk and J. Jozwik, "Resonant DC/DC converter with class-E inverter and class-E rectifier," IEEE Transactions on

Industrial Electronics, vol. 36, no. 4, pp. 468-478, Nov 1989.


Class-E Inverter Vin = 80 V

a

Class-E Rectifier Vout = 12 V

Linv

Cinv

Vin

Q

sinusoidal current Is

Iin

Lrect

Crect

Vout

D

Iout


Class-E2 dc-dc converter : Class-E topology achieves zero-voltage and zero-dv/dt switching.

On

Off

On

Off



a


Linv

Cinv

Vin

Q


Iin

Lrect

Crect

Vout

D

Iout


20 V

Class-E2 dc-dc converter :The major downside is the circuit’s sensitivity to input and output voltages.

Lossy switching



a


Linv

Cinv

Vin

Q


Iin

Lrect

Crect

Vout

D

Iout


160 V

Class-E2 dc-dc converter :The major downside is the circuit’s sensitivity to input and output voltages.

Lossy switching


Previous works : Resistance compression networkY. Han, O. Leitermann, D. A. Jackson, J. M. Rivas and D. J. Perreault, "Resistance Compression Networks for Radio-

Frequency Power Conversion," IEEE Transactions on Power Electronics, vol. 22, no. 1, pp. 41-53, Jan. 2007.


Previous works : Consistant zero-crossing timingL. Roslaniec, A. S. Jurkov, A. A. Bastami and D. J. Perreault, "Design of Single-Switch Inverters for Variable Resistance/Load

Modulation Operation," IEEE Transactions on Power Electronics, vol. 30, no. 6, pp. 3200-3214, June 2015.


Proposed method : Dynamic duty cycle and frequency

S. Park and J. Rivas, "Duty Cycle and Frequency Modulations in Class-E DC-DC Converters for Wide Input and Output

Voltage Ranges," IEEE Trans. Power Electronics, in press.


Class-E2 dc-dc converter implementation for testing

Crect

Vout

Lp' Ls

k'

Cinv /n2

nVin

Lm

dc blocking cap

Linv Lrect

Cinv Crect

VoutVin is equivalent to

Class-E Inverter Class-E Rectifier

Class-E Inverter Class-E Rectifier

We implement

this structure.

S. Park and J. Rivas-Davila, "Isolated resonant DC-DC converters with a loosely coupled transformer," 2017 IEEE 18th

Workshop on Control and Modeling for Power Electronics (COMPEL), Stanford, CA, 2017.


Lp

Cinv

Crect

gate driving signal

Ls

Q

D

Cout

Cin

Vin

Vout

gatebuffer








675/48

Litz wire

GaN

transistor(GS66502B)

Si diode(MBR5H100MFS)





Lp = 2000 nH

Ls = 499 nH

k = 0.26

Cinv = 3 nF

Crect = 6 nF


Experimental setup for testing dynamic duty cycle and frequency control

signalgenerator

electronicload

oscilloscope

6V gate signalpower supply

Vin power supply

dc-dcconverter

thermalcamera




Measured waveforms of the voltage across the inverter transistor : It maintains zero-voltage and zero-dv/dt switching for Vin = 80-200 V.




Measured waveforms of the voltage across the rectifier diode : It maintains zero-voltage and zero-dv/dt switching for Vin = 80-200 V.






Inverter transistor duty cycletheoreticalexperimental

The d-f modulation strategy calls for a dedicated controller design.




Inverter transistor duty cycletheoreticalexperimental


Switching frequencytheoreticalexperimental




Inverter transistor duty cycle

experimental


We need a controller that changes

the duty cycle and frequency of

the gate driving signal,

depending on the in/out voltages.

Switching frequency

experimental



Load

variation



On-off control for output

voltage regulation under

the load variation

on on on

offoff off

Load

variation



Vin = 80 V–200 V Vout = 5 V–20 V



the load variation

on on on

offoff off

Load

variation





the load variation

on on on

offoff off

Load

variation

d-fmodulation to minimize the

switching loss under input / output

voltage variations

Vin = 80 V–200 V Vout = 5 V–20 V

gate drivingsignal


The controller prototype using Mojo v3 FPGA

Mojo v3 FPGA development board

- Xilinx Spartan 6 FPGA

- ADC with 8 input channels

- Clock speed up to 300 MHz

- 84 digital input/output pins


The controller prototype using Mojo v3 FPGA

Mojo v3 FPGA development board

- Xilinx Spartan 6 FPGA

- ADC with 8 input channels

- Clock speed up to 300 MHz

- 84 digital input/output pins

Vout to ADC input

Vin to ADC input

User-selectable

output voltage

Gate driving signal

- on-off controlled

- d-f modulated


⟨⟨ lookup_table ⟩⟩

Vin,Vout LUT

sw_period

duty_cycle

Design details of the FPGA-based controller



Vin,Vout LUT

sw_period

duty_cycle

⟨⟨ pwm ⟩⟩

counterduty_cycle

sw_period

gate_drv_sig



Vout < Vout,target ?

gate_drv_sigon-off gate driving signal

⟨⟨ on_off_ctrl ⟩⟩


Vin,Vout LUT

sw_period

duty_cycle

⟨⟨ pwm ⟩⟩

counterduty_cycle

sw_period

gate_drv_sig



Schematic of the controller and peripheral circuits

Cinv

VinCrect

Lp Ls

k

Q

D

Cin

+

Vout

Cout

+

5-20V

2.5-10V

unity-gain

isolation

amplifier

80-200V

1.3-3.3VFPGA

controller

Vout selection bits

gate driving signal


Controller implementation

extra Cout

isolation amplifier

Vout

Vin gate driving signal

FPGA board

Vout,target selection switch

ADC input ports(under the controller board)

controller board


electronicload

oscilloscope

aux power supplies

Vin power supply

thermalcamera

Experimental setup for testing the controller

dc-dcconverter controller


Class-E2

dc-dcconverter

controller

Experimental setup for testing the controller


Step change in the output voltage

output voltage5 V/div

gate driving signal5 V/div

voltage across rect. diode20 V/div

voltage across inv. transistor100 V/div

Vin = 120 V, Rload = 10 Ω

Vout from 5 V to 9 V


Step change in the output voltage : closer look


gate driving signal5 V/divd = 0.10, f = 2.07 MHz



horizontal timescale200 ns/div

Vin = 120 V, Vout = 5 V








Vin = 120 V, Vout = 9 V








Vin = 120 V, Vout = 12 V








Vin = 120 V, Vout = 20 V


Step change in the load resistance from 7 Ω to 30 Ω





Vin = 120 V, Vout = 12 V


Efficiency at different output powers

Vin = 80 V Vin = 120 V



Vin = 80 V Vin = 120 V

Synchronous rectification and

a low-μ magnetic core achieve

95.71 % efficiency (80 V-to-20 V conversion).S. Park and J. Rivas,

"Isolated Resonant

DC-DC Converters

with a Loosely

Coupled Transformer,

" in Control and Modeli

ng for Power Electroni

cs (COMPEL), Jul.

2017.



Vin = 160 V Vin = 200 V


Comparison with and without dynamic duty cycle and frequency: Efficiency drops when duty cycle and frequency are fixed

instead of being dynamically changed (Rload = 20 Ω)

Vin = 120 V, Vout = 5-20 VVin = 80-200 V, Vout = 12 V


inverter transistor: 35 °C

rectifier diode: 31 °C

inverter transistor: 29 °C

rectifier diode: 31 °C

invertertransistor

rectifierdiode

Comparison with and without dynamic duty cycle and frequency

Reference picture

Vin = 120 V, Vout = 12 V, Rload = 20 Ω

Normal operationWhen d and f aremistuned to Vout of 5 V

efficiency = 77 % efficiency = 74 %


Comparison with and without dynamic duty cycle and frequency

Vin = 120 V, Vout = 12 V, Rload = 20 Ω Lossy switching




gate driving signal, 5 V/div,mistuned to Vout of 5 Vd = 0.10, f = 2.07 MHz



►Class-E2 dc-dc converter loses its zero-voltage and zero-dv/dt switching

when the input and output voltage changes.

►We found that we can solve the problem by changing the gate driving

signal’s duty cycle and frequency.

►We developed a controller that reads the input / output voltages and drives

the transistor with appropriate duty cycle and frequency.

►The controller regulates the output voltage by on-off control scheme.

Summary

fpga-based dynamic duty cycle and frequency controller for ... · generator electronic load...

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