fourth-edition index

863

INDEX

Note: Page numbers for defining references are given in color.

&*%$#@! (ceiling function) 53∆ICC 145∨ (vee) 187∧ (wedge) 186!$ (ABEL XNOR) 245! (ABEL NOT) 245, 246, 397! (Verilog logical NOT) 304!= (ABEL inequality) 253!= (Verilog logical inequality) 304! vs. ~, Verilog 304# (ABEL OR) 245# (Verilog delay specifier) 330# (Verilog parameter substitution)

309$ (ABEL XOR) 245$ (Verilog built-in functions and

tasks) 293, 329% (Verilog modulus) 301&& (Verilog logical AND) 304& (ABEL AND) 245& (Verilog AND) 296& (VHDL concatenation operator)

265, 751-> (ABEL test-vector operator) 253-> (ABEL unclocked truth-table

operator) 250

- (ABEL subtraction) 253- (Verilog subtraction) 301- (VHDL subtraction) 488* (ABEL multiplication) 497* (optional sections) xvi* (Verilog multiplication) 301* (VHDL multiplication) 502∗ suffix 544, 546+ (ABEL addition) 253, 719+ (Verilog addition) 301+ (VHDL addition) 488⊕, Exclusive OR symbol 234, 447.AP suffix, ABEL 612.AR suffix, ABEL 612.C. symbol, ABEL 622.CLK suffix, ABEL 612.FB suffix, ABEL 616, 617.OE suffix, ABEL 424, 612.PIN suffix, ABEL 617.Q suffix, ABEL 617.SP suffix, ABEL 612.SR suffix, ABEL 612.X. symbol, ABEL 245/ (Verilog division) 301/= (VHDL inequality) 276, 466/ prefix, ABEL 244:, in bus name 359

:= (ABEL clocked assignment) 612

:= (VHDL variable assignment) 280

:> (ABEL clocked truth-table operator) 613

< (ABEL less than) 253< (Verilog less than) 304< (VHDL less than) 276<< (Verilog shift left) 301<= (ABEL less than or equal) 253<= (Verilog less than or equal) 304<= (Verilog nonblocking

assignment) 315<= (VHDL less than or equal) 276<= vs. =, Verilog 316= (ABEL unclocked assignment)

246, 248= (Verilog blocking assignment)

315= (VHDL equality) 276, 466== (ABEL equality) 253== (Verilog logical equality) 304= vs. <=, Verilog 316> (ABEL greater than) 253> (Verilog greater than) 304> (VHDL greater than) 276

2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material isprotected under all copyright laws as they currently exist. No portion of this material may be

reproduced, in any form or by any means, without permission in writing by the publisher. For exclusive use of adopters of the book Digital Design Principles and Practices,

Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

864 Index

>= (ABEL greater than or equal) 253

>= (Verilog greater than or equal) 304

>= (VHDL greater than or equal) 276

>> (Verilog shift right) 301?: (Verilog conditional operator)

305, 311, 431, 445, 492? bit value, Verilog 323@ALTERNATE directive, ABEL 245@CARRY directive, ABEL 488[] (Verilog part-select operator)

752^ (Verilog XOR) 296^~ (Verilog XNOR) 296^b binary prefix, ABEL 253^h hexadecimal prefix, ABEL 253_L suffix 348, 387, 390{} (ABEL equation-block

delimiters) 250{} (Verilog concatenation operator)

300, 752| (Verilog OR) 296|| (Verilog logical OR) 304~ (Verilog NOT) 296~^ (Verilog XNOR) 296~ vs. !, Verilog 304’ prefix, as in ’139 387

00 30 and 1 3, 7, 8, 25, 80, 86, 185,

348, 8040s catching 539, 5400-set 2300x prefix 291 310’s complement 3510’s-complement representation 501076, IEEE VHDL standard 2701164, IEEE standard logic package

261, 265, 266, 270

128V64 84016V8C 694, 70316V8R 703, 74016V8S 703, 7031-bit parity code 601-out-of-10 code 511-out-of-m code 3841-out-of-n code 55, 5621s catching 539, 5401s-counting machine 5661-set 23020V8 706, 71922V10 7062421 code 5028C010 81128C040 81128C256 81128C64 811, 8282n-to-n encoder 4082-to-4 decoder 384, 389, 3903-to-8 decoder 386, 387, 3904000-series CMOS 1414B5B code 7794-to-16 decoder 3904-to-2 encoder 41254 prefix 99, 14154-series parts 143, 1675-to-32 decoder 3905-variable Karnaugh map 235, 5645-V-tolerant inputs 153, 1545-V-tolerant outputs 1546-variable Karnaugh map 2367497 79374AC (Advanced CMOS) 128, 14874ACT (Advanced CMOS, TTL

compatible) 128, 135, 14874ACT74 68674AHC (Advanced High-speed

CMOS) 14374AHCT (Advanced High-speed

CMOS, TTL compatible) 143

timing 366, 367

74ALS (Advanced Low-power Schottky TTL) 166

74ALS74 77574ALVC164245 15574AS (Advanced Schottky TTL)

16674F (Fast TTL) 16674F373 77474F374 77474F74 686, 77474FCT (Fast CMOS, TTL

compatible) 128, 135, 149timing 367

74FCT-T (Fast CMOS, TTL compatible with TTL VOH) 149

74HC (High-speed CMOS) 14274HCT (High-speed CMOS, TTL

compatible) 142timing 366, 367

74HCT00 36074HCT04 36074LS (Low-power Schottky TTL)

166, 689timing 366, 367

74LS00 166, 36074LS138 36874LS139 36874LS74 534, 540, 611, 773, 774,

77574LS74 circuit 535, 61174LS86 36874 prefix 99, 14174S (Schottky TTL) 166, 49374S174 77474S373 77474S374 77474S74 77474-series parts 141, 143, 34274VHC (Very High-speed CMOS)

14374VHC1G08 1474VHCT (Very High-speed CMOS,

TTL compatible) 143




Index 865

74x00 143, 166, 361timing 366

74x02 361timing 366

74x03 36174x04 361, 4

timing 36674x08 361

timing 36674x10 361, 2

timing 36674x109 540, 68674x11 361

timing 36674x138 143, 149, 367, 386, 387,

387–395, 399, 403, 418, 424, 452, 717

74x139 389, 440, 813timing 367

74x14 361timing 366

74x148 411–41374x151 433–438

timing 36774x153 436

timing 36774x157 434–436, 440

timing 36774x160 71674x161 71674x162 716, 72574x163 713–719, 725, 765, 2, 474x164 474x16540 42274x166 274x169 716, 72574x174 692

timing 68474x175 691

timing 68574x181 482–48474x182 367, 485–487

timing 367

74x194 730–730, 738, 740, 76574x20 361

timing 36674x21 361

timing 36674x240 42274x241 76574x245 42374x251 436, 43674x257 43674x266 36174x27 361, 4

timing 36674x273

timing 68574x280 449, 450, 451, 454, 455,

456timing 367

74x283 460, 461, 479–482timing 367

74x30 361timing 366

74x32 361timing 366

74x32244 42274x373 527, 693

timing 68574x374 527, 692, 717, 765

timing 68574x375 68674x377 693, 717, 765, 767, 4

timing 68574x381 484, 492–493

timing 36774x382 48474x540 422, 43174x541 421, 45074x682 463, 463, 466, 470

timing 36774x74 686

timing 68474x83 47974x85 460, 461–463, 470–473

74x86 361, 448, 458, 738timing 366

74x999 47774x prefix 144, 38782S100 3738421 code 508B10B code 56, 71, 748-input priority encoder 4118-to-3 encoder 4089s’ complement 38

Aa, asynchronous event frequency

773ABEL (Advanced Boolean

Equation Language) 9, 15, 238, 243–255

!$ (XNOR) 245! (NOT) 245, 246, 397!= (inequality) 253# (OR) 245$ (XOR) 245& (AND) 245-> (test-vector operator) 253-> (unclocked truth-table

operator) 250- (subtraction) 253* (multiplication) 497+ (addition) 253, 719.AP suffix 612.AR suffix 612.C., clock edge 622.CLK suffix 612.FB suffix 616, 617.OE suffix 424, 612.PIN suffix 617.Q suffix 617.SP suffix 612.SR suffix 612.X. symbol 245/ prefix 244:= (clocked assignment) 612< (less than) 253




866 Index

ABEL (continued)<= (less than or equal) 253== (equality) 253= operator 248= unclocked assignment 246> (greater than) 253>= (greater than or equal) 253@ALTERNATE directive 245@CARRY directive 488^b binary prefix 253^h hexadecimal prefix 253{} (equation-block delimiters)

250addition 719attribute suffix 424, 612, 616buffer keyword 248case sensitivity 244case statement 614clocked assignment operator, :=

612clocked truth-table operator, :>

613com keyword 244comments 244compiler 244, 554constant expression 392counters 719–721current-state-variables 618device declaration 244don’t-care

input combination 251else clause 248, 614ENABLE keyword 246end statement 245equation block 250equations 245

state variable on lefthand side 614

equations statement 245goto statement 614identifier 244if statement 614

ABEL (continued)input-list 250, 253intermediate equation 247invert keyword 248istype keyword 244, 612language processor 244latches 694–697module statement 244neg keyword 248next-state-variables 618NOT prefix 244operator precedence 245other declarations 245output-list 250, 253pin declarations 244pin definitions 397pos keyword 248precedence 245property list, istype 244range 251registers 694–697reg keyword 612relation 253relational expression 253relational operators 253retain property 695set 251, 614, 618shift registers 740–748state_diagram 613state diagram 614–621state keyword 614state-machine coding style 629state-value 614state-vector 614string 244test_vectors 245test_vectors keyword 253test vectors 245, 253–255, 622title 244truth_table keyword 250truth table 250, 613

ABEL (continued)unclocked assignment operator,

= 246, 248unclocked truth-table operator,

-> 250when statement 248with statement 620

abnormal state 584, 732, 733absolute maximum ratings 153absolute maximum ratings, TTL

169AC (Advanced CMOS) 128, 148access time from address 815, 825access time from chip select 815,

826AC fanout 111AC load 116, 763ACT (Advanced CMOS, TTL

compatible) 128, 135, 148Actel Corporation 859Active-HDL xx, 337active high 348active-high clock 522active-high pin 349active level 348, 351, 352, 353,

386, 390, 399–400, 404–405active-level naming convention

348active-level suffix 355active low 348active-low clock 522active-low pin 349active mode 815active pull-up 133active region 158actual parameters, VHDL 265adders 474–487

ABEL 487–488Verilog 490–493VHDL 488–490

adding out 189, 202, 203, 476




Index 867

addition 32ABEL 719Verilog 301

address hold time 826address input 800address setup time 826adjacency diagram 605adjacent states 606advanced courses xviAdvanced Micro Devices (AMD)

508, 859after keyword, VHDL 284AHC (Advanced High-speed

CMOS) 143, 153, 154AHCT (Advanced High-speed

CMOS, TTL compatible) 143

A-law PCM 816, 820Aldec, Inc. xxAlfke, Peter 788algebraic operator 186algorithmic state machine (ASM)

664chart 664

all inclusion 553, 574almost one-hot coding 633alpha particle 58Alred, G. J. 508Alternate Mark Inversion (AMI) 72ALU 474always block, Verilog 312always keyword, Verilog 312amandarin 12ambiguous state diagram 571, 573,

576American National Standards

Institute (ANSI) 347American Standard Code for

Information Interchange (ASCII) 53

amplifier 158analog 3analog electronics 1

analog vs. digital 3–6, 7–8, 79analysis, combinational-circuit 183AND gate 6, 82, 186, 194, 210

CMOS 93symbol 346

and gate, Verilog 306AND operation 187AND-OR circuit 193, 202, 204,

208, 209, 211, 215, 226, 229AND-OR device 370AND-OR-INVERT (AOI) gate,

CMOS 94, 175Angell, R. 508anode 156ANSI (American National

Standards Institute) 347ANSI-style port declarations,

Verilog 298application-specific integrated

circuit (ASIC) 16–17, 237, 343, 543, 566, 590, 758, 763

design 22, 342, 526architecture, VHDL 257architecture-control fuses,

GAL16V8 378architecture definition, VHDL 257,

259architecture keyword, VHDL

258arguments, VHDL 265arithmetic and logic unit (ALU)

482, 759arithmetic operators, Verilog 301arithmetic shift 748array, Verilog 302array, VHDL 263

type matching 276array index, Verilog 302array index, VHDL 263array keyword, VHDL 263array literal, VHDL 264array slice, VHDL 265array type, unconstrained 265

array types, VHDL 263arrow, state-diagram 548ASCII (American Standard Code

for Information Interchange) 53

Ashenden, Peter J. 336ASIC

place-and route 242ASIC (application-specific

integrated circuit) 16–17, 237, 343, 543, 566, 590, 758, 763

ASIC design 370, 765ASIC routing 763ASM (algorithmic state machine)

664ASM chart 664assert 348asserted 3assert statement, VHDL 288assign keyword, Verilog 293,

310, 330assignment-statement sizing,

Verilog 300associative law 188asterisk (optional sections) xviasymmetric output drive 143asynchronous clear input 725asynchronous design 2asynchronous inputs, flip-flop 533asynchronous input signal 759, 767asynchronous reset, 22V10 706asynchronous signals 679, 758asynchronous SRAM 829Asynchronous Transfer Mode

(ATM) 171ATM (Asynchronous Transfer

Mode) 171Atmel Corporation 859attribute statement, VHDL 633attribute suffix, ABEL 424, 612,

616




868 Index

automatic test-pattern-generation program 625, 644, 662

auto-refresh cycle, SDRAM 839axiom 185

Bbaby from hell 5back annotator 240back-end design process 242–243Bakeman, Ken xxiiibalanced code 71bank, DRAM 834barrel shifter 516base, number system 26base, transistor 158basis step 190Baylis, John 74^b binary prefix, ABEL 253BCD (binary-coded decimal) 48BCD addition 50BCD code 384, 408BCD decoder 386begin-end block, Verilog 317begin keyword, Verilog 317begin keyword, VHDL 258behavioral description, Verilog 312behavioral description, VHDL 278behavioral design, Verilog

312–329behavioral design, VHDL 278–284behavioral specification, Verilog

292bias 39BiCMOS logic 155bidirectional bus 423bidirectional data bus 828bidirectional pins, PLD 375, 424bidirectional shift register 730big picture 23billions and billions 48, 55, 341,

509, 520, 821, 861bill of materials (BOM) 343

binary adder, serial 758binary addition 32binary-addition table 32binary-coded decimal (BCD) 48binary counter 719binary decoder 384, 440binary digit 25, 26, 80binary division 47–48binary encoder 408binary operator 189binary point 27binary prefix, ABEL 253binary radix 26binary rate multiplier 793binary subtraction 32binary-subtraction table 32binary-to-hexadecimal conversion

27binary-to-octal conversion 27binomial coefficient 49, 56, 561bipolar junction transistor (BJT)

84, 158–160bipolar logic family 85bipolar PAL devices 703bipolar PROM 810Bipolar Return-to-Zero (BPRZ) 72bipolar ROM 808biquinary code 50bird 571Birkner, John 508bistable 523–526, 590bit 26, 80bit_vector type, VHDL 260bit cell 69bit line 804bit rate 69bit select, Verilog 300bits per second 69bit time 69bit type, VHDL 260bit vector, Verilog 295, 299–302

bitwise boolean operators, Verilog 295

BJT (bipolar junction transistor) 84, 158–160

Blake, Gary 508block, Verilog 317block diagram 343, 344, 355, 357,

438, 11blocking assignment operator,

Verilog = 315blocking assignment statement,

Verilog 315, 331, 648blocking vs. non-blocking

assignments, Verilog 648, 755

Bly, Robert W. 508board-level design 22Bolton, Martin 789BOM (bill of materials) 343Boole, George 184, 229boolean, VHDL 261Boolean algebra 184, 229

See also switching algebraboolean operators, Verilog 295boolean reduction operators,

Verilog 302boolean type, VHDL 260boolean vs. logical, Verilog 304bootstrap ROM module 805borrow 32, 43, 476boundary inputs, iterative-circuit

459, 756boundary outputs, iterative-circuit

459, 756boxed comments xviiiBPRZ (Bipolar Return-to-Zero) 72bps 69branching method 221Brown, Charlie 526Brusaw, C. T. 508bubble 83, 90bubble-to-bubble logic design

351–353, 389, 390, 438, 448




Index 869

buffer 80, 350symbol 346

buffer keyword, ABEL 248buffer keyword, VHDL 259buf gate, Verilog 306bufif0 gate, Verilog 306bufif1 gate, Verilog 306bugs 5built-in gate types, Verilog 306buried flip-flops 588buried macrocell 841burst length 839burst mode 830burst-read cycle, SDRAM 838burst-write cycle, SDRAM 839bus 344–346, 358–359, 364

bidirectional 423open-drain 137

bus, open-drain 137–138bus fighting 826bus holder circuit 690, 788business practices 3bus transceiver 423, 424, 431BUT (function) 233BUT flop 674BUT gate 233, 511butification 512byte 28

CC 10C++ 10CAD See computer-aided designCadence Design Systems 290CAE (computer-aided engineering)

9See also computer-aided design

call, Verilog function 327call, Verilog task 328call, VHDL function 265

call, VHDL procedure 269canonical product 198, 205, 210,

222canonical sum 198, 199, 205, 210,

214Cantoni, Antonio 789capacitance, stray 115capacitive load 115, 116, 365, 370capacitive loading 170capacitors, decoupling 124capacitors, filtering 124carburetor 4car heater 521carpet 113carry 32, 43carry generate 478, 492carry lookahead 478carry-lookahead adder 479carry out 474carry propagate 478, 492carry-save addition 496cascaded elements 680cascaded synchronizers 777cascading inputs, comparator 461cascading inputs, iterative-circuit

459, 756cascading outputs, iterative-circuit

459, 756case keyword, Verilog 321case keyword, VHDL 282case sensitivity 354

ABEL 244Verilog 293VHDL 258

case statement, ABEL 614case statement, Verilog 310, 321,

404full 322parallel 321

case statement, VHDL 282casex keyword, Verilog 323casex statement, Verilog 323

casez keyword, Verilog 323casez statement, Verilog 323CAS latency 837cathode 156causality 362, 527CCD (charge-coupled device) 822CD (compact disc) 4, 81CD-R (writeable compact disc) 81ceiling function 53central office (CO) 4central processing unit (CPU) 799Chandrakasan, A. 174, 508Chaney, Thomas J. 775, 789character, VHDL 260, 261characteristic equation 540, 544,

550, 551, 564, 578characteristic impedance 182charge-coupled device (CCD) 822charge pump 812Charlie Brown 526check bits 60checksum 68checksum code 68chip 6chip-select (CS) input 813chip-select setup time 826chip viewer 240chip vs. IC 12Chua, H. T. 508Ciletti, Michael D. 336CINmax 146circle 548circuit description 184, 343circuit specification 342circular reasoning 559circular shift 748Cisco Systems iii, xxiiiCL 123clamp diode 153, 160Clare, Christopher R. 664Clark Kent 526




870 Index

CLB (configurable logic block) 850–854

clear input 527, 533, 680clock 7, 522, 523

distribution 172frequency 522gated 765–767in synchronous system 758jitter 684period 522recovery 740skew 683, 684, 759, 766tick 522, 542

clocked assignment operator, ABEL := 612

clocked synchronous state machine 523, 542

clocked truth-table operator, ABEL :> 613

clock-enable input 534clock skew 759, 762–765CML (current-mode logic)

170–173See also emitter-coupled logic

(ECL)CMOS (complementary MOS)

85–151, 171, 421, 7634000-series 141AND 93AND-OR-INVERT (AOI) gate 94,

175gates 368inverter 88–90latch-up 113load 147logic 80, 81, 88NAND gate 90NOR gate 91OR-AND-INVERT (OAI) gate 95,

175OR gate 93PLD circuits 380–382technology 18, 19

CMOS (complementary MOS) (continued)

transfer characteristic 130transmission gate 129–130unused inputs 112TTL interfacing 103, 106, 142

CMOS/TTL interfacing 103, 106, 142

CMOS vs. TTL 85CO (central office) 4Coburn, James 73code 48–56, 384coded state 560, 572, 605coded states 606code rate 78code word 48coding 241coding style

state-machine 682Verilog 291, 298, 299, 303,

304, 305, 314, 316, 317, 321, 322, 323, 325, 327, 333, 407, 648, 650, 652, 657

Verilog state-machine 649VHDL 289–290, 628, 632VHDL state-machine 628

collector, transistor 158colon, in bus name 359color

for ABEL keywords 244for expressions 186for Verilog keywords 293for VHDL keywords 258

column address, DRAM 836column-address register, SDRAM

836combinational carry output 721combinational circuit 6, 82, 183,

521speed 210

combinational-circuit analysis 183, 199–204

combinational-circuit synthesis 183, 205–222

combinational multiplier 494combinational vs. combinatorial

376combination lock 568combination-lock state machine

620, 623, 637, 656combining theorem 189, 211com keyword, ABEL 244comma in Verilog sensitivity list

314command input 760comments


committee, designed by 629common-emitter configuration 159common-mode signal 172communication 3, 344commutative law 188compact disc (CD) 4, 81, 816compact-disc player 799companded encoding 816comparators 319, 326, 458–473,

759ABEL 466HDL 463–466iterative 459parallel 459serial 756Verilog 469–473VHDL 466–468

comparing numbers 33comparison, Verilog 304compatible states 599compilation 241compiler

ABEL 244HDL 239Verilog 305, 307, 322, 330VHDL 257, 266, 269, 270, 294




Index 871

complement 186of a logic expression 192

complementary MOS See CMOScomplement number system 35complete set 233complete sum 218, 229, 236complex programmable logic

device (CPLD) 15, 23, 378, 543, 840, 841–849, 859

fitter 379fitting 242macrocell 379, 452programming technology 382Xilinx XC9500 841–849

component declaration, VHDL 272component instantiation, Verilog

307component keyword, VHDL 272component statement, VHDL 272computer-aided design (CAD) 9,

189, 347, 350program 577software 577, 763, 764tools 9–10, 576

computer-aided engineering (CAE) 9

See also computer-aided designComputer History Museum 809computer-science students xviicomputing the radix complement

36concatenation operator &, VHDL

265, 751concatenation operator {}, Verilog

300, 752concurrent signal-assignment

statement, VHDL 276concurrent statement, Verilog 306concurrent statement, VHDL 271condition, Verilog 318conditional assignment, VHDL 278conditional concurrent signal-

assignment statement, VHDL 276

conditional operator ?:, Verilog 305, 311, 431, 445, 492

condition input 760conductive wrist strap 113conference circuit 818configurable logic block (CLB)

850–854configuration management

Verilog 293VHDL 258

configuration register, SDRAM 839

consensus 190, 226consensus term 602, 611, 694consensus theorem 190, 223constant, VHDL 261constant declaration, VHDL 263constant expression 299

ABEL 392constant logic value 112constant outputs, PLA 372constants, Verilog 299, 305constants, VHDL 263constraints 242

fitter 379contact bounce 687continuous-assignment statement,

Verilog 310, 313, 431control unit 759CONV_INTEGER function, VHDL

268converting VHDL types 267Conway, Lynn 663, 789cooling 171core logic 151cosmic rays 58, 79, 98cost 2, 6, 16, 17, 22, 23, 284, 443,

584, 828combinational-circuit 211, 216,

220of PLD-based designs 710state-machine 560, 563, 565

Costello, D. J. Jr. 74

counters 710–718, 759ABEL 719–721cascaded 680synchronous 711synchronous parallel 712synchronous serial 712Verilog 725–727VHDL 721–725

cover 189covering theorem 189covers 217CPLD See complex

programmable logic deviceCPU (central processing unit) 799CRC (cyclic-redundancy check) 65critical race 597, 597CS-controlled write 826Cummings, Clifford E. 336, 648,

664CUPL (Compiler Universal for

Programmable Logic) 238current

direction, CMOS 106direction, TTL 164flow, CMOS 106flow, TTL 164leakage 88, 133sinking 106sourcing 106TTL sinking 162TTL sourcing 162

current-mode logic (CML) 170–173

See also emitter-coupled logic (ECL)

current spikes 124current-state-variables, ABEL 618custom LSI 16custom VLSI 381cut off (OFF) 159cut set 594CV2f power 123, 142




872 Index

cyclic-redundancy-check (CRC) code 65

Cypress Semiconductor 775, 789

Ddata bit 364dataflow description, Verilog

310–312dataflow description, VHDL

275–278dataflow design, Verilog 310–312dataflow design, VHDL 275–278data hold time 826Data I/O Corporation 243data output 800data setup time 826data sheet 98

CMOS 98–100TTL 166

data unit 759dating 208DC balance 71, 740DC fanout 111DC load 103, 116, 149, 763DC noise margin 97, 103, 112, 169

HIGH-state 148LOW-state 148TTL 164

DC noise margin, TTL 165DDPPonline xvi, xxi–xxii, 3dead time 419deassert 348debounce 688debugging 3, 113decade counter 716decade counting 725decimal codes 48–51decimal counter 725decimal decoder 386decimal point 26decimal-to-radix-r conversion 30decision window 772declarations, ABEL 244, 245

declarations, Verilog 291decode 384decoders 384–408, 717, 801


decoding 61decoding glitches 717, 735, 736decomposed state assignment 561,

562decomposition, state-machine 587decoupling capacitors 124`define directive, Verilog 305

vs. parameter 305defparam keyword, Verilog 309delay 224, 242, 362–370, 528, 763

maximum 363, 365minimum 365, 368three-state-buffer 419TTL 165typical 363, 365See also propagation delay

delay, feedback-sequential-circuit 608

delay line 822delay-locked loop (DLL) 840delay path 683delay statement, Verilog 331delay value, Verilog 310delta delay, Verilog 331delta delay, VHDL 286delta time 645, 662, 755DeMorgan’s theorem 190

generalized 192, 194, 196, 202DeMorgan equivalent symbols 347demultiplexer 438descrambler 740design 590

hierarchical 241state-machine 553, 554, 559,

566, 577vs. synthesis 184

designed-by-committee project 629

design flow 241VHDL 241

design time 22device declaration, ABEL 244device testing 535Devo 663, 789D flip-flop 532–537

CMOS 600with enable 534

dice 12die, IC 12

plural of 12dielectric 113difference, in subtraction 32differential amplifier 171differential inputs 172differential outputs 172digital 3digital abstraction 96, 185digital attenuator 817, 817, 818digital camera 3digital conference circuit 818digital design 1, 5

levels of abstraction 18digital devices 6–7digital logic 80digital phase-locked loop (DPLL)

70, 778digital revolution 3, 5digital versatile disc (DVD) 4digital voice coding 820digital vs. analog 3–6, 7–8, 79diminished radix-complement

system 38diode 84, 804

clamp 153forward-biased 156parasitic 130reverse-biased 156Schottky 160

diode action 156diode AND gate 157, 160




Index 873

diode-drop 156diode logic 155DIP (dual inline pin) 12diphase 73DIP switch 687directed arc, state-diagram 548disable keyword, Verilog 326disable statement, Verilog 326Disanno, Scott xxiiidisk, magnetic 81$display task, Verilog 329distance 58distinguished 1-cell 218distributive law 189divide-by-m counter 710division 47–48, 284

overflow 48Verilog 301

D latch 530, 686, 694, 822documentation 2, 3, 186, 243, 256,

342–362, 386–387, 528, 680–686

flip-flop 680state machine 680

dominance, flip-flop control inputs 647

don’t-carebit 58in excitation tables 608input combination 222

ABEL 251in state coding 585minimization 222signal value 684truth-table notation 385

don’t-care states 583double-data-rate (DDR) SDRAM

839downto keyword, VHDL 263, 265DPLL (digital phase-locked loop)

70drain, CMOS transistor 87

DRAM (dynamic RAM)bank 834column address 836See also dynamic RAM

drills vs. exercises xixdrive strength, Verilog 310dual in-line-pin (DIP) package 687dual inline-pin (DIP) package 12dual-inline-pin (DIP) package 362duality 185, 186, 193, 209dual of a logic expression 193dumb errors 262, 358duty cycle 522, 716DVD (digital versatile disc) 4dynamic circuit behavior 97, 114dynamic hazard 227, 758dynamic-input indicator 316, 532,

680dynamic memory 81dynamic power dissipation 122,

145dynamic RAM (DRAM) 821,

833–840synchronous (SDRAM)

835–840dynamic range 816

EECL See emitter-coupled logiceclipse 220edge-triggered behavior 532edge-triggered D flip-flop 523,

532–537, 697with enable 534

edge-triggered J-K flip-flop 539EEPLD 381EEPROM (electrically erasable

programmable read-only memory) 811–812

electrical characteristics, TTL 167electrical loading 242electrically erasable programmable

logic device (EEPLD) 381

electrically erasable programmable read-only memory (EEPROM) 811–812

electronics concepts xvielectrostatic discharge (ESD) 98,

113else clause, ABEL 248, 614else keyword, Verilog 318else keyword, VHDL 258, 276,

281elsif, VHDL 281emitter, transistor 158emitter-coupled logic (ECL) 155,

170–173100K family 170, 17310K family 170, 173

enable, Verilog task 328enable input 384, 388

D flip-flop 534multiplexer 436, 440three-state-buffer 421

ENABLE keyword, ABEL 246encoders 408–412

ABEL 412–415VHDL 416–417

encoders, Verilog 417end, VHDL 259end-around carry 44endcase keyword, Verilog 321endgenerate keyword, Verilog

310end keyword, Verilog 317end keyword, VHDL 258endmodule keyword, Verilog 293,

294end statement, ABEL 245energy 145engineering 2engineering design margins 96Eniac 84entity, VHDL 256entity declaration, VHDL 257entity keyword, VHDL 258, 259




874 Index

entrepreneur 344enum_encoding attribute, VHDL

633enumerated type, VHDL 261, 630EPROM (erasable programmable

read-only memory) 810equation block, ABEL 250equations, ABEL 245

reverse-polarity 248state variable on lefthand side

614equations statement, ABEL 245Equivalence gate 447, 459equivalent load circuit 116equivalent states 558equivalent symbols 347erasable programmable read-only

memory (EPROM) 810erasing 810flash 811

erasing an EPROM 810–811Ercegovac, Miloš 73error 58error-correcting code 61, 451, 740error-correcting decoder 64error correction 61error-detecting codes 58–68, 449,

740error model 58errors in this book xxiiESD See electrostatic dischargeEspresso-II 224Espresso-MV 224essential hazard 609, 697, 762essential prime implicant 219Ethernet 740, 778, 779

gigabit 171even-parity circuit 448even-parity code 59, 449event attribute, VHDL 289, 625,

698event list, Verilog simulator

331–332, 662

event list, VHDL simulator 285–286, 645

excess-2m−1 system 39excess-3 code 50excess-3 sequence 719, 725excess-B representation 39excitation 546excitation equation 546, 551, 578,

591excitation logic, VHDL 628, 649excitation maps 564excitation table 563Exclusive-NOR (XNOR) gate 233,

447comparator 458, 459

Exclusive-OR (XOR) gate 233, 447comparator 458

executing statement, Verilog 312exercises vs. drills xixexit statement, VHDL 283exponent 816expression

ABEL relational 253product-of-sums 193, 197, 204,

209sum-of-products 193, 197, 201,

204, 207, 208, 209switching algebra 186, 187

expression, ambiguous 188expression, Verilog 303extended Hamming code 65external feedback, PLD 708extra negative number 37, 42eyeball 223, 594

Ff, synchronizer frequency 773failure 58

intermittent 112Fairchild Semiconductor 508, 788fall time 112, 131, 149, 763fall time (tf) 115

FALSE 3false, Verilog 303false keyword, VHDL 261fan 522fan-in 92fanout 97, 111, 133, 148, 170,

388, 438, 763AC 111CMOS 111DC 111HIGH-state 111, 148LOW-state 111, 148overall 111TTL 164–165

fault detection 230FCT (Fast CMOS, TTL compatible)

128, 135, 149FCT-T (Fast CMOS, TTL

compatible with TTL VOH) 149

feedback input 708feedback loop 183, 523, 524, 525,

526, 527, 529, 590, 595, 600feedback sequential circuit 523,

526, 590–611, 613hazards 228

fiber optics 81fiber-optic transceiver 171Fibonacci sequence 673fictional buffer 590, 591, 594, 595field, finite 73, 737field effect 88field-programmable gate array

(FPGA) 11, 15, 15, 23, 96, 199, 343, 379, 543, 566, 850–859

place-and route 242programming technology 382Xilinx XC4000 850–858

FIFO (first-in, first-out memory) 859

fighting outputs 133, 138, 419, 826file input/output, Verilog 329




Index 875

filtering capacitors 124fine-line PCB technology 17finite field 73, 737finite induction 190finite-memory design 638, 656finite-memory machine 672finite-state machine 522, 558, 672first-in, first-out (FIFO) memory

859fitter 240, 242, 849, 853

constraints 379fitter, CPLD 379fitting 242fixed-OR element (FOE) 373flash EPROM 811, 812flash memory 812flat schematic structure 357Fleischer, Bruce M. 174flip-flop 7, 526, 532–541, 590,

686asynchronous inputs 533CMOS D 600control-input dominance 647documentation 680reset-dominant 647set-dominant 647

flip-flop vs. latch 526–527floating gate 382floating-gate MOS transistor 381,

810floating input 112, 690floating output 418floating-point representation 816floating signal 421floating state 132, 421flowchart 664flow table 597flow-table minimization 604–605Flynn, Michael J. 73fmax 708Ford Thunderbird 571forever statement, Verilog 325

for keyword, Verilog 324for loop, Verilog 324for loop, VHDL 282formal parameters, VHDL 265for statement, Verilog 310, 324forward-biased diode 156forward resistance 156FPGA See field-programmable

gate arrayFranaszek, Peter 74free-running counter 715Frisbee xviifront-end design process 241full adder 474, 475, 476, 477full case, Verilog 322full subtractor 476function, Verilog 326function, VHDL 265functional decomposition 311functional verification 242, 242function block (FB), Xilinx 841function call, Verilog 327function call, VHDL 265function declaration, VHDL 271function definition, Verilog 326function definition, VHDL 265function generator 852–854function hazard 717, 758, 788function keyword, Verilog 326function keyword, VHDL 265function table 388fundamental-mode circuit 590, 592fun stuff xvi, 2, 566, 589fuse pattern 254fuses, PLA 371fuses, PLD 376fusible link 810

GG (giga-) 72Gagliardi, R. M. 74

GAL16V8 376, 378, 394, 424, 426, 440, 441, 442, 703, 707, 709

GAL16V8C 377, 378, 703GAL16V8R 703GAL16V8S 703, 703GAL20V8 378, 412, 424, 706, 709GAL22V10 378, 706, 709GAL devices 376–376, 703–710Galois, Évariste 73, 737Galois-field arithmetic 589Galois fields 788gate 6

of CMOS transistor 87symbols 346–347

gate array 16, 600gate-array design 17Gateway Design Automation 290gating the clock 765–767generalized DeMorgan’s theorem

192, 194, 196, 202, 346generate block 310generate keyword, Verilog 310generate statement, Verilog 506generate statement, VHDL 273,

500generic array logic (GAL) 376

See also GAL devicegeneric constant, VHDL 274generic declaration, VHDL 274generic keyword, VHDL 274generic map, VHDL 274genvar keyword, Verilog 310Ghausi, M. 174giga- (G) 72gigabit Ethernet 171glitch 224, 373, 717, 735, 736, 766glue ICs 13Goldstine, Herman H. 229Golson, Steve 664Google xxiii, 12goto statement, ABEL 614




876 Index

Graham, Martin 174, 790Gray code 51, 57, 385Greek philosophers 663, 789ground (GND) 126ground bounce 126, 127, 128, 149,

152group carry-generate signals 492group-carry lookahead 483, 484,

484group carry-propagate signals 492group-ripple adder 482guessing game 580, 588Gunawan, Hendra 336

Hhalf adder 474half sum 474Hamlet circuit 236Hamming, R. W. 61Hamming code 61, 451Hamming distance 58hardware description language

(HDL) 5, 8, 9, 15, 18, 187, 205, 237

compiler 9hardware model 5Haseloff, Eilhard 789hazard 224–229, 602, 758

dynamic 227, 758essential 609, 697, 762function 717, 758, 788in feedback sequential circuit

228static 694, 717, 758static-0 225static-1 225

hazard-free excitation logic 602, 602

hazardsin synchronous design 228

HC (High-speed CMOS) 102, 142, 153, 154

HCT (High-speed CMOS, TTL compatible) 142, 153, 689

HDL (hardware description language) 5, 8, 9, 15, 18, 187, 205, 237

compiler 9, 239, 576signal naming 354–355simulator 9synthesis tool 239synthesizer 9, 239test bench 10tool suites 239–240

HDL text editor 9, 239Hellerman, Herbert 522helper output, PLD 395helper terms 375, 376Hennie, Frederick C. 664henries 124hertz 69hertz (Hz) 69hexadecimal addition 34hexadecimal digits A–F 27hexadecimal number system 27–29hexadecimal prefix ^h, ABEL 253hexadecimal-to-binary conversion

28hierarchical design 241hierarchical schematic structure

357HIGH 3, 80, 86, 157, 194, 348high-impedance state 132, 418high-order bit 27high-order digit 26HIGH-state DC noise margin 148HIGH-state fanout 111, 148

TTL 165Hi-Z state 132, 418, 420, 421

multiplexer output 436HM62256 828HM6264 828HM628128 828HM628512 828

hold time 242, 532, 533, 540, 541, 697, 816, 825

hold-time margin 683, 762hold-time requirements 370Holley, Michael 336, 629Horton, Marcia xxiiiHuntington, E. V. 229Huntington postulates 229hysteresis 130, 360, 421Hz (hertz) 69

II/O block (IOB) 846, 854–855I/O pin, PAL 375IC (integrated circuit) 11–14, 84∆ICC 145ICCH, TTL 167ICCL, TTL 167ICCT 145IC type 360IC vs. chip 12identifier 354


idle state 560IEEE (Institute of Electrical and

Electronics Engineers) 256, 336, 347

IEEE 1164 standard logic package 261, 265, 266, 270, 427

IEEE 1364 (Verilog) 291IEEE standard 1076 270IEEE standard 1149.1 383IEEE standard logic symbols 347,

681if keyword, Verilog 318if statement, ABEL 614if statement, Verilog 318, 404if statement, VHDL 280II, TTL 167IIH 103IIHmax, TTL 165




Index 877

IIL 103IImax 146impedance vs. resistance 88implicit sensitivity list, Verilog 313imply 217in, VHDL 259`include directive, Verilog 305includes 217inconsistent state-machine

representations 681independent error model 58index 23inductance, stray 124induction step 190inductive effects 124–128inductor 124infer (in synthesis) 239infer a latch, Verilog 314, 320, 322inferred latch 698, 702inferring latches 471, 472information bit 59initial block, Verilog 332initial keyword, Verilog 332initial state 556, 561, 562, 563in keyword, VHDL 258inout declaration, Verilog 295inout keyword, Verilog 295, 328inout keyword, VHDL 259inout port, Verilog 295input

5-V-tolerant 153, 154floating 112PLA 370

input/output declarations, Verilog 327

input combination 6input declaration, Verilog 295input keyword, Verilog 293, 295,

327input-list, ABEL 250, 253input port, Verilog 294–295inputs, unused 112

input state 592instance statement 309instance statement, Verilog 307,

313instantiate 257, 272, 292instantiatiation 357instructors xxiiinsulation 113in-system programmability 383integer keyword, Verilog 297integer type, VHDL 260, 261integrated circuit (IC) 11–14, 84Integrated Device Technology 859intermediate equation, ABEL 247intermittent failure 112internal feedback, PLD 708internal state 592Internet Protocol (IP) 4introductory courses xviinvalid logic level 8inversion bubble 83, 90, 208, 346,

346, 347, 349, 351–353, 389, 390

inverted 1-out-of-n code 55inverter 7, 82, 159–160, 186, 350

CMOS 88–90symbol 346

inverting gate 210, 388invert keyword, ABEL 248IOH 102IOHmax 106IOHmax, TTL 165IOHmaxC 148IOL 102IOLmax 106IOLmax, TTL 165IOLmaxC 147IOLmaxT 147IOS, TTL 167IP (Internet Protocol) 4irredundant sum 234ISE 337

ISE (Integrated Software Environment) xx

is keyword, VHDL 258, 259ISO (International Standards

Organization) 261, 264ispLEVER xx, 337istype keyword, ABEL 244, 612iterative circuit 459, 462, 756

boundary inputs 756boundary outputs 756cascading inputs 756cascading outputs 756primary output 756

iterative comparator 459iterative consensus 190, 223iterative widget 756

JJackson, Tom 859Jacobs, Joanne v, xxivJain, Prem xxiiiJ-K flip-flop 553J-K flip-flop 686job xviiJohnson, Howard 174, 790Johnson counter 735

self-correcting 736Joint Photographic Experts Group

(JPEG) 4joke 522

really bad 588joule 145JPEG (Joint Photographic Experts

Group) 4JTAG port 383juxtaposition 187

KK (kilo-) 72Karnaugh map 212

5-variable 235, 5646-variable 236




878 Index

Karnaugh, M. 230Kaufman, Jennie xxiiiKent, Clark 526keywords, Verilog 293keywords, VHDL 258kilo- (K) 72Kleeman, Lindsay 789Klir, George J. 174kludge 766Knuth, Donald E. 73, 376Kohavi, Zvi 230, 664, 788

L_L suffix 387, 390laboratory courses xviLáng, Tomas 73larger-scale logic element 349,

355, 386–387large-scale integration (LSI) 13, 13

functions 16Larsen, Ib 788latches 526, 527–532, 590, 686


latch inference 471, 472, 652latch inference, Verilog 314, 320,

322latching decoder 696latch-up, CMOS 113latch vs. flip-flop 526–527late-write SSRAM with flow-

through outputs 830late-write SSRAM with pipelined

outputs 830Lattice ispLEVER 337Lattice Semiconductor xx, 378,

508, 859ispLEVER xx

lawyers 132, 373LCD (liquid-crystal display) 408

leakage current 88, 103, 109, 133, 156

least significant bit (LSB) 27least significant digit 26LED (light-emitting diode) 103,

135–137, 408left, shift-register direction 730level shifter 155levels of abstraction, digital design

18level translator 155Levesque, A. H. 74, 788LFSR (linear feedback shift

register) counter 737, 788libraries 239library, Verilog 308library, VHDL 269library, Xilinx ISE unisims 272library clause, VHDL 269light-emitting diode (LED) 103,

135–137, 408Lin, S. 74linear feedback shift register

(LFSR) 588, 589counter 737, 788

line code 69liquid-crystal display (LCD) 408literal 197

Verilog 298–299load

AC 116capacitive 116DC 103, 116resistive 103

load capacitance 115, 170logic, multivalued 224logic 0 8logic 1 8logical addition 187logical expression, Verilog 304logical multiplication 186logical operators, Verilog 303–305

logical vs. bitwise negation, Verilog 755

logical vs. boolean, Verilog 304logic circuit 183

combinational 183sequential 183

logic design 1, 5logic designer 344logic-design template 8logic diagram 306, 343, 355–358logic-drawing template 237logic equation 348logic expression 187, 348

complement of 192dual of 193parenthesized 201

logic expressions vs. signal names 349

logic families, TTL 166logic family 85logic inverter 159

CMOS 88logic levels 101–103

invalid 8TTL 162

logic minimization programs 223–224

logic symbol 390traditional 386

logic value 80CMOS undefined 86constant 112

lookahead carry circuit 485looping statement, Verilog 324LOW 3, 80, 86, 157, 194, 348low-order bit 27low-order digit 26Low-power Schottky TTL (LS-

TTL) 160, 689LOW-state DC noise margin 148LOW-state fanout 111, 148

TTL 165




Index 879

Low-Voltage CMOS (LVC) 154, 690

LSB (least significant bit) 27LSI (large-scale integration) 13LSI Logic Corporation 600LS-TTL (Low-power Schottky

TTL) 160, 689_L suffix 348lunch 3LVC (Low-Voltage CMOS) 154

MM (mega-) 72macrocell, PLD and CPLD 379,

452macros 342magnetic bubbles 822magnetic disk 81magnetic tape 81magnitude comparator 458main machine 587majority function 499

3-input 309Manchester code 73, 81mandarin 12Mano, M. Morris 229mantissa 816marginal notes xviimarginal pun xviimarginal triggering condition 526margins, engineering design 96marketing people 851Marquand, A. 230Mars 76mask 809mask charge 809mask-programmable ROM 809mask ROM 809master/slave J-K flip-flop 538master/slave S-R flip-flop 537master latch 532

mathematicians 594Maxfield, Clive 508maximum delay 363, 365maximum-length sequence 737maximum-length sequence

generator 737maxterm 197, 210, 222maxterm i 198maxterm list 199, 211McCluskey, Edward J. xxiii, 223,

229, 230, 663, 788, 789MCM (multichip module) 17Mead, Carver 663, 789Mealy machine 543, 547, 548,

549, 556, 558, 568, 590Mealy-type output 543, 550, 620,

761mean time between failures

(MTBF) 772, 774, 776, 777mechanical encoding disk 385medium-scale integration (MSI)

13, 22, 392functions 16, 342

mega- (M) 72memory 7, 13, 450

first-in, first-out (FIFO) 859Mercedes 508Mercury Capri 571metal-oxide semiconductor field-

effect transistor (MOSFET) 85–88

metastability 525, 525–526, 528, 529, 530, 532, 533, 538, 594, 645, 663, 762, 767, 769–778, 859

metastability resolution time 771metastable state 525, 769metatheorem 193Michels, Diana 12Michelson, A. M. 74, 788microampere 88microampere (uA) 88Micron Technology 859

microprocessor 13, 358, 410, 421, 450, 523, 773, 777, 799, 811, 813, 828

microsecond (µsec) 6mil 17Mills, Don 664minimal-cost equations 563, 565,

566minimal cut set 594minimal product 222minimal-risk equations 563, 565minimal sum 216, 218, 219, 220,

221minimization programs 223–224minimize 210minimum delay 363, 365, 368minimum distance 59minimum pulse width 121, 526,

528, 531minterm 197, 210, 212, 214, 215minterm i 198minterm list 198, 210minterm number 198, 213minuend 32model, hardware 5modeling language 256modem 740module, Verilog 291module declaration, Verilog 294module keyword, Verilog 293, 294module statement, ABEL 244modulo-m counter 710modulus 710

Verilog 301Moebius counter 735$monitor task, Verilog 329$monitoroff task, Verilog 329$monitoron task, Verilog 329Monolithic Memories, Inc. (MMI)

508Moore’s Law 18Moore machine 543, 548, 549,

552, 555, 572, 590




880 Index

Moore-type output 543, 548, 550, 616, 761

MOS (“moss,” metal-oxide semiconductor) 86

MOSFET (metal-oxide semiconductor field-effect transistor) 85–88

MOS ROM 808MOS transistor 85

floating-gate 381most significant bit (MSB) 27, 34,

37most significant digit 26Motion Picture Experts Group

(MPEG) 4Mountain View, CA 809m-out-of-n code 56movies 5MPEG (Motion Picture Experts

Group) 4MSB (most significant bit) 27, 34,

37MSI (medium-scale integration)

13, 22, 392functions 16, 342

m-subcube 58MTBF (mean time between

failures) 772µ-law PCM 816multichip module (MCM) 17multidimensional array

Verilog 503Verilog-2001 302VHDL 264, 497

multiple-cycle synchronizer 776multiple-emitter transistor 161multiple error 58multiple-output circuits 184multiple-output function 223multiple-output minimization 222,

224multiple-valued logic 230multiplexed address inputs 835

multiplexer 18–21, 311, 432–446ABEL program 20Boolean equation 19CMOS 18enable input 436, 440gate-level design 19MSI building block 20PLD realization 20switch model 18truth table 19Verilog program 22VHDL program 20

multiplexersABEL 440–443expanding 436–438Verilog 445–446VHDL 444–445

multiplication 45–47ABEL 497signed 46–47using ROM 803Verilog 301, 503–507VHDL 497–502

multiplication dot (⋅) 186, 187multipliers 494–502multiplying out 189, 201, 203,

207, 208, 476multivalued logic 224Murphy’s law 366mutual exclusion 553, 574mux 432

Nn{}, Verilog replication operator

300named state 572, 605NAND gate 83, 191, 210, 529

CMOS 90symbol 346

nand gate, Verilog 306NAND-NAND circuit 204, 208,

209, 211, 229

NAND vs. NOR gate 529CMOS 92

nanohenries (nH) 124nanosecond (ns) 6nasty realities 762National Semiconductor

Corporation 132natural subtype, VHDL 263n-bit binary code 384n-bit binary counter 711NBUT gate 674n-channel MOS (NMOS) transistor

87n-cube 57, 58NEC Electronics 859negate 348negated 3negative BCD numbers 49negative-edge-triggered D flip-flop

533negative logic 80negative-logic convention 185, 194negative numbers 34–39negedge keyword, Verilog 334,

646, 702neg keyword, ABEL 248nerds 185, 230nested expansion formula 30nested if statement, Verilog 318nested when statement, ABEL 250nesting, if-then-else, ABEL

616net, Verilog 296net declaration, Verilog 296net list 242, 273, 306nets vs. variables, Verilog 297–298next-state function 545next-state logic 542

VHDL 628next-state logic, Verilog 649next statement, VHDL 283next-state-variables, ABEL 618




Index 881

nH (nanohenries) 124nibble 29Nikolic, B. 174, 508NMOS (n-channel MOS) 87node, state-diagram 548noise 98, 131noise immunity, ECL 172noise margin 7, 101–103, 169

DC 97, 103, 112TTL 164, 165

noise marginsTTL 162

nonblocking assignment, Verilog 331

nonblocking assignment operator, Verilog <= 315

non-blocking assignment statement, Verilog 648

noncode word 58noncritical race 597noninverting gate 210, 388nonrecurring engineering (NRE)

cost 16, 22Non-Return-to-Zero (NRZ) 69Non-Return-to-Zero Invert-on-1s

(NRZI) 71nonvolatile, erasable memory 81nonvolatile memory 801, 810, 822NOR gate 83, 192, 210, 529

CMOS 91symbol 346

nor gate, Verilog 306normal term 197NOR-NOR circuit 209, 211, 229NOR vs. NAND gate, CMOS 92notation 144NOT gate 7, 82not gate, Verilog 306notif0 gate, Verilog 306notif1 gate, Verilog 306not keyword, VHDL 258NOT operation 186

NOT prefix 244npn transistor 158NRE (nonrecurring engineering

cost) 16NRZ (Non-Return-to-Zero) 69NRZI (Non-Return-to-Zero Invert-

on-1s) 71n-to-2n decoder 384null statement, Verilog 317null statement, VHDL 268numeric_std VHDL package 270

Ooctal 421, 692octal number system 27–29octal-to-binary conversion 28odd-parity circuit 448odd-parity code 60off-set 199"off" transistor 87Ohm’s law 100Oliu, W. E. 508one-hot state assignment 562

almost 562one-hot state encoding 658OneKey xx–xxi, xxiiones’ complement 38, 77ones’-complement addition 44ones’-complement arithmetic 44ones’-complement subtraction 44ones-counting machine 635, 655one-time programmable (OTP)

ROM 811one-to-one mapping 384on-set 198, 248, 612"on" transistor 87ooze 134open-collector output 133, 360open-drain bus 137, 137–138open-drain output 133–136, 360operator overloading, VHDL 266,

276

operator precedence 193ABEL 245Verilog 303VHDL 276

optional sections xvi, 38OR-AND circuit 193, 202, 209,

211, 227, 229OR-AND-INVERT (OAI) gate,

CMOS 95, 175OR gate 6, 82, 187, 194, 210

CMOS 93symbol 346

or gate, Verilog 306or keyword, Verilog 312, 313, 314OR operation 187Osborne, Thomas E. 664other declarations, ABEL 245others, VHDL 264, 277, 282, 429OTP-ROM (one-time

programmable ROM) 811out, VHDL 259outkeyword, VHDL 258output

5-V-tolerant 154open-collector 133, 360open-drain 133–136

output-coded state assignment 543, 584

output declaration, Verilog 295output-disable time 815, 826output-enable (OE) input 813output-enable gate 375output-enable time 815, 826output equation 547, 552, 592output function, state-machine 545output-hold time 815, 826output keyword, Verilog 293,

295, 328output-list, ABEL 250, 253output loading 101, 102, 111output logic, state-machine 542output logic, Verilog 649




882 Index

output logic, VHDL 629output logic macrocell 703output polarity, GAL 378output-polarity control 378output port, Verilog 294–295outputs, fighting 133, 138outputs, PLA 370output-select multiplexer 617output stage, TTL 161output table 552output timing skew 747overall fanout 111

TTL 165overbar notation 186, 390overflow 43

rules 41two’s-complement 41, 42

overlaid functions, VHDL 468, 488, 502

overloaded output, TTL 165overshoot 153

Ppackage, VHDL 269package body keywords, VHDL

271package keyword, VHDL 271packed-BCD representation 49pad, IC 12pad ring 151page, SDRAM 838PAL16L8 374, 375, 376, 378, 394,

424PAL20L8 376, 378PALASM (PAL Assembler) 237PALCE16V8 378, 707PALCE20V8 378Palnitkar, Samir 336parallel case, Verilog 321parallel comparator 459parallel data 69

parallel-in, parallel-out shift register 728

parallel-in, serial-out shift register 728

parallel-to-serial conversion 728parameter, Verilog 309parameter declaration, Verilog 299parameterized modules, Verilog

309parameter keyword, Verilog 299parameter substitution, Verilog

309, 506parasitic diode 130parasitic SCR 113parenthesization

switching algebra 188parenthesized logic expression 201parity bit 59parity-check matrix 61parity function, ABEL 452parity function, Verilog 456–457parity function, VHDL 453–454partial product 46part-select operator [], Verilog

300, 752party line 418, 419, 420, 421passive pull-up 133patents 74path, signal 120path sensitization 230PayPal xxiiPBX (Private Branch Exchange) 4PCB (printed-circuit board) 17–18,

362, 763PCB design 765PCB-level design 22PCB routing 763PCB traces 17p-channel MOS (PMOS) transistor

87PCI bus 778PCI Express 69

PDP-11 minicomputer 805Pedroni, Volnei A. 336Pellerin, David 290, 336, 629pepperoni 12perfect induction 188, 196perfume 101PERL 10Perl 10permanent failure 58Peterson, W. W. 74phase splitter 161Philips Semiconductor 508, 788picosecond (ps) 6pin declarations, ABEL 244pin definitions, ABEL 397pin diagram 12pin locking 849pin number 360pinout 12pipelined Mealy outputs 761pipelined outputs 544, 620, 629,

634, 649, 652Pixar 5pizza 12PL 123PLA (programmable logic array)

14, 199See also programmable logic

device (PLD)place and route 242PLA fuses 371PLCC package 128PLD (programmable logic device)

11, 243CMOS circuits 380–382fitting 242fuses 376macrocell 379, 452minimization 222, 247–248programming 254

PLD-based design 342, 578, 584PLD-based synchronizer 777




Index 883

PMOS (p-channel MOS) 87pneumatic logic 81, 174pnp transistor 158politics 3polymer memory 81Porsche 508port, VHDL 259port, VHDL 259port-association list, Verilog 307,

308port declaration 259port keyword, VHDL 258port map, VHDL 272ports, Verilog 294–295posedge keyword, Verilog 334,

646, 702positional number system 26positive ECL (PECL) 173positive-edge-triggered D flip-flop

532–537positive logic 80, 388positive-logic convention 185, 194,

195, 348pos keyword 248post-fitting timing verification 242postponed-output indicator 537postulate 185power 103power consumption 109, 123

CMOS 97, 114TTL 124

power dissipation 123dynamic 122, 145quiescent 122static 122

power-dissipation capacitance 122, 145

power-down input 814power supply 124power-supply rails 102, 108power-supply voltage 101, 102,

170, 363, 365, 593, 597, 775

precedenceABEL operator 245switching algebra 187, 193Verilog operator 303VHDL operator 276

precharge 834predefined types, VHDL 260preset input 527, 533, 680primary inputs and outputs,

iterative-circuit 459primary output, iterative-circuit

756prime (′) 186prime, definition of 206, 231prime implicant 217

essential 219secondary essential 221

prime-implicant theorem 218, 229prime notation 186prime number 206prime-number detector 205, 211,

216, 217, 231, 272, 276, 277, 280, 281, 282, 283, 311, 318, 319, 320, 322, 324

test bench 333primitive flow table 603, 603principle of duality 193printed-circuit board 124printed-circuit board (PCB) 17–18,

124, 362, 763printed-circuit-board (PCB) layout

189printed-wiring board (PWB) 17priority 410priority encoder 410private branch exchange (PBX) 4problem solving 2procedural code 297

Verilog 312–329procedural statement, Verilog 312,

313, 315procedure, VHDL 269

procedure call, VHDL 269process, Verilog simulator 331process, VHDL 278process keyword, VHDL 278process statement, VHDL 278product code 66product component 494, 495product of sums 189product-of-sums expression 193,

197, 202, 204, 209product-of-sums minimization 222product term 197product-term allocation 843product-term allocator 844product terms, PLA 370programmable array logic (PAL)

device 14, 373–376programmable interconnect

856–858programmable logic array (PLA)

14, 199, 370–373constant outputs 372diagram 371

programmable logic device (PLD) 11, 13, 14–15, 22, 23, 237, 243, 343, 541, 543, 554, 564, 566, 588, 703–709

CMOS circuits 380–382compiler 424complex See complex

programmable logic device (CPLD)

fitting 242fuses 376macrocell 379, 452minimization 222, 247–248programmer 382programming 254vs. simulation 11

programmable read-only memory (PROM) 382, 809

biploar 810programmer 382, 809




884 Index

programmable switch matrix (PSM) 857

programmer vs. logic designer 344programming 349

CPLD 382EEPLD 381EEPROM 811EPROM 810FPGA 382mask ROM 809PROM 809

programming and state machines 555

programming an EPROM 810–812programming voltage, EEPROM

812programming vs. state-machine

design 555, 681programs, logic minimization

223–224project leader 344PROM (programmable read-only

memory) 809propagation delay 97, 111, 115,

120–122, 144, 364, 368, 528, 528, 531, 532, 608, 697, 708

property list, istype 244P-set 230pseudorandom counting sequence

740pseudorandom sequence generator

588, 589pull-up, active 133pull-up, passive 133pull-up resistor 133, 421, 690pull-up-resistor calculation 139pulse-catching circuit 603–611pulse input 663pulse-mode circuit 663pulse-triggered flip-flop 537pulse width, minimum 526, 528,

531punctuation 77

pushbutton 687push-pull output, TTL 161

QQDR SSRAM 832quad-data-rate (QDR) SSRAM 832quad gate 98quadruple gate 98quantizing distortion 817quiescent power dissipation 122Quine, W. V. 223, 229Quine-McCluskey algorithm 223Q vs. QN 592, 669Q vs. QN 528

RRaaum, Dave xxiii, 325, 339Rabaey, J. M. 174, 508race 596, 605, 758race-free state assignment 605–608radix 26radix-complement system 35radix point 26, 35radix-r-to-decimal conversion 29RAID (redundant array of

inexpensive disks) 67rails, power-supply 102, 108random-access memory (RAM)

821–840, 859static (SRAM) 822–829

range, ABEL 251range, VHDL 262range attribute, VHDL 268range keyword, VHDL 262range specification, Verilog 295RAS-CAS delay 836rate of a code 78RC time constant 117, 690read/write memory (RAM) 696,

759read/write memory (RWM) 821

read cycle, SDRAM 836read-only memory (ROM) 696,

800–821one-time programmable (OTP)

811realization 207realize 207recommended operating conditions,

TTL 167reconfigurable hardware 382recovery time 529rectangular sets of 1s 215redundant array of inexpensive

disks (RAID) 67reference designator 360reflected code 52reflections, transmission-line 131,

153refresh counter, SDRAM 839refresh cycle 834refresh operations, DRAM 839register 691–694, 759

cascaded 680registered carry output 721registered output 612registers, ABEL 694–697registers, Verilog 701–702registers, VHDL 697–701register-transfer language 239reg keyword, ABEL 612reg keyword, Verilog 297reg vs. register, Verilog 404, 405relation, ABEL 253relational expression, ABEL 253relational operators

ABEL 253Verilog 303–304VHDL 276

relay 103relay logic 81, 174reliability 112, 145, 810Renesas Technology 859




Index 885

repeat statement, Verilog 325replication operator n{}, Verilog

300report statement, VHDL 288reserved words 354

Verilog 293VHDL 258

resetstate-machine 558, 560, 561

reset, synchronous versus asynchronous 664

reset circuit 558reset-dominant flip-flop 647reset input 527, 623, 624, 632,

641, 644, 652, 660resistance, forward 156resistance vs. impedance 88resistive load 103resistor

pull-up 421, 690calculation 139

resolution function, VHDL 427resolved type, VHDL 427result, VHDL 265retain property, ABEL 695return keyword, VHDL 265, 266Return-to-Zero (RZ) 71reverse-biased diode 156reverse-polarity equation 248reviewers xvii, xviiirevolution 3, 5right, shift-register direction 730ring counter 718, 732, 742

self-correcting 733ripple 461ripple adder 460, 475ripple carry out, 74x163 counter

715ripple counter 711rise time 112, 131, 149, 763rise time (tr) 115risk 3

Robbins, Tom xxiiirollover, loop counter 333rotating drum 822row address, SDRAM 836row-address register, SDRAM 836row latch, SDRAM 836running disparity 71running process, VHDL 279RZ (Return-to-Zero) 71

Ssafe state 583, 616, 733sales pitch 5–6SanDisk Corporation 812, 859saturated (ON) 159saturation 170scan capability 535, 663

latch 663scan chain 536schematic 273, 306, 680schematic diagram 237, 343, 346,

355–358schematic drawing 204schematic editor 237schematic entry 9schematic viewer 240Schmid, Hermann 73Schmitt-trigger input 130–131,

770Schmitt-trigger inverter 805Schottky-clamped transistor 160Schottky diode 160Schottky transistor 160, 166scope,Verilog 293scope of signal name 355SCR (silicon-controlled rectifier)

113scrambler 740SDRAM (synchronous DRAM)

835–840auto-refresh cyle 839burst-read cyle 838

SDRAM (synchronous DRAM) (continued)

burst-write cyle 839column-address register 836configuration register 839page 838read cyle 836refresh counter 839row address 836row-address register 836row latch 836write cyle 838

second, s 69secondary essential prime implicant

221secret sauce 849security fuse 383Seitz, Charles L. 789selected signal assignment, VHDL

278selected signal-assignment

statement, VHDL 277select statement, VHDL 399self-complementing code 50self-correcting counter 733self-correcting Johnson counter

736self-correcting ring counter 733self-documenting code 682self-dual logic function 234self-timed systems 789semicolon, Verilog 317semiconductor diode 84, 156semicustom IC 16sense amplifier 834sensitivity list

Verilog 312–314, 331implicit 313

VHDL process 279sensitivity matrix, Verilog 331, 332sensor 51sequential circuit 7, 82, 183, 521




886 Index

sequential multiplier 495sequential PLD 376sequential signal-assignment

statement, VHDL 279sequential statements, VHDL 265,

278–284serial-access memory 822serial binary adder 758serial comparator 756serial data 69serial-in, parallel-out shift register

728serial input, shift-register 727serial output, shift-register 727serial-to-parallel conversion 728serial widget 756set 527set, ABEL 251, 614, 618set-dominant flip-flop 647setup time 242, 532, 533, 540,

541, 697, 709, 825setup-time margin 683seven-segment decoder 408seven-segment display 408Shannon, Claude E. 185, 229shift-and-add multiplication 45shift-and-add multiplier 761shift-and-subtract division 47shift register 727–740, 759

cascaded 680shift-register counter 730shift registers


sidebars xviiisign 816signal, Verilog 296signal declaration, VHDL 260signal flags 356, 359signal keyword, VHDL 260signal name 348, 353, 386

signal names 350case sensitivity 354in HDLs 354–355vs. logic expressions 349

signal-namesscope 355

signal naming 355signal path 120signal-sensitivity list, VHDL

285–286signal-sensitivity matrix, VHDL

285signals vs. variables, VHDL 500,

752sign bit 34, 37signed arithmetic, Verilog 301signed division 48signed-magnitude adder 35signed-magnitude representation

50signed-magnitude subtractor 35signed-magnitude system 34signed multiplication 46–47signed vs. unsigned numbers 43sign extension 35, 37, 47, 77silicon-controlled rectifier (SCR)

113parasitic 113

simulation 11, 238, 241, 279, 282, 301, 310, 645, 662, 663

Verilog 331–332VHDL 285–286vs. PLDs 11

simulation cycle, Verilog 331, 332simulation cycle, VHDL 286simulation time, Verilog 331simulation time, VHDL 285simulator 9–10, 200, 240, 330,

337, 369, 507Verilog 331–332VHDL 285–286

simultaneous input changes 590, 593, 594

simultaneous switching 126, 127, 128

single-ended input 172single error 58single stuck-at fault model 255sinking current 106

TTL 162six-variable Karnaugh map 236Skahill, Kevin 336skew 172slash (/) 344slave latch 532sledgehammer 113small-scale integration (SSI) 12,

22, 392, 566, 686sneak path 806Social Security 663software tools 8–10

for logic design 186soldering iron 8solder paste 17source, CMOS transistor 87sourcing current 106

TTL 162space/time trade-off 756, 758specifications 8, 98–100, 102specs 8, 102, 342speed 5

CMOS 97, 114combinational-circuit 208, 210PAL 378PLD 378

speed-power product 145Spencer, R. 174spikes, current 124S-R latch 121, 527, 530, 531, 534,

537, 645, 662, 694with enable 530

S-R latch 529S-set 230SSI (small-scale integration) 12stable 525




Index 887

stable total state 592, 603standard cell 16, 342standard-cell design 16standard logic package, IEEE 1164

261, 265, 266, 270standard MSI functions 342standby mode 815state 7, 522, 545

abnormal 584, 732, 733coded 560idle 560initial 561, 562, 563safe 616, 733unused 584, 616

state/output table 545, 547, 552state adjacency diagram 605state assignment 567, 569state diagram 545, 548, 552, 555,

570–576, 577, 680ABEL 614–621synthesis 682

state_diagram, ABEL 613state keyword, ABEL 614state machine 542–570, 759, 769

ABEL coding style 629cost 563, 565decomposition 587design 2, 553, 554, 559, 566,

577documentation 680inconsistent descriptions 681pipelined output 629, 649programs 682reset 560synthesis 577Verilog coding style 649VHDL coding style 628

state-machine description language 613, 680

state-machine design vs. programming 555, 681

state memory 542Verilog 649VHDL 628

statements, Verilog 292state minimization 599, 604–605state name 547, 548states, total number of 560states, unused 560, 561, 563state table 82, 547, 555, 592, 680state-table reduction 663state-value, ABEL 614state variable 522state-vector, ABEL 614static-0 hazard 225static-1 hazard 225static behavior 101static circuit behavior 97, 101static electricity 98, 113static hazard 602, 694, 717, 758static power dissipation 122static RAM (SRAM) 822–829

asynchronous 829cell 823

std_logic_1164 VHDL package 270

std_logic_arith VHDL package 270, 467–468, 488, 502, 635, 637, 721

std_logic_signed VHDL package 270, 468

std_logic_unsigned VHDL package 270, 468

std_logic_vector type, VHDL 265

std_logic type, VHDL 261, 427std_ulogic type, VHDL 427steady-state behavior 101, 224Stone, Harold S. 229$stop task, Verilog 329storage time 160stray capacitance 115stray inductance 124

stringABEL 244VHDL 264

strong typing, VHDL 262structural description

Verilog 306–310VHDL 273–274

structural designVerilog 306–310VHDL 273–274

structural specification, Verilog 292

structural Verilog code 505structural VHDL code 500structured logic device description

343Strunk, William, Jr. 508subcube 58submachine 587subtraction 32subtraction, Verilog 301subtractor 474

full 476subtractors 476–478

See also adderssubtrahend 32, 32subtype, VHDL 262, 427subtype keyword, VHDL 261suggestive drawings 550sum bit 478sum-of-products expression 189,

193, 197, 201, 204, 207, 208, 209

sum term 197Sunnyvale, California 5Superman 526surface-mount technology (SMT)

17suspended statement, Verilog 312suspended VHDL process 279switch 687switch debouncing 687–689




888 Index

switching, simultaneous 126, 127, 128

switching algebra 184, 185–199, 229

adding out 189ambiguous expression 188associative law 188binary operator 189combining theorem 189commutative law 188consensus theorem 190cover 189covering theorem 189DeMorgan’s theorem 190distributive law 189duality 193expression 186, 187juxtaposition 187multiplying out 189parenthesization 188precedence 187, 193theorem 188

switching characteristics, TTL 169switching noise 149, 152switch model, CMOS 89symbols, gate 346–347symmetric output drive 143, 149,

368synchronization signal 70synchronizer 2, 759, 767

failure 770, 797synchronizer, PLD-based 777synchronizing sequence 624synchronous 542synchronous counter 711synchronous design methodology

683hazards in 228

synchronous DRAM (SDRAM) 835–840

See also SDRAMsynchronous parallel counter 712

synchronous preset, 22V10 707synchronous serial counter 712synchronous SRAM (SSRAM) 829

late-write with flow-through outputs 830

late-write with pipelined outputs 830

QDR 832turn-around penalty 831, 832ZBT with flow-through outputs

831ZBT with pipelined outputs 832zero-bus-turnaround (ZBT) 831

synchronous systems 679, 758–761syndrome 64, 451, 452Synopsys 270, 467, 502Synopsys, Inc. 290, 633synthesis 238, 242, 284, 289, 301,

304, 309, 311, 319, 325, 326, 330, 335, 470–472, 474, 490–493, 500, 502, 627, 647, 651, 656, 698, 701, 702, 727, 752

combinational-circuit 183state-machine 577vs. design 184

synthesis tools 337HDL 239Verilog 290VHDL 256

synthesizer 205, 314HDL 239

system architect 344system clock signal 628

TT (tera-) 72τ, metastability-resolution time

constant 773, 775T1 link 72, 73tAA 815, 825tACS 815, 826

tAH 826tail lights 571tape, magnetic 81tAS 826task, Verilog 328task call, Verilog 328task definition, Verilog 328task enable, Verilog 328task keyword, Verilog 328Taylor, Douglas 290, 336T-bird tail lights 571–576tCF 708tclk 771tCO 708tcomb 771tCSW 826tDH 826tDS 826telephone system 4, 799, 816temperature 101, 102, 105, 363,

365, 593, 597, 775template generator 240temporary failure 58tera- (T) 72termination 103, 182test_vectors, ABEL 245test_vectors keyword, ABEL

253test bench 10, 240, 241, 336

Verilog 294, 326, 506, 648, 659–662

VHDL 279, 285, 287–289, 628, 641–644

test enable (TE) 536testing 535, 536, 623test input, TI 536test-input generation 740test vectors 383, 625, 644, 662

ABEL 245, 253–255, 622Texas Instruments 508, 775, 788,

789, 859text 53




Index 889

text editor, HDL 239tf 115T flip-flop 541, 711, 713, 727

with enable 541tH 708theorem, switching algebra 188The Phone Company (TPC) 4, 72,

73Thévenin equivalent 104Thévenin resistance 104Thévenin termination 182Thévenin voltage 104three-state buffer 132, 418–424three-state bus 132, 690

Verilog 431VHDL 427

three-state driver 418three-state enable 418three-state output 132–133, 436,

690Verilog 430VHDL 427

three-state output pin 424three-state outputs 154


threshold 8threshold function 499threshold logic 230tick 542, 543tilde notation 186$time function, Verilog 329time, modeling 284time keyword, Verilog 330`timescale directive, Verilog 330time scale

Verilog 330time to market 15, 23, 205timing 362–364, 708–709

closure 370

timing analysis 368, 764program 369tools 369

timing analyzer 10, 240, 369timing control, Verilog 325–326,

330–331timing diagram 83, 343, 362, 550,

554, 557, 680, 682–686timing generator 744timing hazard 190timing margin 112, 683timing parameters, PLD 708–709timing skew 610

output 747three-state-buffer 419

timing specifications 362, 365–368, 680, 682–686

MSI parts 367SSI parts 366

timing table 363, 683timing verification 242

post-fitting 242timing verifier 10Tin Toy 5tiny-scale integration 14title statement, ABEL 244TL7705 558To 773tOE 815, 826tOH 815, 826to keyword, VHDL 263, 265tools 2total number of states 560total state 592, 593totem-pole output, TTL 161Tower of Babel 270tOZ 815, 826tp (propagation delay) 120–122TPC See The Phone CompanytPD 708tpHL 121

tpHZ 419tpLH 121tpLZ 419tpZH 419tpZL 419tr 115, 771trace, PCB 17trademarks 373traditional logic symbols 386traffic-light controller 53

See also Sunnyvaletraffic lights 4transceiver 423, 424, 431transfer characteristic, CMOS 101,

130transfer function 524transient behavior 224transistor 804

bipolar junction 84, 158–160MOS 85n-channel MOS (NMOS) 87p-channel MOS (PMOS) 87Schottky-clamped 160

transistor-transistor logic (TTL) 81, 85, 155, 160–168, 171

CMOS interfacing 103, 106, 142

families 166fanout 164–165gates 368load 147logic levels 162noise margin 164, 165noise margins 162output stage 161overall fanout 165power consumption 124totem-pole output 161

transition/excitation table 564transition equation 547, 551, 577,

578transition expression 552, 553




890 Index

transition frequency 122, 145transition list 576–580, 680transition p-term 577transition-sensitive media 71transition statement 614transition s-term 579transition table 547, 552, 563, 591transition time 97, 115–120, 131

TTL 165translator 240transmission gate 18, 129–130,

516, 600transmission line

reflections 131, 153termination 103

transparent latch 531, 822tri net type, Verilog 296tri-state output 132TRUE 3true, Verilog 303truth_table keyword, ABEL 250truth table 10, 19, 82, 196–199,

212, 213, 385, 564, 800ABEL 250, 613notation 385, 388, 434

tsetup 771, 771tSU 708T suffix 143TTL See transistor-transistor logicTTL/CMOS interfacing 103, 106,

142TTL vs. CMOS 85Turing machine 522turn-around penalty, SSRAM 831,

832turning the crank 2, 184, 554, 563,

576, 603, 608, 681, 710TV 522twisted-ring counter 735two’s complement 37, 77two’s-complement addition 39two’s-complement arithmetic

39–43

two’s-complement multiplication 46

two’s-complement subtraction 41two-dimensional code 66two-dimensional decoding 807,

827, 834two-level AND-OR circuit 204, 208two-level NAND-NAND circuit 204,

208two-level NOR-NOR circuit 209two-level OR-AND circuit 209two-level sum-of-products

expression 466two-pass logic, PLD 395two-phase latch design 765two-phase latch machine 663tWP 826type, VHDL 260

unresolved 427type conversion, VHDL 267type keyword, VHDL 261typical delay 363, 365

U

µA (microampere) 88µ-law PCM 816unambiguous state diagram 573,

574unary minus, Verilog 301unary plus, Verilog 301unclocked assignment operator, =

248unclocked assignment operator,

ABEL = 246unclocked truth-table operator,

ABEL -> 250unconstrained array type, VHDL

265undefined logic level 8undefined logic value, CMOS 86undefined region 115

underscore 354Verilog 293VHDL 258

underscore, Verilog 293undershoot 153unidirectional error 68unidirectional shift register 730unisims library, Xilinx ISE 272unit under test (UUT) 287, 332,

641, 659universal shift register 730unreset 558unresolved type, VHDL 427unsigned binary multiplication 45unsigned division 47–48unsigned multiplication 45–46unstable total state 592unused inputs 112unused states 560, 561, 563, 584,

616up/down counter 716, 725U.S. Department of Defense (DoD)

256use clause, VHDL 270user-defined type, VHDL 261U.S. patents 74UUT (unit under test) 287, 332,

641, 659

Vvacuum-tube logic 174Vantis Corporation 508variable, Verilog 297variable, VHDL 260, 279variable-assignment statement,

VHDL 280variable declaration, Verilog 297variable declaration, VHDL 260variable keyword, VHDL 260,

279variables vs. nets, Verilog 297–298variables vs. signals, VHDL 752




Index 891

VCC 89VCC bounce 128VDD 89vector, Verilog 295, 299–302vector net, Verilog 296vector padding, Verilog 300vector variable, Verilog 297vee ∨ 187Veitch, E. W. 229Veitch diagram 229verification 241Verilog 9, 15, 22, 290–335

! (logical NOT) 304!= (logical inequality) 304! vs. ~ 304# (delay specifier) 330# (parameter substitution) 309$ (built-in functions and tasks)

293, 329% (modulus) 301&& (logical AND) 304& (AND) 296- (subtraction) 301* (multiplication) 301+ (addition) 301/ (division) 301< (less than) 304<< (shift left) 301<= (less than or equal) 304<= (nonblocking assignment)

315<= vs. = 316= (blocking assignment) 315== (logical equality) 304= vs. <= 316> (greater than) 304>= (greater than or equal) 304>> (shift right) 301?: (conditional operator) 305,

311, 431, 445, 492? bit value 323[] (part-select operator) 752

Verilog (continued)^ (XOR) 296^~ (XNOR) 296{} (concatenation operator)

300, 752| (OR) 296|| (logical OR) 304~ (NOT) 296~^ (XNOR) 296~ vs. ! 304addition 301always block 312always keyword 312ANSI-style port declarations

298arithmetic operators 301array 302array index 302assign keyword 293, 310, 330assignment-statement sizing 300begin-end block 317begin keyword 317behavioral description 312behavioral design 312–329behavioral specification 292bit select 300bit vector 295, 299–302bitwise boolean operators 295blocking assignment operator, =

315blocking assignment statement

315, 331, 648blocking vs. non-blocking

assignments 648, 755boolean operators 295boolean reduction operators 302built-in gate types 306case keyword 321case sensitivity 293case statement 310, 321, 404casex keyword 323casex statement 323

Verilog (continued)casez keyword 323casez statement 323coding style 291, 298, 299, 303,

304, 305, 314, 316, 317, 321, 322, 323, 325, 327, 333, 407, 648, 650, 652, 657

comma in sensitivity list 314comments 293comparison 304compiler 305, 307, 322, 330component instantiation 307concatenation operator {} 300,

752concurrent statement 306

executing 312suspended 312

condition 318conditional operator ?: 305,

311, 431, 445, 492configuration management 293constants 299, 305continuous-assignment

statement 310, 313, 431counters 725–727dataflow description 310–312dataflow design 310–312declarations 291`define directive 305`define vs. parameter 305defparam keyword 309delay statement 331delta delay 331disable keyword 326disable statement 326$display task 329division 301else keyword 318end 317endcase keyword 321endgenerate keyword 310




892 Index

Verilog (continued)end keyword 317endmodule keyword 293, 294expression 303false 303file input/output 329forever statement 325for keyword 324for loop 324for statement 310, 324full case 322function 326function call 327function definition 326function keyword 326gate types, built-in 306generate keyword 310generate statement 506genvar keyword 310identifiers 293if keyword 318if statement 318, 404implicit sensitivity list 313`include directive 305infer a latch 314, 320, 322initial block 332initial keyword 332inout keyword 295, 328inout port 295input/output declarations 295,

327input keyword 293, 295, 327input port 294–295instance statement 307, 313integer keyword 297integer variable 297keywords 293latches 701–702latch inference 314, 320, 322library 308literals 298–299logical expression 304

Verilog (continued)logical operators 303–305logical vs. bitwise negation 755looping statement 324module 291module declaration 294module keyword 293, 294modulus 301$monitor task 329$monitoroff task 329$monitoron task 329multidimensional array 302,

503multiplication 301negedge keyword 334, 646,

702nested if statement 318net 296net declaration 296nets vs. variables 297–298next-state logic 649nonblocking assignment 331nonblocking assignment

operator, <= 315non-blocking assignment

statement 648null statement 317operator precedence 303or keyword 312, 313, 314output keyword 293, 295, 328output logic 649output port 294–295parallel case 321parameter 309parameter declaration 299parameterized modules 309parameter keyword 299parameter substitution 309, 506part-select operator [] 300, 752port-association list 307, 308ports 294–295posedge keyword 334, 646,

702

Verilog (continued)procedural code 312–329procedural statement 312, 313,

315process, simulator 331range specification 295registers 701–702reg variable 297reg vs. register 404, 405relational operators 303–304repeat statement 325replication operator n{} 300reserved words 293scope 293semicolon 317sensitivity list 312–314, 331

implicit 313sensitivity matrix 331, 332shift registers 752–755signal 296signed arithmetic 301simulation 331–332simulation cycle 331simulation time 331simulator 331–332

event list 331–332, 662state-machine coding style 649state memory 649statements 292

executing 312suspended 312

$stop task 329structural description 306–310structural design 306–310structural specification 292subtraction 301synthesis tools 290task 328task call 328task definition 328task enable 328task keyword 328




Index 893

Verilog (continued)test bench 326, 659–662three-state bus 431three-state output 430$time function 329time keyword 330time scale 330`timescale directive 330timing control 325–326,

330–331tri net type 296true 303unary minus 301unary plus 301variable 297variable declaration 297variables vs. nets 297–298vector 295, 299–302vector net 296vector padding 300vector variable 297vs. VHDL 295, 302, 310, 418while statement 325wire net type 296$write task 329z bit value 323

Verilog-1995 291, 293, 298, 303, 503

Verilog-2001 291, 293, 298, 314Verilog HDL See Verilogvery large-scale integration (VLSI)

13, 223custom 381

VHC (Very High-speed CMOS) 143

VHCT (Very High-speed CMOS, TTL compatible) 143

VHDL 9, 15, 20–21, 256–290& (concatenation operator) 265,

751- (subtraction) 488* (multiplication) 502+ (addition) 488

VHDL (continued)/= (inequality) 276, 466:= (variable assignment) 280< (less than) 276<= (less than or equal) 276= (equality) 276, 466> (greater than) 276>= (greater than or equal) 276actual parameters 265after keyword 284architecture 257architecture definition 257, 259architecture keyword 258arguments 265array 263array index 263array keyword 263array literal 264array slice 265array types 263assert statement 288attribute statement 633begin keyword 258behavioral description 278behavioral design 278–284bit_vector type 260bit type 260boolean type 260, 261buffer keyword 259case keyword 282case sensitivity 258case statement 282character type 260, 261coding style 289–290comments 258compiler 257, 266, 269, 270,

294component declaration 272component keyword 272component statement 272concatenation operator & 265,

751

VHDL (continued)concurrent signal-assignment

statement 276conditional 276

concurrent statement 271conditional assignment 278configuration management 258constant declaration 263constant keyword 261constants 263CONV_INTEGER function 268converting types 267counters 721–725dataflow description 275–278dataflow design 275–278delta delay 286design flow 241downto keyword 263, 265else keyword 258, 276, 281elsif keyword 281end keyword 258, 259entity 256entity declaration 257entity keyword 258, 259enum_encoding attribute 633enumerated type 261, 630equality operator (=) 466event attribute 289, 625, 698excitation logic 628, 649exit statement 283false keyword 261for loop 282formal parameters 265function 265function call 265function declaration 271function definition 265function keyword 265generate statement 273, 500generic constant 274generic declaration 274generic keyword 274




894 Index

VHDL (continued)generic map clause 274identifiers 258IEEE 1164, standard logic

package 261, 265, 266, 270

IEEE standard 1076 270if statement 280in keyword 258, 259inout keyword 259integer type 260, 261is keyword 258, 259keywords 258latches 697–699library 269library clause 269multidimensional array 264,

497natural subtype 263next-state logic 628next statement 283not operator 258null statement 268operator overloading 266, 276operator precedence 276others keyword 264, 277, 282,

429out keyword 258, 259output logic 629overlaid functions 468, 488, 502package 269

numeric_std 270std_logic_1164 270std_logic_arith 270,

467–468, 488, 502, 635, 637, 721

std_logic_signed 270, 468

std_logic_unsigned 270, 468

package body keywords 271package keyword 271port 259

VHDL (continued)port keyword 258, 259port map keywords 272predefined types 260procedure 269procedure call 269process 278

running 279sensitivity list 279suspended 279

process keyword 278process statement 278range 262range attribute 268range keyword 262registers 697–701relational operators 276report statement 288reserved words 258resolution function 427resolved type 427result 265return keyword 265, 266selected signal assignment 278selected signal-assignment

statement 277select statement 399sequential signal-assignment

statement 279sequential statements 265,

278–284shift registers 748–752signal declaration 260signal keyword 260signal-sensitivity list 285–286signal-sensitivity matrix 285signals vs. variables 500, 752simulation 285–286simulation cycle 286simulation time 285simulator 285–286

event list 285–286, 645

VHDL (continued)standard, IEEE 1076 270state-machine coding style 628state memory 628std_logic_vector type 265std_logic type 261, 427std_ulogic type 427string 264strong typing 262structural description 273–274structural design 273–274subtype 262, 427subtype keyword 261synthesis tools 256test bench 287–289, 641–644three-state bus 427three-state output 427to keyword 263, 265type 260type keyword 261uncontrained array type 265unresolved type 427use clause 270user-defined type 261variable 260, 279variable-assignment statement

280variable declaration 260variable keyword 260, 279variables vs. signals 752vs. Verilog 295, 302, 310, 418wait statement 285when keyword 258, 276while loop 284work library 269, 269

VHDL-1987 256, 336VHDL-1993 256, 336VHDL-2002 256, 336VHSIC (Very High Speed

Integrated Circuit) 256VIHmin 102, 147




Index 895

VIHmin , TTL 162VILmax 102, 146VILmax, TTL 164VLSI See very large-scale

integrationVOHmin 102VOHmin , TTL 162VOHminC 148VOHminT 148volatile memory 822VOLmax 102VOLmax, TTL 164VOLmaxC 148VOLmaxT 148Volpi, Mike xxiiivoltage, power-supply 365, 593,

597, 775Vulcan 184

Wwafer 11wait statement, VHDL 285Wakerly, John F. xxiv, 1, 73, 74Wakerly, Kate xxivWaser, Shlomo 73waveform editor 240waveform viewer 337WE-controlled write 826wedge ∧ 186weight 26, 37, 46

of MSB 37weighted code 50Weldon, E. J. Jr. 74when keyword, VHDL 258, 276when statement, ABEL 248while loop, VHDL 284while statement, Verilog 325White, E. B. 508widget, iterative 756widget, serial 756Widmer, Albert 74wimpy logic families 689

wired AND 138wired logic 138wire keyword, Verilog 296wire lengths 242with statement, ABEL 620word line 804word processor 9, 10working digital designers xviwork library, VHDL 269, 269worst-case delay 368wrapper 257wrist strap, conductive 113$write task, Verilog 329writeable compact disc (CD-R) 81write cycle 825

SDRAM 838write-enable (WE) input 822write-pulse width 826writing 344www.ddpp.com xx–xxiiiwww.DDPPonline.com xxiwww.prenhall.com/wakerlyinfo

xxii

XXC9500 CPLD 471, 493Xilinx, Inc. xx, 508, 775, 789, 859

ISE (Integrated Software Environment) xx

Xilinx ISE 272, 336, 337, 493, 502, 627, 727

Xilinx University Program xxiiXilinx XC4000 FPGAs 850–858Xilinx XC9500 CPLDs 471, 493,

841–849Xilinx XST synthesis tool 418XNOR gate 233, 447, 463, 715,

719xnor gate, Verilog 306XOR function 234

ABEL 452Verilog 454–457VHDL 452–454

XOR gate 233, 234, 447as comparator 458

xor gate, Verilog 306XOR operation 234XOR structure 719

Zz bit value, Verilog 323ZBT SSRAM with flow-through

outputs 831ZBT SSRAM with pipelined

outputs 832zero-bus-turnaround (ZBT)

SSRAM 831zero-code suppression 73




896 Index




fourth-edition index

Documents