Introduction to comparator:

The Digital Comparator

Another common and very useful combinational logic circuit is that of

the Digital Comparator circuit. Digital or Binary Comparators are made up

from standard AND, NOR and NOT gates that compare the digital signals

present at their input terminals and produce an output depending upon the

condition of those inputs.

For example, along with being able to add and subtract binary numbers we need

to be able to compare them and determine whether the value of input A is

greater than, smaller than or equal to the value at input B etc. The digital

comparator accomplishes this using several logic gates that operate on the

principles of Boolean algebra. There are two main types of Digital

Comparator available and these are.

1. Identity Comparator - an Identity Comparator is a digital comparator that has

only one output terminal for when A = B either "HIGH"  A = B = 1 or

"LOW"  A = B = 0

 

2. Magnitude Comparator - a Magnitude Comparator is a type of digital

comparator that has three output terminals, one each for equality, A = B  greater

than, A > B  and less thanA < B

The purpose of a Digital Comparator is to compare a set of variables or

unknown numbers, for example A (A1, A2, A3, .... An, etc) against that of a

constant or unknown value such as B (B1, B2, B3, .... Bn, etc) and produce an

output condition or flag depending upon the result of the comparison. For

example, a magnitude comparator of two 1-bits, (A and B) inputs would

produce the following three output conditions when compared to each other.

Which means:  A is greater than B,   A is equal to B,  and A is less than B

This is useful if we want to compare two variables and want to produce an

output when any of the above three conditions are achieved. For example,

produce an output from a counter when a certain count number is reached.

Consider the simple 1-bit comparator below.

1-bit Digital Comparator

Then the operation of a 1-bit digital comparator is given in the following Truth

Table.

Truth Table

Inputs Outputs

B A A > B A = B A < B

0 0 0 1 0

0 1 1 0 0

1 0 0 0 1

1 1 0 1 0

You may notice two distinct features about the comparator from the above truth

table. Firstly, the circuit does not distinguish between either two "0" or two "1"'s

as an output A = B is produced when they are both equal, either A = B =

"0" or A = B = "1". Secondly, the output condition for A = B resembles that of a

commonly available logic gate, the Exclusive-NOR or Ex-NOR function

(equivalence) on each of the n-bits giving: Q = A ⊕ B

Digital comparators actually use Exclusive-NOR gates within their design for

comparing their respective pairs of bits. When we are comparing two binary or

BCD values or variables against each other, we are comparing the "magnitude"

of these values, a logic "0" against a logic "1" which is where the

term Magnitude Comparator comes from.

As well as comparing individual bits, we can design larger bit comparators by

cascading together n of these and produce a n-bit comparator just as we did for

the n-bit adder in the previous tutorial. Multi-bit comparators can be constructed

to compare whole binary or BCD words to produce an output if one word is

larger, equal to or less than the other.

A very good example of this is the 4-bit Magnitude Comparator. Here, two 4-

bit words ("nibbles") are compared to each other to produce the relevant output

with one word connected to inputs A and the other to be compared against

connected to input B as shown below.

4-bit Magnitude Comparator

Some commercially available digital comparators such as the TTL 74LS85 or

CMOS 4063 4-bit magnitude comparator have additional input terminals that

allow more individual comparators to be "cascaded" together to compare words

larger than 4-bits with magnitude comparators of "n"-bits being produced.

These cascading inputs are connected directly to the corresponding outputs of

the previous comparator as shown to compare 8, 16 or even 32-bit words.

8-bit Word Comparator

When comparing large binary or BCD numbers like the example above, to save

time the comparator starts by comparing the highest-order bit (MSB) first. If

equality exists, A = B then it compares the next lowest bit and so on until it

reaches the lowest-order bit, (LSB). If equality still exists then the two numbers

are defined as being equal.

If inequality is found, either A > B or A < B the relationship between the two

numbers is determined and the comparison between any additional lower order

bits stops. Digital Comparator are used widely in Analogue-to-Digital

converters, (ADC) and Arithmetic Logic Units, (ALU) to perform a variety of

arithmetic operations.

 

Comparator:

The operation of a single bit digital comparator can be expressed as a truth

table:

Inputs Outputs

0 0 0 1 0

0 1 0 0 1

1 0 1 0 0

1 1 0 1 0

The operation of a two bit digital comparator can be expressed as a truth table:

Inputs Outputs

0 0 0 0 0 1 0

0 0 0 1 1 0 0

0 0 1 0 1 0 0

0 0 1 1 1 0 0

0 1 0 0 0 0 1

0 1 0 1 0 1 0

0 1 1 0 1 0 0

0 1 1 1 1 0 0

1 0 0 0 0 0 1

1 0 0 1 0 0 1

1 0 1 0 0 1 0

1 0 1 1 1 0 0

1 1 0 0 0 0 1

1 1 0 1 0 0 1

1 1 1 0 0 0 1

1 1 1 1 0 1 0

Implementation:

Consider two 4-bit binary numbers A and B such that

Here each subscript represents one of the digits in the numbers.

Equality

The binary numbers A and B will be equal if all the pairs of significant digits of

both numbers are equal, i.e.,

,  ,   and 

Since the numbers are binary, the digits are either 0 or 1 and the boolean

function for equality of any two digits   and   can be expressed as

.

 is 1 only if   and   are equal.

For the equality of A and B, all   variables (for i=0,1,2,3) must be 1.

So the quality condition of A and B can be implemented using

the AND operation as

The binary variable (A=B) is 1 only if all pairs of digits of the two numbers are

equal.

Inequality

In order to manually determine the greater of two binary numbers, we inspect

the relative magnitudes of pairs of significant digits, starting from the most

significant bit, gradually proceeding towards lower significant bits until an

inequality is found. When an inequality is found, if the corresponding bit of A is

1 and that of B is 0 then we conclude that A>B.

This sequential comparison can be expressed logically as:

(A>B) and (A < B) are output binary variables, which are equal to 1 when A>B

or A<B respectively.

Representation:

A value of a fixed-point data type is essentially an [[integer]] that is scaled by a

specific factor determined by the type. For example, the value 1.23 can be

represented as 1230 in a fixed-point data type with scaling factor of 1/1000, and

the value 1230000 can be represented as 1230 with a scaling factor of 1000.

Unlike floating-point data types, the scaling factor is the same for all values of

the same type, and does not change during the entire computation.

The scaling factor is usually a [[power (mathematics)|power]] of 10 (for human

convenience) or a power of 2 (for computational efficiency). However, other

scaling factors may be used occasionally, e.g. a time value in hours may be

represented as a fixed-point type with a scale factor of 1/3600 to obtain values

with one-second accuracy.

The maximum value of a fixed-point type is simply the largest value that can be

represented in the underlying integer type, multiplied by the scaling factor; and

similarly for the minimum value. For example, consider a fixed-point type

represented as a binary integer with ''b'' bits in [[two's complement]] format,

with a scaling factor of 1/2^''f'' (that is, the last ''f'' bits are fraction

bits): the minimum representable value is &minus

Operations:

To convert a number from a fixed point type with scaling factor ''R'' to another

type with scaling factor ''S'', the underlying integer must be multiplied by ''R''

and divided by ''S''; that is, multiplied by the ratio ''R''/''S''. Thus, for example,

to convert the value 1.23 = 123/100 from a type with scaling factor ''R''=1/100

to one with scaling factor ''S''=1/1000, the underlying integer 123 must be

multiplied by (1/100)/(1/1000) = 10, yielding the representation 1230/1000. If

''S'' does not divide ''R'' (in particular, if the new scaling factor ''S'' is less than

the original ''R''), the new integer will have to be [[rounding|rounded]]. The

rounding rules and methods are usually part of the language's specification.

To add or subtract two values of the same fixed-point type, it is sufficient to add

or subtract the underlying integers, and keep their common scaling factor. The

result can be exactly represented in the same type, as long as no [[arithmetic

overflow|overflow]] occurs (i.e. provided that the sum of the two integers fits in

the underlying integer type). If the numbers have different fixed-point types,

with different scaling factors, then one of them must be converted to the other

before the sum.

To multiply two fixed-point numbers, it suffices to multiply the two underlying

integers, and assume that the scaling factor of the result is the product of their

scaling factors. This operation involves no rounding. For example, multiplying

the numbers 123 scaled by 1/1000 (0.123) and 25 scaled by 1/10 (2.5) yields the

integer 123×25 = 3075 scaled by (1/1000)×(1/10) = 1/10000, that is 3075/10000

= 0.3075. If the two operands belong to the same fixed-point type, and the result

is also to be represented in that type, then the product of the two integers must

be explicitly multiplied by the common scaling factor; in this case the result

may have to be rounded, and overflow may occur. For example, if the common

scaling factor is 1/100, multiplying 1.23 by 0.25 entails multiplying 123 by 25

to yield 3075 with an intermediate scaling factor of 1/10000. This then must be

multiplied by 1/100 to yield either 31 (0.31) or 30 (0.30), depending on the

rounding method used, to result in a final scale factor of 1/100.

To divide two fixed-point numbers, one takes the integer quotient of their

underlying integers, and assumes that the scaling factor is the quotient of their

scaling factors. The first division involves rounding in general. For example,

division of 3456 scaled by 1/100 (34.56) and 1234 scaled by 1/1000 (1.234)

yields the integer 3456÷1234 = 3 (rounded) with scale factor (1/100)/(1/1000) =

10, that is, 30. One can obtain a more accurate result by first converting the

[[dividend]] to a more precise type: in the same example, converting 3456

scaled by 1/100 (34.56) to 3456000 scaled by 1/100000, before dividing by

1234 scaled by 1/1000 (1.234), would yield 3456000÷1234 = 2801 (rounded)

with scaling factor (1/100000)/(1/1000) = 1/100, that is 28.01 (instead of 290).

If both operands and the desired result are represented in the same fixed-point

type, then the quotient of the two integers must be explicitly divided by the

common scaling factor.

Binary vs. Decimal:

The two most common classes of fixed-point types are decimal and binary.

Decimal fixed-point types have a scaling factor that is a power of ten; for binary

fixed-point types it is a power of two.

Binary fixed-point types are most commonly used, because the rescaling

operations can be implemented as fast [[bit shift]]s. Binary fixed-point numbers

can represent fractional powers of two exactly, but, like binary floating-point

numbers, cannot exactly represent fractional powers of ten. If exact fractional

powers of ten are desired, then a decimal format should be used. For example,

one-tenth (0.1) and one-hundredth (0.01) can be represented only approximately

by binary fixed-point or binary floating-point representations, while they can be

represented exactly in decimal fixed-point or decimal floating-point

representations. These representations may be encoded in many ways,

including [[Binary-coded decimal|BCD]].

Precision loss and overflow:

Because fixed point operations can produce results that have more bits than the

[[operand]]s, there is possibility for information loss. For instance, the result of

fixed point multiplication could potentially have as many bits as the sum of the

number of bits in the two operands. In order to fit the result into the same

number of bits as the operands, the answer must be [[Rounding|rounded]] or

[[truncated]]. If this is the case, the choice of which bits to keep is very

important. When multiplying two fixed point numbers with the same format, for

instance with <math>I</math> integer bits, and <math>Q</math> fractional

bits, the answer could have up to <math>2I</math> integer bits, and

<math>2Q</math> fractional bits.

For simplicity, many fixed-point multiply procedures use the same result format

as the operands. This has the effect of keeping the middle bits; the

<var>I</var>-number of least significant integer bits, and the <var>Q</var>-

number of most significant fractional bits. Fractional bits lost below this value

represent a precision loss which is common in fractional multiplication. If any

integer bits are lost, however, the value will be radically inaccurate. Some

model-based fixed-point packages<ref name="vsi-fp">VisSim Fixed-Point User

Guide|http://www.vissim.com/downloads/doc/EmbeddedControlsDeveloper_U

Gv80.pdf</ref> allow you to specify a result format different from the input

formats. This allows you to maximize precision and avoid overflow.

Some operations, like divide, often have built-in result limiting so that any

positive overflow results in the largest possible number that can be represented

by the current format. Likewise, negative overflow results in the largest

negative number represented by the current format. This built in limiting is

often referred to as ''saturation''.

Some processors support a hardware [[overflow flag]] that can generate an

[[Exception handling|exception]] on the occurrence of an overflow, but it is

usually too late to salvage the proper result at this point.

Modern development cycles include a prototyping phase which examines the

potential precision loss and overflow of designs using fixed point calculations

before proceeding to physical prototyping.

INTRODUCTION TO XILINX

Migrating Projects from Previous ISE Software Releases

When you open a project file from a previous release, the ISE® software

prompts you to migrate your project. If you click Backup and Migrate or

Migrate Only, the software automatically converts your project file to the

current release. If you click Cancel, the software does not convert your project

and, instead, opens Project Navigator with no project loaded.

Note After you convert your project, you cannot open it in previous versions

of the ISE software, such as the ISE 11 software. However, you can optionally

create a backup of the original project as part of project migration, as

described below.

To Migrate a Project

1. In the ISE 12 Project Navigator, select File > Open Project.

2. In the Open Project dialog box, select the .xise file to migrate.

Note You may need to change the extension in the Files of type field to

display .npl (ISE 5 and ISE 6 software) or .ise (ISE 7 through ISE 10

software) project files.

3. In the dialog box that appears, select Backup and Migrate or

Migrate Only.

4. The ISE software automatically converts your project to an ISE 12

project.

Note If you chose to Backup and Migrate, a backup of the original

project is created at project_name_ise12migration.zip.

5. Implement the design using the new version of the software.

Note Implementation status is not maintained after migration.

Properties

For information on properties that have changed in the ISE 12 software, see

ISE 11 to ISE 12 Properties Conversion.

IP Modules

If your design includes IP modules that were created using CORE Generator™

software or Xilinx® Platform Studio (XPS) and you need to modify these

modules, you may be required to update the core. However, if the core netlist

is present and you do not need to modify the core, updates are not required and

the existing netlist is used during implementation.

Obsolete Source File Types

The ISE 12 software supports all of the source types that were supported in the

ISE 11 software.

If you are working with projects from previous releases, state diagram source

files (.dia), ABEL source files (.abl), and test bench waveform source files

(.tbw) are no longer supported. For state diagram and ABEL source files, the

software finds an associated HDL file and adds it to the project, if possible. For

test bench waveform files, the software automatically converts the TBW file to

an HDL test bench and adds it to the project. To convert a TBW file after

project migration, see Converting a TBW File to an HDL Test Bench.

Migrating Projects from Previous ISE Software Releases

When you open a project file from a previous release, the ISE® software

prompts you to migrate your project. If you click Backup and Migrate or

Migrate Only, the software automatically converts your project file to the

current release. If you click Cancel, the software does not convert your project

and, instead, opens Project Navigator with no project loaded.

Note After you convert your project, you cannot open it in previous versions

of the ISE software, such as the ISE 11 software. However, you can optionally

create a backup of the original project as part of project migration, as

described below.

To Migrate a Project

1. In the ISE 12 Project Navigator, select File > Open Project.

2. In the Open Project dialog box, select the .xise file to migrate.

Note You may need to change the extension in the Files of type field to

display .npl (ISE 5 and ISE 6 software) or .ise (ISE 7 through ISE 10

software) project files.

3. In the dialog box that appears, select Backup and Migrate or

Migrate Only.

4. The ISE software automatically converts your project to an ISE 12

project.

Note If you chose to Backup and Migrate, a backup of the original

project is created at project_name_ise12migration.zip.

5. Implement the design using the new version of the software.

Note Implementation status is not maintained after migration.

Properties

For information on properties that have changed in the ISE 12 software, see

ISE 11 to ISE 12 Properties Conversion.

IP Modules

If your design includes IP modules that were created using CORE Generator™

software or Xilinx® Platform Studio (XPS) and you need to modify these

modules, you may be required to update the core. However, if the core netlist

is present and you do not need to modify the core, updates are not required and

the existing netlist is used during implementation.

Obsolete Source File Types

The ISE 12 software supports all of the source types that were supported in the

ISE 11 software.

If you are working with projects from previous releases, state diagram source

files (.dia), ABEL source files (.abl), and test bench waveform source files

(.tbw) are no longer supported. For state diagram and ABEL source files, the

software finds an associated HDL file and adds it to the project, if possible. For

test bench waveform files, the software automatically converts the TBW file to

an HDL test bench and adds it to the project. To convert a TBW file after

project migration, see Converting a TBW File to an HDL Test Bench.

Using ISE Example Projects

To help familiarize you with the ISE® software and with FPGA and CPLD

designs, a set of example designs is provided with Project Navigator. The

examples show different design techniques and source types, such as VHDL,

Verilog, schematic, or EDIF, and include different constraints and IP.

To Open an Example

1. Select File > Open Example.

2. In the Open Example dialog box, select the Sample Project Name.

Note To help you choose an example project, the Project Description

field describes each project. In addition, you can scroll to the right to see

additional fields, which provide details about the project.

3. In the Destination Directory field, enter a directory name or

browse to the directory.

4. Click OK.

The example project is extracted to the directory you specified in the

Destination Directory field and is automatically opened in Project Navigator.

You can then run processes on the example project and save any changes.

Note If you modified an example project and want to overwrite it with the

original example project, select File > Open Example, select the Sample

Project Name, and specify the same Destination Directory you originally used.

In the dialog box that appears, select Overwrite the existing project and click

OK.

Creating a Project

Project Navigator allows you to manage your FPGA and CPLD designs using

an ISE® project, which contains all the source files and settings specific to your

design. First, you must create a project and then, add source files, and set

process properties. After you create a project, you can run processes to

implement, constrain, and analyze your design. Project Navigator provides a

wizard to help you create a project as follows.

Note If you prefer, you can create a project using the New Project dialog box

instead of the New Project Wizard. To use the New Project dialog box,

deselect the Use New Project wizard option in the ISE General page of the

Preferences dialog box.

To Create a Project

1. Select File > New Project to launch the New Project Wizard.

2. In the Create New Project page, set the name, location, and project

type, and click Next.

3. For EDIF or NGC/NGO projects only: In the Import EDIF/NGC

Project page, select the input and constraint file for the project, and click

Next.

4. In the Project Settings page, set the device and project properties,

and click Next.

5. In the Project Summary page, review the information, and click

Finish to create the project.

Project Navigator creates the project file (project_name.xise) in the directory

you specified. After you add source files to the project, the files appear in the

Hierarchy pane of the Design panel. Project Navigator manages your project

based on the design properties (top-level module type, device type, synthesis

tool, and language) you selected when you created the project. It organizes all

the parts of your design and keeps track of the processes necessary to move the

design from design entry through implementation to programming the targeted

Xilinx® device.

Note For information on changing design properties, see Changing Design

Properties.

You can now perform any of the following:

Create new source files for your project.

Add existing source files to your project.

Run processes on your source files.

Modify process properties.

Creating a Copy of a Project

You can create a copy of a project to experiment with different source options

and implementations. Depending on your needs, the design source files for the

copied project and their location can vary as follows:

Design source files are left in their existing location, and the

copied project points to these files.

Design source files, including generated files, are copied and

placed in a specified directory.

Design source files, excluding generated files, are copied and

placed in a specified directory.

Copied projects are the same as other projects in both form and function. For

example, you can do the following with copied projects:

Open the copied project using the File > Open Project menu

command.

View, modify, and implement the copied project.

Use the Project Browser to view key summary data for the copied

project and then, open the copied project for further analysis and

implementation, as described in Using the Project Browser.

Note Alternatively, you can create an archive of your project, which puts all of

the project contents into a ZIP file. Archived projects must be unzipped before

being opened in Project Navigator. For information on archiving, see Creating

a Project Archive.

To Create a Copy of a Project

1. Select File > Copy Project.

2. In the Copy Project dialog box, enter the Name for the copy.

Note The name for the copy can be the same as the name for the project,

as long as you specify a different location.

3. Enter a directory Location to store the copied project.

4. Optionally, enter a Working directory.

By default, this is blank, and the working directory is the same as the

project directory. However, you can specify a working directory if you

want to keep your ISE® project file (.xise extension) separate from your

working area.

5. Optionally, enter a Description for the copy.

The description can be useful in identifying key traits of the project for

reference later.

6. In the Source options area, do the following:

o Select one of the following options:

o Keep sources in their current locations - to leave the

design source files in their existing location.

If you select this option, the copied project points to the files

in their existing location. If you edit the files in the copied

project, the changes also appear in the original project,

because the source files are shared between the two projects.

o Copy sources to the new location - to make a copy of all

the design source files and place them in the specified Location directory.

If you select this option, the copied project points to the files in the

specified directory. If you edit the files in the copied project, the

changes do not appear in the original project, because the source

files are not shared between the two projects.

o Optionally, select Copy files from Macro Search Path

directories to copy files from the directories you specify in the Macro Search

Path property in the Translate Properties dialog box. All files from the specified

directories are copied, not just the files used by the design.

Note If you added a netlist source file directly to the project as

described in Working with Netlist-Based IP, the file is

automatically copied as part of Copy Project because it is a project

source file. Adding netlist source files to the project is the preferred

method for incorporating netlist modules into your design, because

the files are managed automatically by Project Navigator.

o Optionally, click Copy Additional Files to copy files that were not

included in the original project. In the Copy Additional Files dialog box, use the

Add Files and Remove Files buttons to update the list of additional files to

copy. Additional files are copied to the copied project location after all other

files are copied.

7. To exclude generated files from the copy, such as implementation

results and reports, select Exclude generated files from the copy.

When you select this option, the copied project opens in a state in which

processes have not yet been run.

8. To automatically open the copy after creating it, select Open the

copied project.

Note By default, this option is disabled. If you leave this option

disabled, the original project remains open after the copy is made.

Click OK.

Creating a Project Archive

A project archive is a single, compressed ZIP file with a .zip extension. By

default, it contains all project files, source files, and generated files, including

the following:

User-added sources and associated files

Remote sources

Verilog `include files

Files in the macro search path

Generated files

Non-project files

To Archive a Project

1. Select Project > Archive.

2. In the Project Archive dialog box, specify a file name and

directory for the ZIP file.

3. Optionally, select Exclude generated files from the archive to

exclude generated files and non-project files from the archive.

4. Click OK.

A ZIP file is created in the specified directory. To open the archived project,

you must first unzip the ZIP file, and then, you can open the project.

Note Sources that reside outside of the project directory are copied into a

remote_sources subdirectory in the project archive. When the archive is

unzipped and opened, you must either specify the location of these files in the

remote_sources subdirectory for the unzipped project, or manually copy the

sources into their original location.

INTRODUCTION TO VERILOG HDL

What is HDL

A typical Hardware Description Language (HDL) supports a mixed-

level description in which gate and netlist constructs are used with

functional descriptions. This mixed-level capability enables you to describe

system architectures at a high level of abstraction, then incrementally

refine a design’s detailed gate-level implementation.

HDL descriptions offer the following advantages:

• We can verify design functionality early in the design process. A design

written as an HDL description can be simulated immediately. Design

simulation at this high level — at the gate-level before implementation —

allows you to evaluate architectural and design decisions.

• An HDL description is more easily read and understood than a netlist or

schematic description. HDL descriptions provide technology-independent

documentation of a design and its functionality. Because the initial HDL

design description is technology independent, you can use it again to

generate the design in a different technology, without having to translate

it from the original technology.

• Large designs are easier to handle with HDL tools than schematic tools.

Verilog Overview :

Introduction

Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). A

hardware description Language is a language used to describe a digital

system, for example, a microprocessor or a memory or a simple flip-flop. This

just means that, by using a HDL one can describe any hardware (digital ) at any

level.

Verilog provides both behavioral and structural language structures. These

structures allow expressing design objects at high and low levels of

abstraction. Designing hardware with a language such as Verilog allows using

software concepts such as parallel processing and object-oriented

programming. Verilog has a syntax similar to C and Pascal.

Design Styles

Verilog like any other hardware description language permits the designers to

create a design in either Bottom-up or Top-down methodology.

Bottom-Up Design

The traditional method of electronic design is bottom-up. Each design is

performed at the gate-level using the standard gates. With increasing

complexity of new designs this approach is nearly impossible to maintain.

New systems consist of ASIC or microprocessors with a complexity of

thousands of transistors. These traditional bottom-up designs have to give

way to new structural, hierarchical design methods. Without these new design

practices it would be impossible to handle the new complexity.

Top-Down Design

The desired design-style of all designers is the top-down design. A real

top-down design allows early testing, easy change of different technologies, a

structured system design and offers many other advantages. But it is very

difficult to follow a pure top-down design. Due to this fact most designs are

mix of both the methods, implementing some key elements of both design

styles.

Complex circuits are commonly designed using the top down

methodology. Various specification levels are required at each stage of the

design process.

Abstraction Levels of Verilog

Verilog supports a design at many different levels of abstraction. Three

of them are very important:

Behavioral level

Register-Transfer Level

Gate Level

Behavioral level

This level describes a system by concurrent algorithms (Behavioral). Each

algorithm itself is sequential, that means it consists of a set of instructions that

are executed one after the other. Functions, Tasks and Always blocks are the

main elements. There is no regard to the structural realization of the design.

Register-Transfer Level

Designs using the Register-Transfer Level specify the characteristics of a

circuit by operations and the transfer of data between the registers. An explicit

clock is used. RTL design contains exact timing possibility; operations

are scheduled to occur at certain times. Modern definition of a RTL code is

"Any code that is synthesizable is called RTL code".

Gate Level

Within the logic level the characteristics of a system are described by

logical links and their timing properties. All signals are discrete signals. They

can only have definite logical values (`0', `1', `X', `Z`). The usable operations

are predefined logic primitives (AND, OR, NOT etc gates). Using gate

level modeling might not be a good idea for any level of logic design.

Gate level code is generated by tools like synthesis tools and this Netlist is used

for gate level simulation and for backend.

vlsi design flow

Introduction

Design is the most significant human endeavor: It is the channel through

which creativity is realized. Design determines our every activity as well as the

results of those activities; thus it includes planning, problem solving, and

producing. Typically, the term "design" is applied to the planning and

production of artifacts such as jewelry, houses, cars, and cities. Design is also

found in problem-solving tasks such as mathematical proofs and games.

Finally, design is found in pure planning activities such as making a law

or throwing a party.

More specific to the matter at hand is the design of manufacturable

artifacts. This activity uses all facets of design because, in addition to the

specification of a producible object, it requires the planning of that

object's manufacture, and much problem solving along the way. Design of

objects usually begins with a rough sketch that is refined by adding

precise dimensions. The final plan must not only specify exact sizes, but also

include a scheme for ordering the steps of production. Additional

considerations depend on the production environment; for example,

whether one or ten million will be made, and how precisely the manufacturing

environment can be controlled.

A semiconductor process technology is a method by which working circuits

can be manufactured from designed specifications. There are many such

technologies, each of which creates a different environment or style of design.

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