finale cad lab manual

ELCTRONICS AND COMMUNICATION ENGINEERING

INTRODUCTION TO VHDL

What is VHDL?

VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very

High Speed Integrated Circuit. It can describe the behavior and structure of electronic

systems, but is particularly suited as a language to describe the structure and behavior

of digital electronic hardware designs, such as ASICs and FPGAs as well as

conventional digital circuits.

VHDL is a notation, and is precisely and completely defined by the Language Reference

Manual (LRM). This sets VHDL apart from other hardware description languages, which

are to some extent defined in an ad hoc way by the behavior of tools that use them.

VHDL is an international standard, regulated by the IEEE. The definition of the language

is non-proprietary.

VHDL is not an information model, a database schema, a simulator, a toolset or a

methodology! However, a methodology and a toolset are essential for the effective use

of VHDL.

Simulation and synthesis are the two main kinds of tools which operate on the VHDL

language. The Language Reference Manual does not define a simulator, but

unambiguously defines what each simulator must do with each part of the language.

VHDL does not constrain the user to one style of description. VHDL allows designs to be

described using any methodology - top down, bottom up or middle out! VHDL can be

used to describe hardware at the gate level or in a more abstract way. Successful high

level design requires a language, a tool set and a suitable methodology. VHDL is the

language, you choose the tools, and the methodology... well, I guess that's where

Doulos come in to the equation!

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A Brief History of VHDL

The development of VHDL was initiated in 1981 by the United States Department of

Defense to address the hardware life cycle crisis. The cost of reprocuring electronic

hardware as technologies became obsolete was reaching crisis point, because the

function of the parts was not adequately documented, and the various components

making up a system were individually verified using a wide range of different and

incompatible simulation languages and tools. The requirement was for a language with a

wide range of descriptive capability that would work the same on any simulator and was

independent of technology or design methodology.

Standardization

The standardization process for VHDL was unique in that the participation and feedback

from industry was sought at an early stage. A baseline language (version 7.2) was

published 2 years before the standard so that tool development could begin in earnest in

advance of the standard. All rights to the language definition were given away by the

DoD to the IEEE in order to encourage industry acceptance and investment.

ASIC Mandate

DoD Mil Std 454 mandates the supply of a comprehensive VHDL description with every

ASIC delivered to the DoD. The best way to provide the required level of description is to

use VHDL throughout the design process.

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VHDL '93

As an IEEE standard, VHDL must undergo a review process every 5 years (or sooner) to

ensure its ongoing relevance to the industry. The first such revision was completed in

September 1993, and tools conforming to VHDL '93 are now available.

Summary: History of VHDL

1981 - Initiated by US DoD to address hardware life-cycle crisis

1983-85 - Development of baseline language by Intermetrics, IBM and TI

1986 - All rights transferred to IEEE

1987 - Publication of IEEE Standard

1987 - Mil Std 454 requires comprehensive VHDL descriptions to be delivered with

ASICs

1994 - Revised standard (named VHDL 1076-1993)

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Levels of Abstraction

VHDL can be used to describe electronic hardware at many different levels of

abstraction. When considering the application of VHDL to FPGA/ASIC design, it is

helpful to identify and understand the three levels of abstraction shown opposite -

algorithm, register transfer level (RTL), and gate level. Algorithms are unsynthesizable,

RTL is the input to synthesis, gate level is the output from synthesis. The difference

between these levels of abstraction can be understood in terms of timing.

Levels of abstraction in the context of their time domain

Algorithm

A pure algorithm consists of a set of instructions that are executed in sequence to

perform some task. A pure algorithm has neither a clock nor detailed delays. Some

aspects of timing can be inferred from the partial ordering of operations within the

algorithm. Some synthesis tools (behavioral synthesis) are available that can take

algorithmic VHDL code as input. However, even in the case of such tools, the VHDL

input may have to be constrained in some artificial way, perhaps through the presence of

an ‘algorithm' clock - operations in the VHDL code can then be synchronized to this

clock.

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RTL

An RTL description has an explicit clock. All operations are scheduled to occur in

specific clock cycles, but there are no detailed delays below the cycle level.

Commercially available synthesis tools do allow some freedom in this respect. A single

global clock is not required but may be preferred. In addition, retiming is a feature that

allows operations to be re-scheduled across clock cycles, though not to the degree

permitted in behavioral synthesis tools.

Gates

A gate level description consists of a network of gates and registers instanced from a

technology library, which contains technology-specific delay information for each gate.

Writing VHDL for Synthesis

In the diagram above, the RTL level of abstraction is highlighted. This is the ideal level of

abstraction at which to design hardware given the state of the art of today's synthesis

tools. The gate level is too low a level for describing hardware - remember we're trying to

move away from the implementation concerns of hardware design, we want to abstract

to the specification level - what the hardware does, not how it does it. Conversely, the

algorithmic level is too high a level, most commercially available synthesis tools cannot

produce hardware from a description at this level.

In the future, as synthesis technology progresses, we will one day view the RTL level of

abstraction as the “dirty” way of writing VHDL for hardware and writing algorithmic (often

called behavioral) VHDL will be the norm.

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Scope of VHDL

VHDL is suited to the specification, design and description of digital electronic hardware.

System level

VHDL is not ideally suited for abstract system-level simulation, prior to the hardware-

software split. Simulation at this level is usually stochastic, and is concerned with

modeling performance, throughput, queuing and statistical distributions. VHDL has been

used in this area with some success, but is best suited to functional and not stochastic

simulation.

Digital

VHDL is suitable for use today in the digital hardware design process, from specification

through high-level functional simulation, manual design and logic synthesis down to

gate-level simulation. VHDL tools usually provide an integrated design environment in

this area.

VHDL is not suited for specialized implementation-level design verification tools such as

analog simulation, switch level simulation and worst case timing simulation. VHDL can

be used to simulate gate level fan-out loading effects providing coding styles are

adhered to and delay calculation tools are available. The standardization effort named

VITAL (VHDL Initiative toward ASIC Libraries) is active in this area, and is now bearing

fruit in that simulation vendors have built-in VITAL support. More importantly, many ASIC

vendors have VITAL-compliant libraries, though not all are allowing VITAL-based sign-

off - not yet anyway.

Analogue

In 1999, the IEEE approved Standard 1076.1, which is informally known as VHDL-AMS.

It is a true super-set of VHDL, and includes analog and mixed-signal extensions.

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http://www.vhdl.org/analog/


Design process

The diagram below shows a very simplified view of the electronic system design process

incorporating VHDL. The central portion of the diagram shows the parts of the design

process which are most impacted by VHDL.

Design Flow using VHDL

The diagram below summarizes the high level design flow for an ASIC (ie. gate array,

standard cell) or FPGA. In a practical design situation, each step described in the

following sections may be split into several smaller steps, and parts of the design flow

will be iterated as errors are uncovered.

System-level Verification

As a first step, VHDL may be used to model and simulate aspects of the complete

system containing one or more devices. This may be a fully functional description of the

system allowing the FPGA/ASIC specification to be validated prior to commencing

detailed design. Alternatively, this may be a partial description that abstracts certain

properties of the system, such as a performance model to detect system performance

bottle-necks.

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RTL design and test bench creation

Once the overall system architecture and partitioning is stable, the detailed design of

each FPGA/ASIC can commence. This starts by capturing the design in VHDL at the

register transfer level, and capturing a set of test cases in VHDL. These two tasks are

complementary, and are sometimes performed by different design teams in isolation to

ensure that the specification is correctly interpreted. The RTL VHDL should be

synthesizable if automatic logic synthesis is to be used. Test case generation is a major

task that requires a disciplined approach and much engineering ingenuity: the quality of

the final FPGA/ASIC depends on the coverage of these test cases.

RTL verification

The RTL VHDL is then simulated to validate the functionality against the specification.

RTL simulation is usually one or two orders of magnitude faster than gate level

simulation, and experience has shown that this speed-up is best exploited by doing more

simulation, not spending less time on simulation. In practice it is common to spend 70-

80% of the design cycle writing and simulating VHDL at and above the register transfer

level, and 20-30% of the time synthesizing and verifying the gates.

Look-ahead Synthesis

Although some exploratory synthesis will be done early on in the design process, to

provide accurate speed and area data to aid in the evaluation of architectural decisions

and to check the engineer's understanding of how the VHDL will be synthesized, the

main synthesis production run is deferred until functional simulation is complete. It is

pointless to invest a lot of time and effort in synthesis until the functionality of the design

is validated.

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Benefits of using VHDL

Executable specification

It is often reported that a large number of ASIC designs meet their specifications first

time, but fail to work when plugged into a system. VHDL allows this issue to be

addressed in two ways: A VHDL specification can be executed in order to achieve a high

level of confidence in its correctness before commencing design, and may simulate one

to two orders of magnitude faster than a gate level description. A VHDL specification for

a part can form the basis for a simulation model to verify the operation of the part in the

wider system context (eg. printed circuit board simulation). This depends on how

accurately the specification handles aspects such as timing and initialization. Behavioral

simulation can reduce design time by allowing design problems to be detected early on,

avoiding the need to rework designs at gate level. Behavioral simulation also permits

design optimization by exploring alternative architectures, resulting in better designs.

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1 Getting Started with Quartus® IIEach logic circuit, or subcircuit, being designed with the Quartus® II software is called a project. The software works on one project at a time and keeps all information for that project in a single directory (folder) in the file system. To begin a new logic circuit design, the first step is to create a directory to hold its files.As part of the installation of the Quartus® II software, a few sample projects are placed into a directory called altera \91\qdesigns\vhdl_verilog_tutorial To hold the design files for this tutorial, we will use a directory calledquartus_tutorial. The running example for this tutorial is a simple adder/subtractor circuit, which is defined in the VHDL hardware description language.

Start the Quartus® II software. You should see a display similar to the one in Figure 2. This display consists of several windows that provide access to all the features of the Quartus® II software, which the user selects with the computer mouse. Most of the commands provided by the Quartus® II software can be accessed by using a set of menus that are located below the title bar.

For example, in Figure 2 clicking the left mouse button on the menu named File opens the menu shown in Figure 3. Clicking the left mouse button on the entry Exit exits from the Quartus® II software. In general, whenever the mouse is used to select something, the left button is used. Hence we will not normally specify which button to press. In the few cases when it is necessary to use the right mouse button, it will be specified explicitly.

To see the list of available toolbars, select Tools > Customize > Toolbars. Once a toolbar is opened, it can be moved using the mouse. To see the command associated with an icon, position the mouse over the icon and a tooltip will appear that displays the command name.It is possible to modify the appearance of the display in Figure 2 in many ways.

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Figure 2: The main Quartus® II display.

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2 Starting a New Project

To start working on a new design we first have to define a new design project. The Quartus® II software makes the designer’s task easy by providing support in the form of a wizard.1. Select File > New Project Wizard to reach a window that indicates the capability of this wizard, as shown in Figure 4.

2. Set the working directory to be quartus_tutorial you can use a directory name of your choice. The project must have a name, which is usually the

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same as the top-level design entity that will be included in the project. Choose addersubtractor as the name for both the project and the top-level entity, as shown in Figure 4. Press Next. Since we have not yet created the directory quartus_tutorial, the Quartus® II software displays the pop-up box in Figure 5 asking if it should create the desired directory. Click Yes, which leads to the window in Figure 6.

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3. This window makes it easy to specify which existing files (if any) should be included in the project. Assuming that we do not have any existing files, click Next, which leads to the window in Figure 7.

Figure 7: Choose the device family and a specific device.4. In this window, we can specify the type of device in which the designed circuit will be implemented. Choose the cyclone II® menu item as the target device family. We can let the Quartus® II software select a specific device in the family, or we can choose the device explicitly. We will take the latter approach. From the list of available devices, choose the device called EP2C35F672C6. Press Next, which opens the window in Figure 8.

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5. In this window we can specify any third-party tools that should be used. A commonly used term for CAD software for electronic circuits is EDA tools, where the acronym stands for Electronic Design Automation.This term is used in the Quartus® II messages that refer to third-party tools, which are the tools developed and marketed by companies other than Altera®; Since we will rely solely on the Quartus® II tools, we will not choose any other tools. Press Next. Now, a summary of the chosen settings appears in the screen shown in Figure 9. Press Finish, which returns to the main Quartus® II display. Note that addersubtractor is now specified as the current project, as indicated in the title bar at the top of the display. The screen should look similar to that of Figure 10.

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Fig:8 Summary of the project settings

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3.1 Using the Quartus® II Text EditorThis section demonstrates how to use the Quartus® II Text Editor. to create the addersubtractor.vhd file, or if you have chosen to copy the file from the alteran91\qdesigns\vhdl_verilog_tutorial directory.

1. Select File > New to get the window in Figure 13, choose VHDL File, and click OK. This opens the Text Editor window.

2. The first step is to specify a name for the file that will be created. Select File > Save As to open the pop-up box shown in Figure 14. In the field labeled Save as type choose VHDL File. In the field labeled File name type addersubtractor. Put a checkmark in the box Add file to current project. Click Save, which puts the file into the directory quartus_tutorial and leads to the Text Editor window shown in Figure 15. Type the name in the box under Type the workspace name: and press ok

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3. Enter the VHDL code into the Text Editor Window, which is located on the right side of the screen. Save the file by going to File > Save, or by typing the shortcut Ctrl-s.

3.2 Adding Design Files to a ProjectDesign files can be added to the Quartus® II software which design files it should use as part of the current project. To see the list of files already included in the addersubtractor project, selectAssignments > Settings > Files, which leads to a window similar to the window in Figure 17. An alternative way of making this selection is to go to Project > Add/Remove Files in Project.

4 Compiling the VHDL CodeThe VHDL code is processed by several Quartus® II tools that analyze the code and generate an implementation of it for the target chip. These tools are controlled by the application program called the Compiler.

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1. Run the Compiler by selecting Processing > Start Compilation, or by using the toolbar icon . As the compilation moves through various stages, its progress is reported in the Tasks window on the left side.This window also provides an comprehensive interface to edit, start and monitor different stages of the compilation. Successful (or unsuccessful) compilation is indicated in a pop-up box. Acknowledge it by clicking OK. This leads to the Quartus® II display in Figure 19, in which we have expanded the Entity hierarchy in the top left corner to show all entities in the addersubtractor design. In the message window, located at the bottom of the display, various messages are shown. In case of errors, there will be appropriate messages given.

2. When the compilation is finished, a compilation report is produced. A window showing this report, displayedin Figure 20, is opened automatically. The window can be resized, maximized, or closed in the normal way, and it can be opened at any time either by selecting Processing > Compilation Report or by clicking on the

icon in the toolbar. The report includes a number of sections listed on

ECADLAB(VHDL) 20


the left side of its window. Figure 20 shows the Compiler Flow Summary section, which indicates that only a miniscule amount of chip resources are needed to implement this tiny circuit on the selected FPGA chip.

Simulation:1. Add simulator file by clicking File>New>vector

Waveform File then click OK. As shown in fig.212. Right click on area as show in fig go to insert node or

bus. As show in fig 22.3. On the pop-up window click on node finder press in the

need finder window click on list click on the signals required for simulation. Fig 23.

4. From the Node found window move the signals into selected node window by pressing > and to select all signals press >>. As show in fig 24.

5. Save and give name to wave form file as addersubtractor.vwf.

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6. Click on processing> simulator tool select simulation mode functional and sect waveform file as addersubtractor.vwf. select the two options as shown in fig.

7. Click on Generate functional simulation netlist.8. Then start simulation then open waveform window.9. For further details verify

tutorial_quartusii_intro_vhdl.pdf

Fig :21 create new waveform file

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Fig:22 for inserting new signals

Fig:23 for inserting new signals

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Fig:24 for inserting signals

Fig .25 wave form window with all signals required for simulation

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Fig.26 apply values and required excitations

Fig.27 simulator tool window

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Add excitations as shown in fig.


EXPERIMENT NO.1: GATES

AIM: To simulate internal structure of all gates using VHDL and verify their operation.

APPARATUS:

S.NO COMPONENT QUANTITY

1. IC 7400 1

2. IC 7402 1

3. IC 7404 1

4. IC 7408 1

5. IC 7436 1

6. IC 7486 1

7. IC CD74HC7266 1

8. Digital Trainer Board 1

SOFTWARE USED: Quartus-II

THEORY:

Logic gates: Digital systems are said to be constructed by using logic gates. These

gates are the AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basic

operations are described below with the aid of truth tables.

AND gate

The AND gate is an electronic circuit that gives a high output (1) only if all

its inputs are high. A dot (.) is used to show the AND operation i.e. A.B

for a two input (A & B) AND gate, Y = A.B. Bear in mind that this dot is

sometimes omitted i.e. written as AB

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OR gate

The OR gate is an electronic circuit that gives a high output (1) if one or

more of its inputs are high. A plus (+) is used to show the OR operation.

E.g. output of a 2-input OR gate is Y=A+B.

NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the

input at its output. It is also known as an inverter. If the input variable is A, the

inverted output is known as NOT A. This is also shown as A', or A with a bar

over the top, as shown at the output, i.e., Y= A'

NAND gate

This is a NOT-AND gate which is equal to an AND gate followed by a

NOT gate. The output of a NAND gate is high if any of its inputs are low.

The symbol is an AND gate with a small circle on the output. The small

circle represents inversion.

For a two input(A & B) NAND gate, output Y = (A.B)′ .

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NOR gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT

gate. The output of a NOR gate is low if any of the inputs are high.

The symbol is an OR gate with a small circle on the output. The small

circle represents inversion. For a two input(A & B) NOR gate, output Y =

(A+B)′ .

EXOR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either,

but not both, of its two inputs are high. An encircled plus sign ( ) is used

to show the EOR operation.When inputs are A and B,output Y of EXOR

gate is Y=A B

EXNOR gate

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It

will give a low output if either, but not both, of its two inputs are high.

The symbol is an EXOR gate with a small circle on the output. The small

circle represents inversion.The output Y of a EXNOR gate with inputs

A&B is given by Y=( A B)′ .

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The NAND and NOR gates are called universal gates since with either one the

AND and OR functions and NOT can be generated.

Table 1 is a summary truth table of the input/output combinations for the NOT gate

together with all possible input/output combinations for the other gate functions. Also

note that a truth tables with 'n' inputs has 2n rows. You can compare the outputs of

different gates.

Table 1: Logic gates representation using the Truth table

ALL GATES Output Equations:

Y = A AND B; Y = A OR B;

Y = A NAND B; Y = A NOR B;

Y = A EXOR B; Y = A EXNOR B;

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VHDL CODE:

library IEEE;

use IEEE.std_logic_1164.all;

entity gates is

port ( a: in STD_LOGIC;

b: in STD_LOGIC;

and1: out STD_LOGIC;

or1: out STD_LOGIC;

nor1: out STD_LOGIC;

nand1: out STD_LOGIC;

xor1: out STD_LOGIC;

xnor1: out STD_LOGIC);

end gates;

architecture gates of gates is

begin

and1 <= a and b;

or1 <= a or b;

nor1 <= a nor b;

nand1 <= a nand b;

xor1 <= a xor b;

xnor1 <= a xnor b;

end gates;

DE2 PIN ASSIGNMENTS :

SIGNAL NAME PIN NAME TYPE

A SW[0] PIN_N25 Toggle Switch[0]

B SW[1] PIN_N26 Toggle Switch[1]

AND1 LEDR[0] PIN_AE23 LED Red[0]OR1 LEDR[1] PIN_AF23 LED Red[1]NOR1 LEDR[2] PIN_AB21 LED Red[2]NAND1 LEDR[3] PIN_AC22 LED Red[3]

XOR1 LEDR[4] PIN_AD22 LED Red[4]XNOR1 LEDR[5] PIN_AD23 LED Red[5]

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Fig: Pin planner

EXPECTED RESULTS (HARDWARE):

AND GATE OR GATE

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INPUTS OUTPUT

A B Y

0V 0V 0V

0V 5V 0V

5V 0V 0V

5V 5V 5V

INPUTS OUTPUT

A B Y

0V 0V 0V

0V 5V 5V

5V 0V 5V

5V 5V 5V

31


NAND GATE NOR GATE

EX-OR GATE EX-NOR GATE

EXPECTED RESULTS (SOFTWARE):

AND GATE : when all inputs are high output should be high.

OR GATE : when any of input is high output should be high.

NAND GATE : when any of input is low output should be high.

NOR GATE : when any of input is high output should be low.

EX-OR GATE: when input combination contains odd number of

Ones then only output should be high.

EX-NOR GATE: when input combination contains even number of

ones then only output should be high.

ECADLAB(VHDL)

INPUTS OUTPUT

A B Y

0V 0V 5V

0V 5V 0V

5V 0V 0V

5V 5V 0V

INPUTS OUTPUT

A B Y

0V 0V 5V

0V 5V 5V

5V 0V 5V

5V 5V 0V

INPUTS OUTPUT

A B Y

0V 0V 0V

0V 5V 5V

5V 0V 5V

5V 5V 0V

INPUTS OUTPUT

A B Y

0V 0V 5V

0V 5V 0V

5V 0V 0V

5V 5V 5V

32


RESULTS (SOFTWARE):

Fig: Simulation Report of ALL GATES

RESULTS (HARDWARE):

AND GATE OR GATE

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INPUTS OUTPUT

LEDA B

0 0 OFF

0 1 OFF

1 0 OFF

1 1 ON

INPUTS OUTPUT

LEDA B

0 0 OFF

0 1 ON

1 0 ON

1 1 ON

33


NAND GATE NOR GATE

EX-OR GATE EX-NOR GATE

Fig: Simulation Results of ALL GATES

RESULT:

ALL GATES Internal Structures are Simulated and Verified Using Quartus-IISoftware

and in Hardware Lab Respectively.

INFERENCE:

Theoretical and Practical Results are according to the expected results both for Software

and Hardware.

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INPUTS OUTPUT

LEDA B

0 0 ON

0 1 OFF

1 0 OFF

1 1 OFF

INPUTS OUTPUT

LED A B

0 0 ON

0 1 ON

1 0 ON

1 1 OFF

INPUTS OUTPUT

LEDA B

0 0 OFF

0 1 ON

1 0 ON

1 1 OFF

INPUTS OUTPUT

LEDA B

0 0 ON

0 1 OFF

1 0 OFF

1 1 ON

34


PRECAUTIONS (SOFTWARE):

1) Follow Getting Started Procedure for the Software you are using.

2) Don’t Forget to instantiate IEEE Libraries At the starting of

the code

3) Follow Syntax and Semantics of the VHDL code throughout

PRECAUTIONS (HARDWARE):

1) Apply the voltages to the IC as per the details given in the data

Sheets.

2) Apply the inputs to the respective pins.

3) First decide which one is MSB and LSB.

4) Take the outputs at appropriate pins.

QUESTIONS & ANSWERS:

1) Draw internal diagram of nand gate using RTL logic.

Ans:

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2) What are the universal gates ?

Ans: NAND and NOR gates are called as universal gates.

3) What is the main difference between Exor and Exnor gates ?

Ans: Whenever inputs are same output is low - Exor gate

Whenever inputs are same output is high- Exnor gate

4) What are the Minimum number of nand gates required to implement

Exor gate ?

Ans : FOUR nand gates are required to implement Exor gate

PROCEDURE (SOFTWARE):

1) Follow Getting Started Procedure for the Software you are

using.

2) Don’t forget to instantiate IEEE Libraries at the starting of

the code.

PROCEDURE (HARDWARE):

1) Connect the circuit as per the pin diagram.

2) Give proper VCC voltage to the IC.

3) Supply the inputs according to truth table and verify outputs.

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EXPERIMENT NO.2: D FLIP-FLOP

AIM: To Simulate internal structure of D FLIP FLOP(IC 7474) using VHDL and verify

Its operation.

APPARATUS:


1. IC 7474 1



THEORY:

The IC7474 contains two independent positive-edge-triggered D-type flip-flops with

complementary outputs. The information on the D input is accepted by the flip-flops on

the positive going edge of the clock pulse. The triggering occurs at a voltage level and is

not directly related to the transition time of the rising edge of the clock. The data on the

D input may be changed while the clock is low or HIGH without affecting the outputs as

long as the data setup and hold times are not violated. A LOW logic level on the preset

or clear inputs will set or reset the outputs regardless of the logic levels of the other

inputs. 74LS74 is a dual positive edge triggered D-type FF. It’s features are individual

data Clock Set and reset inputs and Complementary Q and Q΄outputs .The clock input is

level-sensitive. The positive transition of clock pulse between 0.8V and 2.0V should be

equal.

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D-FLIP FLOP DETAILS:

PIN DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTS

PR CLR CLK D Q Q*

L H X X H L

H L X X L H

L L X X H H

H H H H L

H H L L H

H H L X Q0 Q0*

H = HIGH Logic Level X = Either LOW or HIGH Logic Level Clear

L = LOW Logic Level ↑ = Positive-going transition of the clock.

Q0 = The output logic level of Q before the indicated input conditions were and

established.

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INTERNAL DIAGRAM:

D FLIP- FLOP Output Equations:

D = Qt+1

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VHDL CODE:

library IEEE;


entity dff is

port (

d: in STD_LOGIC;

clk: in STD_LOGIC;

clr: in STD_LOGIC;

pr: in STD_LOGIC;

q: out STD_LOGIC;

qbar: out STD_LOGIC);

end dff;

architecture dff of dff is

signal clr1,pr1:std_logic;

begin

clr1<=not clr;

pr1<=not pr;

process(clk,clr1,pr1)

begin

if(pr1='1'and clr1='1')then q<='1';qbar<='1';

elsif(pr1='1'and clr1='0')then q<='1';qbar<='0';

elsif(pr1='0'and clr1='1')then q<='0';qbar<='1';

elsif(clk'event and clk='1')then q<=d;qbar<=not d;

end if;

end process;

end dff;

ECADLAB(VHDL) 40




CLK KEY[0] PIN_G26 PUSHBUTTON[0]

D SW[0] PIN_N25 Toggle Switch[0]

CLR SW[1] PIN_N26 Toggle Switch[1]

PR SW[2] PIN_P25 Toggle Switch[2]

Q LEDR[0] PIN_AE23 LED Red[0]QBAR LEDR[1] PIN_AF23 LED Red[1]


INPUTS OUTPUTS

PR CLR CLK D Q Q*

0 1 X X 5V 0V

1 0 X X 0V 5V

0 0 X X 5V 5V

1 1 1 5V 0V

1 1 0 0V 5V

1 1 0 X Q0 Q0*


ECADLAB(VHDL) 41


When pr = 0, clr = 1 irrespective of clock and D input Q = 1, Q* = 0.



When pr = 1, clr = 1, clock transition is positive and D = 1, Q = 1, Q* = 0.

When pr = 1, clr = 1, clock transition is positive and D = 0, Q = 0, Q* = 1.

When pr = 1, clr = 1, clock = 0, irrespective of D input Q = Q0, Q* = Q0*

Q0 = The output logic level of Q before the indicated input conditions were and

established.



ECADLAB(VHDL) 42



When pr = 1, clr = 1, clock = 0, irrespective of D input Q = Q0, Q* = Q0*

RESULTS (SOFTWARE): Fig: Simulation Report of D FLIP- FLOP

RESULTS (HARDWARE):

INPUTS OUTPUTS

PR CLR CLK D Q LED Q* LED

0 1 X X ON OFF

1 0 X X OFF ON

0 0 X X ON ON

1 1 1 ON OFF

1 1 0 OFF ON

1 1 0 X Q0 Q0*

ECADLAB(VHDL) 43


RESULT:

D FLIP-FLOP Internal Structure is Simulated and Verified Using QUARTUS

IISoftware and in Hardware Lab Respectively.

INFERENCE:


and Hardware.



2) Don’t Forget to instantiate IEEE Libraries at the starting of

the code

3) Follow Syntax and Semantics of the VHDL code throughout



Sheets.



4)Take the outputs at appropriate pins.


1. Why it is called D-FF?

Ans: Due to the reason of transmitting whatever is given as input.

2. Applications of D-FF.

Ans: we can design any circuit easily with D-FF because only one input is involved..

3. Difference between edge-triggered FF, level sensitive FF and master slave FF.

ECADLAB(VHDL) 44


Ans: Edge Triggered FF responds for 1 to 0 (or) 0 to 1 transition whereas level sensitive

FF’s

respond to the level 1(or) 0.

In master-slave FF if the master respond for positive edge then slave responds for

negative

edge.

4. What is a Flip-Flop?

Ans: Flip-Flop is a one bit storage device. It is having two outputs one for normal value

and one for the complement value of the bit stored in it.

5. Explain the operation of D Flip-Flop?

Ans: The binary information present at the data input of the D Flip-Flop is transferred to

Q output when clock pulse input is enabled.

6. What is the advantage of D Flip-Flop when compared with RS Flip-Flop?

Ans: The undesirable condition of indeterminate state in RS Flip-Flop is eliminated in

D Flip-Flop

7. Why D Flip-Flop sometimes called as gated D latch?

Ans: The D Flip-Flop receives the designation from its ability to hold data into its internal

storage such a type of Flip-Flop sometimes called as gated D latch.


1)Follow Getting Started Procedure for the Software you are

using.


the code.





ECADLAB(VHDL) 45


EXPERIMENT NO. 3: DECADE COUNTER

AIM: To Simulate internal structure of Decade Counter(IC 7490) using VHDL and verify

Its operation.

APPARATUS: HARDWARE:


1. IC 7490 1


SOFTWARE: Quartus-II

THEORY:

7490 is a 4-bit ripple type decade counter.

Features are:

Output QA is connected to input B for BCD count. Output QD is connected

to input A for qi-binary count. This counter has a gated ‘O’ reset. This

counter contains 4 master-slave FF’s and additional gating to provide a

divide by two counter.

TRUTH TABLE:

COUNT OUTPUT

QD QC QB QA

0 L L L L

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 L H L H

6 L H H L

7 L H H H

8 H L L L

9 H L L H

H = HIGH; L = LOW

ECADLAB(VHDL) 46


INTERNAL DIAGRAM:

Decade Counter Output Equations:

OUTPUT Q = 0000 when INPUTS ro(1)= 1, ro(2) = 1 and rg(1)= 0 ;

OUTPUT Q = 1001 when INPUTS rg(1)= 1 and rg(2) = 1;

OUTPUT Q = Q + 1 when clock is HIGH

ECADLAB(VHDL) 47

VHDL CODE:

library IEEE;


use IEEE.std_logic_arith.all;

entity dcounter is

port (

clk: in STD_LOGIC;

ro: in STD_LOGIC_VECTOR (2 downto 1):="00";

rg: in STD_LOGIC_VECTOR (2 downto 1):="00";

q:out unsigned(3 downto 0):="0000"

);

end dcounter;

architecture dcounter of dcounter is

begin

process(clk,rg,ro)

variable vq : unsigned(3 downto 0);

begin

if(ro(1)='1'and ro(2)='1'and rg(1)='0')then vq:="0000";

elsif(ro(1)='1'and ro(2)='1'and rg(2)='0')then vq:="0000";

elsif(rg(1)='1'and rg(2)='1')then vq:="1001";

elsif(clk'event and clk='1')then vq:=vq+1;

end if;

if vq(1)='1'and vq(3)='1' then vq:="0000";

end if;

q<=vq;

end process;

end dcounter;

ECADLAB(VHDL) 48




Clk KEY[0] PIN_G26 Pushbutton[0]

Q0 LEDR[0] PIN_AE23 LED Red[0]

Q1 LEDR[1] PIN_AF23 LED Red[1]

Q2 LEDR[2] PIN_AB21 LED Red[2]

Q3 LEDR[3] PIN_AC22 LED Red[3]

R(1) SW[0] PIN_N25 Toggle Switch[0]


RG(1) SW[2] PIN_P25 Toggle Switch[2]

RG(2) SW[3] PIN_AE14 Toggle Switch[3]

ECADLAB(VHDL) 49



COUNT OUTPUT

QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1


Reset inputs Output

RO(1) RO(2) RG(1) RG(2) QD QC QB QA

H H L X L L L L

H H X L L L L L

X X H H H L L H

X L X L

COUNT

L X L X COUNT

L X X L COUNT

X L L X COUNT

RESULTS (SOFTWARE):

ECADLAB(VHDL) 50


Fig: Simulation Report of Decade Counter

ECADLAB(VHDL) 51


RESULTS (HARDWARE):

COUNT OUTPUT

QD LED QC LED QB LED QA LED

0 OFF OFF OFF OFF

1 OFF OFF OFF ON

2 OFF OFF ON OFF

3 OFF OFF ON ON

4 OFF ON OFF OFF

5 OFF ON OFF ON

6 OFF ON ON OFF

7 OFF ON ON ON

8 ON OFF OFF OFF

9 ON OFF OFF ON

RESULT:

Decade Counter internal structure is Simulated and verified using Quartus-IISoftware


INFERENCE:


and Hardware.




the code.

3) Follow Syntax and Semantics of the VHDL code throughout.

ECADLAB(VHDL) 52



1) Apply the voltages to the IC as per the details given in the data sheets.





1. Explain the operation binary counter.

Ans: A counter that follows the binary sequence is called binary counter. An n-bit

binary counter consists of n flip-flops and can count in binary from 0 to 2n-1.

2. What is difference between register and counter?

Ans: A Register is a group of binary cells where each cell stores one bit information.

A sequential circuit that goes through a prescribed sequence of states upon the

application of input pulses is called a counter.

3. What is a decade counter?

Ans: The BCD counter is a decade counter , since it counts from 0 to 9.

4. How many Decade counters are required to count from 0 to 999?

Ans: Three Decade counters are required to count from 0 to 999.

5. Applications of decade counter?

Ans: A decade counter is also known as mod-10 counter or BCD counter. It is used In frequency counter, digital voltmeter, digital voltmeter, wrist watches etc.

6. Applications of counter?

Ans: Digital system use counter in a variety of applications, such as digital clocks,

special sequence generators, time-delay circuits, pulse counters, control

state counters, program counters etc.

ECADLAB(VHDL) 53




2) Don’t forget to instantiate IEEE Libraries at the starting of the code.





ECADLAB(VHDL) 54


EXPERIMENT NO.4: 4 BIT COUNTER

AIM: To Simulate Internal structure of Four Bit Counter (IC 7493) using VHDL and

Verify its operation.

APPARATUS:


1. IC 7493 1



THEORY:

7493 is a 4- bit ripple type binary counter.

- The device consists of 4 master slaves Flip Flops internally connected to provide

Divide by two sections and a divide by eight sections.

- Independent use of first Flip Flop is available if reset function coincides with Reset

of 3-bit ripple through counter.

ECADLAB(VHDL) 55


4 BIT COUNTER DETAILS:

PIN DIAGRAM:

TRUTH TABLE:

COUNT OUTPUT

QO Q1 Q2 Q3

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

14 0 1 1 1

15 1 1 1 1

ECADLAB(VHDL) 56

INTERNAL DIAGRAM:

VHDL CODE:

library IEEE;


use IEEE.std_logic_arith.all;

entity counter4 is

port (

clk: in STD_LOGIC;

r: in STD_LOGIC_VECTOR (1 downto 0);

q: out unsigned(3 downto 0):="0000" );

end counter4;

Architecture counter4 of counter4 is

begin

process (clk)

variable vq : unsigned(3 downto 0);

begin

if(r(0)='1'and r(1)='1')then vq:="0000";

elsif (clk'event and clk='1') then vq:=vq+1;

end if;

q<=vq;

end process;

end counter4;

PIN ASSIGNMENTS :

ECADLAB(VHDL) 57











COUNT OUTPUT

QO Q1 Q2 Q3

0 0V 0V 0V 0V

1 5V 0V 0V 0V

2 0V 5V 0V 0V

3 5V 5V 0V 0V

4 0V 0V 5V 0V

5 5V 0V 5V 0V

ECADLAB(VHDL) 58


6 0V 5V 5V 0V

7 5V 5V 5V 0V

8 0V 0V 0V 5V

9 5V 0V 0V 5V

10 0V 5V 0V 5V

11 5V 5V 0V 5V

12 0V 0V 5V 5V

13 5V 0V 5V 5V

14 0V 5V 5V 5V

15 5V 5V 5V 5V


If R0(1) ,R0(2) inputs are high then output will be low

else if any one of the input is high count will be increased by one.

Fig: Simulation Report of Four Bit Counter

RESULTS (HARDWARE):

ECADLAB(VHDL) 59


COUNT OUTPUT

QOLED Q1LED Q2LED Q3LED

0 OFF OFF OFF OFF

1 ON OFF OFF OFF

2 OFF ON OFF OFF

3 ON ON OFF OFF

4 OFF OFF ON OFF

5 ON OFF ON OFF

6 OFF ON ON OFF

7 ON ON ON OFF

8 OFF OFF OFF ON

9 ON OFF OFF ON

10 OFF ON OFF ON

11 ON ON OFF ON

12 OFF OFF ON ON

13 ON OFF ON ON

14 OFF ON ON ON

15 ON ON ON ON

RESULT:

Four Bit Counter internal structure is Simulated and verified using Quartus-IISoftware


INFERENCE:

ECADLAB(VHDL) 60


Theoretical and Practical results are according to the expected results both for Software

and Hardware.



2) Don’t forget to instantiate IEEE Libraries At the starting of

the code.




Sheets.





1. What is the difference between synchronous counter and asynchronous counter?

Ans: In asynchronous counter flip flops are connected in such a way that output of first

flip flop drives the clock for next flip flop.

In synchronous counter there is no connection between output of first flip flop and clock

input of next flip flop.

2. Which type of counter is preferred when there are more number of flip flops and why

such a type of counter is preferred?

ECADLAB(VHDL) 61


Ans: synchronous counter is preferred because clock is simultaneously given to all flip

flops there is no problem of propagation delay

3. If a four-bit synchronous counter is designed with 4 flip flops and two AND gates then

determine f max if t pd (propagation delay time ) for each flip flop is 50ns and t pd for each

AND gate is 20ns?

Ans: For a synchronous counter total delay that must be allowed between input clock

pulses is equal to flip flop t pd + AND gate t pd .Thus Tclk 50 + 20 = 70ns and so counter

has f max = 1/ 70ns = 14.3Mhz.

4. A counter has 14 stable states 0000 through 1101 .If input frequency is 50khz what

will be its output frequency?

Ans: Input frequency /number of stable states = output frequency

50 kHz / 14 = 3.57 kHz.


1)Follow Getting Started Procedure for the Software you are

using.

2)Don’t Forget to instantiate IEEE Libraries at the starting of

the code.





EXPERIMENT NO.5: UNIVERSAL SHIFT REGISTER

ECADLAB(VHDL) 62


AIM: To Simulate Internal structure of Universal Shift Register (IC 74194/195) using

VHDL and Verify its operation.

APPARATUS:


1. IC 74194/195 1



THEORY (HARDWARE):

The 74194 is a bidirectional shift register designed to incorporate virtually all of the

features a system designer want in a shift register. The circuit contains 46 equivalent

gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs,

operating mode control inputs and a direct overriding clear line. The register has four

distinct modes of operation namely;

Parallel (Broadside) Load

Shift Right (In the direction of QA toward QD)

Shift Left (In the direction of QD toward QA)

Inhibit Clock (Do nothing)

Synchronous parallel loading is accomplished by applying the four bits of data and

taking both mode control inputs, S0 and S1, high. The data is loaded into the associated

flip flop and appears at the outputs after the positive transition of the clock input. During

loading, serial data flow is inhibited.

Shift right is accomplished synchronously with the rising edge of the clock pulse when S0

is high and S1 is low. Serial data for this mode is entered at the shift-left serial input.

Clocking of the flip flop is inhibited when both mode control inputs are low. The mode

controls should be changed only while the clock input is high.

SHIFT REGISTER DETAILS:

ECADLAB(VHDL) 63


PIN DIAGRAM:

TRUTH TABLE:

INPUTS OUTPUTS

CLEAR MODE CLOCK SERIAL PARALLEL QA QB QC QD

S1 S0 LEFT RIGHT A B C D

L X X X X X X X X X L L L L

H X X L X X X X X X QA0 QB0 QC0 QD0

H H H X X a b c d a b c d

H L H X H X X X X H QAN QBN QCN

H L H X L X X X X L QAN QBN QCN

H H L H X X X X X QBN QCN QDN H

H H L L X X X X X QBN QCN QDN L

H L L X X X X X X X QA0 QB0 QC0 QD0

INTERNAL DIAGRAM:

ECADLAB(VHDL) 64


VHDL CODE:

library IEEE;

ECADLAB(VHDL) 65

entity pshift is

port (

clr: in STD_LOGIC;

ro: in STD_LOGIC;

lo: in STD_LOGIC;

clk: in STD_LOGIC;

s: in STD_LOGIC_VECTOR (0 to 1);

ip: in STD_LOGIC_VECTOR (0 to 3);

q: out STD_LOGIC_VECTOR (0 to 3)

);

end pshift;

architecture pshift of pshift is

signal qin:std_logic_vector(0 to 3);

begin

process(clk,clr,ip,ro,lo,s)

variable vq:std_logic_vector(0 to 3);

begin

if(clk'event and clk='1')then

if(clr='0')then vq:="0000";

elsif(s="01")then vq:=ro&vq(0)&vq(1)&vq(2);

elsif(s="10")then vq(0):=vq(1);vq(1):=vq(2);vq(2):=vq(3);vq(3):=lo;

elsif(s="00")then vq:=ip;

end if;

end if;

q<=vq;

end process;

end pshift;

UNIVERSAL SHIFT REGISTER OUTPUT EQUATIONS:

QA = (QB S0`+ A(S0)`+(S1)`)` + (S1)`(SRSI))`

ECADLAB(VHDL) 66


QB = (QA S0`+ B(S0)`+(S1)`)` + (S1)`(QA))`

QC = (QB S0`+ C(S0)`+(S1)`)` + (S1)`(QB))`

QD = (QC S0`+ D(S0)`+(S1)`)` + (S1)`(QC))`

SRSI = Shift Right Serial Input


DATAIN inputs are “011010000” in that order.


S = 00 then Parallel load

S = 01 then Serial out

S = 10 then Left Shift

RESULTS (SOFTWARE):

ECADLAB(VHDL)

0 0 0 0

1 0 0 0

1 1 0 0

0 1 1 0

1 0 1 1

0 1 0 1

0 0 1 0

0 0 0 1

0 0 0 0

67


Fig: Simulation Report of Shift Register

DE2 BOARD PIN ASSIGNMENTS :

ECADLAB(VHDL) 68









L(0) SW[1] PIN_N26 Toggle Switch[1]

S(0) SW[2] PIN_P25 Toggle Switch[2]

S(1) SW[3] PIN_AE14 Toggle Switch[3]

IP(0) SW[4] PIN_AF14 Toggle Switch[4]

IP(1) SW[5] PIN_AD13 Toggle Switch[5]

IP(2) SW[6] PIN_AC13 Toggle Switch[6]

IP(3) SW[7] PIN_C13 Toggle Switch[7]

CLR SW[8] PIN_B13 Toggle Switch[8]

RESULTS (HARDWARE):

ECADLAB(VHDL) 69



INPUTS OUTPUTS



0 X X X X X X X X X 0 0 0 0

1 X X 0 X X X X X X QA0 QB0 QC0 QD0

1 1 1 X X a b c d a b c d

1 0 1 X 1 X X X X 1 QAN QBN QCN


1 1 0 1 X X X X X QBN QCN QDN 1


1 0 0 X X X X X X X QA0 QB0 QC0 QD0


clock= 1 ; input e= 1; input l= 1 output q = r ; output q(0) = q(1); q(1) = q(2); and so

on up to q(n-2) = q(n-1). q(n-1) = input w;

Fig: Compilation Report of Universal Shift Register

RESULTS (HARDWARE):

ECADLAB(VHDL) 70


INPUTS OUTPUTS



0 X X X X X X X X X 0 0 0 0

1 X X 0 X X X X X X QA0 QB0 QC0 QD0

1 1 1 X X a b c d a b c d





1 0 0 X X X X X X X QA0 QB0 QC0 QD0

Universal Shift Register internal structure is simulated and verified using QUARTUS II

Software and in Hardware Lab Respectively.

INFERENCE:


and Hardware.






1) Apply the voltages to the IC as per the details given in the data Sheets.

ECADLAB(VHDL) 71






1) What are the features of universal shift register

Ans: This register has both left and right shifts and parallel load capabilities.

2) Mention any two applications of shift register.

Ans: i) Delay line:

A Serial- in serial-out shift register used to introduce time delay in

digital signals. The time delay can be given as = N X 1/fc. (N = No. of stages, fc is

clock frequency).

ii) Pseudo random binary sequence (PRBS) generator:

A suitable feed back is used to generate PRBS.

3) What do you mean by parallel load in universal shift register?

Ans: The binary information on parallel input lines is transferred into the universal

shift register simultaneously.

4) Differentiate between bidirectional and universal shift registers.

Ans: Bidirectional shift register capable of shifting in both left and right directions.

Universal shift register has both left and right shifts and parallel load capabilities.



using.


the code.

ECADLAB(VHDL) 72






ECADLAB(VHDL) 73


EXPERIMENT NO.6: 3-to-8 DECODER

AIM: To Simulate the internal structure of a 3- to-8 decoder (IC 74138) using VHDL

and verify its operation.

APPARATUS:


1. IC 74LS138 1



THEORY:

These Schottky-clamped circuits are designed to be used in high-performance memory-

decoding or data-routing applications, requiring very short propagation delay times. In

high-performance memory systems these decoders can be used to minimize the effects

of system decoding. When used with high-speed memories, the delay times of these

decoders are usually less than the typical access time of the memory. This means that

the effective system delay introduced by the decoder is negligible. The DM74LS138

decodes one-of-eight lines; based upon the conditions at the three binary select inputs

and the three enable inputs. Two active-low and one active-high enable inputs reduce

the need for external gates or inverters when expanding. A 24-line decoder can be

implemented with no external inverters, and a 32-line decoder requires only one inverter.

An enable input can be used as a data input for demultiplexing applications. The

DM74LS139 comprises two separate two-line-to-four line decoders in a single package.

The active-low enable input can be used as a data line in demultiplexing applications. All

of these decoders/demultiplexers feature fully buffered inputs, presenting only one

normalized load to its driving circuit. All inputs are clamped with high-performance

Schottky diodes to suppress line-ringing and simplify system design.

Absolute Maximum Ratings:

ECADLAB(VHDL) 74


The “Absolute Maximum Ratings” are those values beyond which the safety of the

device cannot be guaranteed. The device should not be operated at these limits. The

parametric values defined in the Electrical Characteristics tables are not guaranteed at

the absolute maximum ratings. The “Recommended Operating Conditions” table will

define the conditions for actual device operation. An N-bit decoder has 2N outputs, only

one of which may be activated at a given time. If the device is active-HIGH, then only

one output may be HIGH at any time. If the device is active-LOW, then only one output

may be LOW at any time.

DECODER DETAILS:

TRUTH TABLE:

INPUTS OUTPUTS

G1 G2* C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X L X X X H H H H H H H H

H X X X X H H H H H H H H

L H L L L H L L L L L L L

L H L L H L H L L L L L L

L H L H L L L H L L L L L

L H L H H L L L H L L L L

L H H L L L L L L H L L L

L H H L H L L L L L H L L

L H H H L L L L L L L H L

L H H H H L L L L L L L H

H = high level , L = low level, X = Don’t Care

G2* = G2*A + G2*B

ECADLAB(VHDL) 75


INTERNAL DIAGRAM:

3- 8 Decoder Output Equations:

Y0 = X2` X1` X0` Y4 = X2 X1` X0`

Y1 = X2 ` X1 `X0 Y5 = X2 X1 `X0

Y2 = X2 ` X1 X0` Y6 = X2 X1X0`

Y3 = X2 ` X1X0 Y7 = X2 X1X0

ECADLAB(VHDL) 76

VHDL CODE:

Library IEEE;

use IEEE.Std_Logic_1164.All;

ENTITY decoder IS

PORT (sel: IN STD_LOGIC_VECTOR (2 downto 0) ;

outZ: OUT STD_LOGIC_VECTOR (7 downto 0)

);

END decoder;

ARCHITECTURE DATA_FLOW OF decoder IS

BEGIN

WITH sel SELECT

outZ <= "00000001" WHEN "000",

"00000010" WHEN "001",

"00000100" WHEN "010",

"00001000" WHEN "011",

"00010000" WHEN "100",

"00100000" WHEN "101",

"01000000" WHEN "110",

"10000000" WHEN "111";

END DATA_FLOW;

ECADLAB(VHDL) 77




SEL(0) SW[0] PIN_N25 Toggle Switch[0]


SEL(2) SW[2] PIN_P25 Toggle Switch[2]

outZ(0) LEDR[0] PIN_AE23 LED Red[0]

outZ(1) LEDR[1] PIN_AF23 LED Red[1]

outZ(2) LEDR[2] PIN_AB21 LED Red[2]

outZ(3) LEDR[3] PIN_AC22 LED Red[3]

outZ(4) LEDR[4] PIN_AD22 LED Red[4]



outZ(7) LEDR[7] PIN_AC21 LED Red[7]

ECADLAB(VHDL) 78



INPUTS OUTPUTS

C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 5V 0V 0V 0V 0V 0V 0V 0V

0 0 1 0V 5V 0V 0V 0V 0V 0V 0V

0 1 0 0V 0V 5V 0V 0V 0V 0V 0V

0 1 1 0V 0V 0V 5V 0V 0V 0V 0V

1 0 0 0V 0V 0V 0V 5V 0V 0V 0V

1 0 1 0V 0V 0V 0V 0V 5V 0V 0V

1 1 0 0V 0V 0V 0V 0V 0V 5V 0V

1 1 1 0V 0V 0V 0V 0V 0V 0V 5V


Z7 Should be 1 when Sel = 000








ECADLAB(VHDL) 79


RESULTS (SOFTWARE):

Fig: Simulation Report of 3-to-8 DECODER

RESULTS (HARDWARE):

INPUTS OUTPUTS

G1 G2* C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

LED LED LED LED LED LED LED LED

X L X X X ON ON ON ON ON ON ON ON

H X X X X ON ON ON ON ON ON ON ON

L H L L L ON OFF OFF OFF OFF OFF OFF OFF

L H L L H OFF ON OFF OFF OFF OFF OFF OFF

L H L H L OFF OFF ON OFF OFF OFF OFF OFF

L H L H H OFF OFF OFF ON OFF OFF OFF OFF

L H H L L OFF OFF OFF OFF ON OFF OFF OFF

L H H L H OFF OFF OFF OFF OFF ON OFF OFF

L H H H L OFF OFF OFF OFF OFF OFF ON OFF

L H H H H OFF OFF OFF OFF OFF OFF OFF ON

H = high level , L = low level, X = Don’t Care

G2* = G2*A + G2*B

ECADLAB(VHDL) 80


RESULT:

3-to-8 DECODER internal structure is Simulated and verified using Quartus-II


INFERENCE:


and Hardware.




the code.

3) Follow Syntax and Symantics of the VHDL code throughout.






ECADLAB(VHDL) 81



1) Explain about decoder.

Ans: A decoder is a multiple input, multiple output logic circuit which converts coded

inputs into coded outputs, where input and output codes are different. The input code

generally has fewer bits than output code.

2) Explain about binary decoder.

Ans: A decoder which has n-bit binary input code and one activated output out-of-2n

output code is called Binary decoder.

3) Explain basic concept of 3-to-8 line decoder.

Ans: Three inputs are decoded into eight outputs, each output represent one

of minterms of the three input variables.

4) Implement 3-to-8 line decoder using 2-to-4 line decoder ?

Ans:

Fig: 3 to 8 line decoder using 2 to 4 line decoder

ECADLAB(VHDL) 82









ECADLAB(VHDL) 83

EXPERIMENT NO.7: 4 BIT COMPARATOR

AIM: To Simulate internal structure of 4 Bit Comparator(IC 7485) using VHDL and


APPARATUS:


THEORY:

This four-bit magnitude comparator performs comparison of straight binary or BCD

codes. Three fully-decoded decisions about two, 4-bit words {A, B} are made and are

externally available at three outputs. This device is fully expandable to any number of

bits without external gates. Words of greater length may be compared by connecting

comparators in cascade. The A>B, A<B, and A=B outputs of a stage handling less

significant bits are connected to the corresponding inputs of the next stage handling

more-significant bits. The stage handling the least-significant bits must

have a high level voltage applied to the A=B input.

ECADLAB(VHDL)


1. IC 7485 1


84

FOUR BIT COMPARATOR DETAILS:

TRUTH TABLE:

COMPARING INPUTS CASCADING

INPUTS

OUTPUTS

A3>B3 A2>B2 A1>B1 AO>BO A>B AB AB3 X X X X X X X X X H L L

A3<B3 X X X X X X X X X L H L

A3=B3 A2>B2 X X X X X X X H L L

A3=B3 A2<B2 X X X X X X X L H L

A3=B3 A2=B2 A1>B1 X X X X X H L L

A3=B3 A2=B2 A1<B1 X X X X X L H L

A3=B3 A2=B2 A1=B1 AO>BO X X X H L L

A3=B3 A2=B2 A1=B1 AO<BO X X X L H L

A3=B3 A2=B2 A1=B1 AO=BO H L L H L L

A3=B3 A2=B2 A1=B1 AO=BO L H L L H L

A3=B3 A2=B2 A1=B1 AO=BO L L H L L H

A3=B3 A2=B2 A1=B1 AO=BO H H L L L L

A3=B3 A2=B2 A1=B1 AO=BO L L L H H L

ECADLAB(VHDL) 85


INTERNAL DIAGRAM:

ECADLAB(VHDL) 86

FOUR BIT COMPARATOR OUTPUT EQUATIONS:

A<B = (A3(A3B3)`)` ((A0B0)À0 + (A0B0)`B0)` (CIAGB) ((A1B1)À1 + (A1B1)`B1)` (A2B2)À2 +

(A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` ((A0B0)À0 + (A0B0)`B0)` (CIAEQB) ((A1B1)À1

+(A1B1)`B1)` (A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` ((A0) (A0B0)`

((A1B1)À1 +(A1B1)`B1)` (A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)`

((A1B1)À1(A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` )( (A3B3)À3 +

(A3B3)`B3)`(A2B2)À2)`.

A>B = (B3(A3B3)`)` ((A0B0)À0 + (A0B0)`B0)` (CIALB) ((A1B1)À1 + (A1B1)`B1)` (A2B2)À2 +

(A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` ((A0B0)À0 + (A0B0)`B0)` (CIAEQB) ((A1B1)À1

+(A1B1)`B1)` (A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` ((B0) (A0B0)`

((A1B1)À1 +(A1B1)`B1)` (A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)`

((A1B1)`B1(A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)`) ((A3B3)À3 + (A3B3)`B3)`

(A2B2)`B2)`.

(A=B) = (A3B3)À3 + (A3B3)`B3)` (A2B2)À2 + (A2B2)`B2)` ((A1B1)À1 +(A1B1)`B1)`

((A0B0)À0 + (A0B0)`B0)` (CIAEQB).

CIAGB = Cascading Input A Greater than B

CIAEQB = Cascading Input A Equal to B

CIALB = Cascading Input A Less than B

ECADLAB(VHDL) 87

VHDL CODE:

library IEEE;


entity bit4 is

port (

a: in STD_LOGIC_vector(3 downto 0);

b: in STD_LOGIC_vector(3 downto 0);

cg: in STD_LOGIC; -- Cascading input greater

ce: in STD_LOGIC; -- Cascading input equal

cl: in STD_LOGIC; -- Cascading input less than

agb: out STD_LOGIC; --output A greater than B

aeb: out STD_LOGIC; --output A equal to B

alb: out STD_LOGIC); ----output A less than B

end bit4;

architecture bit4 of bit4 is

begin

process(a,b,cg,ce,cl)

variable cas : std_logic_vector(2 downto 0);

begin

cas:= cg&ce&cl;

if cas="010" then

if a(3)<b(3) then agb<='0'; alb<='1';aeb<='0';

elsif a(3)>b(3) then agb<='1'; alb<='0';aeb<='0';

elsif a(2)>b(2) then agb<='1'; alb<='0';aeb<='0';

elsif a(2)<b(2) then agb<='0'; alb<='1';aeb<='0';

elsif a(1)>b(1) then agb<='1';alb<='0';aeb<='0';

elsif a(1)<b(1) then agb<='0';alb<='1';aeb<='0';

elsif a(0)>b(0) then agb<='1';alb<='0';aeb<='0';

elsif a(0)<b(0) then agb<='0';alb<='1';aeb<='0';

else agb<='0'; alb<='0';aeb<='1';

end if;

else if cas="100" then agb<='1';alb<='0';aeb<='0';

ECADLAB(VHDL) 88

else if cas="001" then agb<='0'; alb<='1';aeb<='0';

end if;

end if;

end if;

end process;

end bit4;



alb LEDR[0] PIN_AE23 LED Red[0]

aeb LEDR[1] PIN_AF23 LED Red[1]

agb LEDR[2] PIN_AB21 LED Red[2]

a(0) SW[0] PIN_N25 Toggle Switch[0]

a(1) SW[1] PIN_N26 Toggle Switch[1]

a(2) SW[2] PIN_P25 Toggle Switch[2]

a(3) SW[3] PIN_AE14 Toggle Switch[3]

b(0) SW[4] PIN_AF14 Toggle Switch[4]

b(1) SW[5] PIN_AD13 Toggle Switch[5]

b(2) SW[6] PIN_AC13 Toggle Switch[6]

b(3) SW[7] PIN_C13 Toggle Switch[7]

cl SW[8] PIN_B13 Toggle Switch[8]

ce SW[9] PIN_A13 Toggle Switch[9]

cg SW[10] PIN_N1 Toggle Switch[10]

ECADLAB(VHDL) 89

INPUTS

OUTPUTS

A3>B3 A2>B2 A1>B1 AO>BO A>B AB AB3 X X X X X X X X X 5V 0V 0V

A3<B3 X X X X X X X X X 0V 5V 0V

A3=B3 A2>B2 X X X X X X X 5V 0V 0V

A3=B3 A2<B2 X X X X X X X 0V 5V 0V

A3=B3 A2=B2 A1>B1 X X X X X 5V 0V 0V

A3=B3 A2=B2 A1<B1 X X X X X 0V 5V 0V

A3=B3 A2=B2 A1=B1 AO>BO X X X 5V 0V 0V

A3=B3 A2=B2 A1=B1 AO<BO X X X 0V 5V 0V

A3=B3 A2=B2 A1=B1 AO=BO 1 0 0 5V 0V 0V

A3=B3 A2=B2 A1=B1 AO=BO 0 1 0 0V 5V 0V

A3=B3 A2=B2 A1=B1 AO=BO 0 0 1 0V 0V 5V

A3=B3 A2=B2 A1=B1 AO=BO 1 1 0 0V 0V 0V

ECADLAB(VHDL) 90


A3=B3 A2=B2 A1=B1 AO=BO 0 0 0 5V 5V 0V


Agb should be HIGH when data A is Greater than data B

Alb should be HIGH when data A is less than data B

Aeb should be HIGH when data A is Equal data B

ECADLAB(VHDL) 91


Fig: Simulation Report of 4 bit Comparator

ECADLAB(VHDL) 92

RESULTS (HARDWARE):


INPUTS

OUTPUTS

A3>B3 A2>B2 A1>B1 AO>BO A>B AB

LED

AB3 X X X X X X X X X ON OFF OFF

A3<B3 X X X X X X X X X OFF ON OFF

A3=B3 A2>B2 X X X X X X X ON OFF OFF

A3=B3 A2<B2 X X X X X X X OFF ON OFF

A3=B3 A2=B2 A1>B1 X X X X X ON OFF OFF

A3=B3 A2=B2 A1<B1 X X X X X OFF ON OFF

A3=B3 A2=B2 A1=B1 AO>BO X X X ON OFF OFF

A3=B3 A2=B2 A1=B1 AO<BO X X X OFF ON OFF

A3=B3 A2=B2 A1=B1 AO=BO 1 0 0 ON OFF OFF

A3=B3 A2=B2 A1=B1 AO=BO 0 1 0 OFF ON OFF

A3=B3 A2=B2 A1=B1 AO=BO 0 0 1 OFF OFF ON

A3=B3 A2=B2 A1=B1 AO=BO 1 1 0 OFF OFF OFF

A3=B3 A2=B2 A1=B1 AO=BO 0 0 0 ON ON OFF

Fig: Simulation Results of 4 bit Comparator

ECADLAB(VHDL) 93


RESULT:

Four bit Comparator internal structure is Simulated and verified using Quartus-


INFERENCE:


and Hardware.




the code.




Sheets.





1) Explain concept of magnitude comparator.

Ans: It is a special type of combinational circuit designed primarily to compare the

relative magnitude of two binary numbers.

2) What is the main feature of IC 7485?

Ans: IC 7485 is a four- bit comparator used to compare two four-bit binary inputs.

ECADLAB(VHDL) 94


3) Draw the block diagram for magnitude comparator.

Ans:



using.


the code.





ECADLAB(VHDL) 95


EXPERIMENT NO.8: 8X1 MULTIPLEXER

AIM: To Simulate internal structure of 8X1 MULTIPLEXER (IC 74151) using VHDL and

verify its operation.

APPARATUS:


1. IC 74151 1



THEORY:

74LS51 is a logical implementation of a single-pole, 8-position switch with Switch

position controlled by the state of three select inputs S0,S1,S2.

- Multi function capability.

- Complementary outputs.

DETAILS: TRUTH TABLE:

INPUT OUTPUT

SELECT STROBE W Y

C B A S

X X X H H L

L L L L DO’ DO

L L H L D1΄ D1

L H L L D2΄ D2

L H H L D3΄ D3

H L L L D4΄ D4

H L H L D5΄ D5

H H L L D6΄ D6

H H H L D7΄ D7

ECADLAB(VHDL) 96


INTERNAL DIAGRAM:

OUTPUT EQUATIONS:

D0 = A`B`C` D1 = AB`C` D2 = A`BC` D3 = ABC` D4 = A`B`C

D5 = AB`C D6 = A`BC D7 = ABC

ECADLAB(VHDL) 97

VHDL CODE:

library IEEE;


entity mux is

port ( a: in STD_LOGIC;

b: in STD_LOGIC;

c: in STD_LOGIC;

input: in STD_LOGIC_VECTOR(7 downto 0);

en: in STD_LOGIC;

output: out STD_LOGIC );

end mux;

Architecture mux of mux is

signal sel: std_logic_vector(2 downto 0);

begin

sel<=c&b&a;

process (sel,input,en)

begin

if(en='0')then output<='Z';

else

case sel is

when "000"=> output<= input(0);








end case;

end if;

end process;

end mux;

ECADLAB(VHDL) 98




output LEDR[0] PIN_AE23 LED Red[0]

a SW[0] PIN_N25 Toggle Switch[0]

b SW[1] PIN_N26 Toggle Switch[1]

c SW[2] PIN_P25 Toggle Switch[2]

input(0) SW[3] PIN_AE14 Toggle Switch[3]

input(1) SW[4] PIN_AF14 Toggle Switch[4]

input(2) SW[5] PIN_AD13 Toggle Switch[5]

input(3) SW[6] PIN_AC13 Toggle Switch[6]

input(4) SW[7] PIN_C13 Toggle Switch[7]

input(5) SW[8] PIN_B13 Toggle Switch[8]

input(6) SW[9] PIN_A13 Toggle Switch[9]

input(7) SW[10] PIN_N1 Toggle Switch[10]

en SW[11] PIN_P1 Toggle Switch[11]

ECADLAB(VHDL) 99




a='0' and b='0' and c='0' output=input(0);








ECADLAB(VHDL)

INPUT OUTPUT

SELECT STROBE W Y

C B A S

X X X 1 1 0

0 0 0 0 A+B+C A`B`C`

0 0 1 0 A`+B+C AB`C`

0 1 0 0 A+B`+C A`BC`

0 1 1 0 A`+B`+C ABC`

1 0 0 0 A+B+C` A`B`C

1 0 1 0 A`+B+C` AB`C

1 1 0 0 A+B`+C` A`BC

1 1 1 0 A`+B`+C` ABC

100


Fig: Simulation Results of 8X1 MULTIPLEXER

RESULTS (HARDWARE):

INPUT OUTPUT

SELECT STROBE

W Y C B A S

X X X 1 1 0

0 0 0 0 A+B+C A`B`C`

0 0 1 0 A`+B+C AB`C`

0 1 0 0 A+B`+C A`BC`

0 1 1 0 A`+B`+C ABC`

1 0 0 0 A+B+C` A`B`C

1 0 1 0 A`+B+C` AB`C

1 1 0 0 A+B`+C` A`BC

1 1 1 0 A`+B`+C` ABC

ECADLAB(VHDL) 101


RESULT:

8X1 MULTIPLEXER internal structure is simulated and verified using Quartus-II


INFERENCE:


and Hardware.


1)Follow Getting Started Procedure for the Software you are using.

2)Don’t forget to instantiate IEEE Libraries at the starting of

the code.

3)Follow Syntax and Semantics of the VHDL code throughout.







1) What is the main feature of IC 74LS151?

Ans: It is an 8x1 Multiplexer having eight inputs and provides two outputs, one is

active high and other one is active low.

ECADLAB(VHDL) 102


2) Give the functional table for Quadruple 2-to-1 line multiplexer.

Ans:

ENABLE SELECT OUTPUT

1 X 0

0 0 Select input A

0 1 Select input B

3) What is principle of operation of a multiplexer?

Ans: Multiplexer is a digital switch which allows digital information from several

sources to be routed onto a single output line.

4) Differentiate between decoder and multiplexer.

Ans: Decoder: n inputs produce 2n possible outputs, 2n output values are from 0

through 2n-1.

Multiplexer: There are 2n input lines and n select lines whose bit combinations

determine which input is selected.

5. Applications of multiplexers?

Ans: The multiplexer include data selection and routing, operation sequencing, parallel to serial conversion, wave form generation and logic function generation.

6. Applications of demultiplexers?

Ans: The demultiplexer include serial to parallel conversion, logic function generation, operation sequencing.



using.


the code.





EXPERIMENT NO.8: 2X4 DEMULTIPLEXER

ECADLAB(VHDL) 103


AIM: To Simulate internal structure of 2X4 DEMULTIPLEXER (IC 74155) using VHDL

and Verify its operation.

APPARATUS:


1. IC 74155 1



THEORY:

The LS155 and LS156 are Dual 1-of-4 Decoder/Demultiplexers with common Address

inputs and separate gated Enable inputs. When enabled, each decoder section accepts

the binary weighted Address inputs (A0, A1) and provides four mutually exclusive active

LOW outputs (O0–O3). If the Enable requirements of each decoder are not met, all

outputs of that decoder are HIGH.

Each decoder section has a 2-input enable gate. The enable gate for Decoder “a”

requires one active HIGH input and one active LOW input (Ea•Ea). In demultiplexing

applications, Decoder “a” can accept either true or complemented data by using the Ea

or Ea inputs respectively. The enable gate for Decoder “b” requires two active LOW

inputs (Eb•Eb). The LS155 or LS156 can be used as a 1-of-8 Decoder/Demultiplexer by

tying Ea to Eb and relabeling the common connection

as (A2). The other Eb and Ea are connected together to form the common enable.The

LS155 and LS156 can be used to generate all four minterms of two variables. These

four minterms are useful in some applications replacing multiple gate functions.

2X4 DEMULTIPLEXER DETAILS:

ECADLAB(VHDL) 104


TRUTH TABLE:

ADDRESS ENABLE a OUTPUT a ENABLE b OUTPUT b

A0 A1 Ea Ea` O0` O1` O2` O3` Eb` Eb` O0` O1` O2` O3`

X X L X H H H H H X H H H H

X X X H H H H H X H H H H H

L L H L L H H H L L L H H H

H L H L H L H H L L H L H H

L H H L H H L H L L H H L H

H H H L H H H L L L H H H L

INTERNAL DIAGRAM:

OUTPUT EQUATIONS:

ECADLAB(VHDL) 105

VHDL CODE:

library ieee;

use ieee.std_logic_1164.all;

entity DeMUX is

port( X: in std_logic;

sel: in std_logic_vector (1 downto 0);

A: out std_logic;

B: out std_logic;

C: out std_logic;

D: out std_logic);

end DeMUX;

architecture behaviour of DeMUX is

begin

process(sel,X)

begin

case sel is

when "00"=>

A <=X; B <= '0'; C <= '0'; D <= '0';

when "01" =>

B <=X; A <='0'; C <='0'; D <='0';

when "10" =>

C <=X; A <='0'; B <='0'; D <='0';

when others =>

D <=X; A <='0'; B <= '0'; C <='0';

end case;

end process;

end behaviour;


ECADLAB(VHDL) 106



A LEDR[0] PIN_AE23 LED Red[0]

B LEDR[1] PIN_AF23 LED Red[1]

C LEDR[2] PIN_AB21 LED Red[2]

D LEDR[3] PIN_AC22 LED Red[3]

X SW[0] PIN_N25 Toggle Switch[0]


SEL(1) SW[2] PIN_P25 Toggle Switch[2]


ADDRESS ENABLE a OUTPUT a ENABLE b OUTPUT b


X X 0 X 5V 5V 5V 5V 1 X 5V 5V 5V 5V

X X X 1 5V 5V 5V 5V X 1 5V 5V 5V 5V

0 0 1 0 0V 5V 5V 5V 0 0 0V 5V 5V 5V

1 0 1 0 5V 0V 5V 5V 0 0 5V 0V 5V 5V

0 1 1 0 5V 5V 0V 5V 0 0 5V 5V 0V 5V

1 1 1 0 5V 5V 5V 0V 0 0 5V 5V 5V 0V


ECADLAB(VHDL) 107

When SELECT = 00

A =1; B = '0'; C = '0'; D = '0';

When SELECT = 01

B =1; A ='0'; C ='0'; D ='0';

when SELECT =10

C <=1; A = 0; B = 0; D = 0;

When SELECT = 11

D =1; A = 0; B = 0; C = 0;

RESULTS (SOFTWARE):

Fig: Simulation Report of 2X4 DEMULTIPLEXER

ECADLAB(VHDL) 108


RESULTS (HARDWARE):

ADDRESS ENABLE

a

OUTPUT a ENABLE

b

OUTPUT b


X X 0 X ON ON ON ON 1 X ON ON ON ON

X X X 1 ON ON ON ON X 1 ON ON ON ON

0 0 1 0 OFF ON ON ON 0 0 OFF ON ON ON

1 0 1 0 ON OFF ON ON 0 0 ON OFF ON ON

0 1 1 0 ON ON OFF ON 0 0 ON ON OFF ON

1 1 1 0 ON ON ON OFF 0 0 ON ON ON OFF

RESULT:

2X4 DEMULTIPLEXER internal structure is simulated and verified using Quartus-


INFERENCE:


and Hardware.



2) Don’t forget to instantiate IEEE Libraries At the starting of

the code.




ECADLAB(VHDL) 109


Sheets.





1) Explain the concept of Demultiplexer.

Ans: A Demultiplexer is a circuit that receives information on a single line and transmits

this information on one of 2n possible output lines. The selection of specific output line is

controlled by values of n selection lines.

2. Differentiate Decoder and Demultiplexer.

Ans: Decoder: n inputs produce 2n possible outputs, 2n output values are from 0

through 2n-1.

Demultiplexer: A Demultiplexer is a circuit that receives information on a single line and

transmits this information on one of 2n possible output lines.

3. Draw the block diagram for full subtractor using 1:8 Demultiplexer

Ans:

ECADLAB(VHDL) 110



1. Follow Getting Started Procedure for the Software you are

using.


the code.




3) Supply the inputs according to truth table and verify outputs

ECADLAB(VHDL) 111


EXPERIMENT NO.9: RAM (16x4)

AIM: To Simulate Internal structure of 16X4 RAM(IC 74189) using VHDL and


APPARATUS:


1. IC 74189 1



THEORY:

The CY7C189 and CY7C190 are extremely high performance 64-bit static RAM’s

organized as 16 words by 4 bits. Easy memory expansion n is provided by an active low

chip select (CS) input and three- state outputs. The devices are provided with inverting

(CY7C189) and non inverting (CY7C190) outputs. Writing to the device is accomplished

when the chip select (CS) and write enable (WE) inputs are both low. Data on the four

data inputs (D0 through D3) is written into the memory location specified on the address

pins(A0 through A3). The outputs are preconditioned such that the correct data is present

at the data outputs (O0 through O3) when the write cycle is complete. This precondition

operation insures minimum write recovery times by eliminating the “write recovery

glitch.” Reading the device is accomplished by taking chip select (CS) LOW, while write

enable(WE) remains HIGH. Under these conditions, the contents of the memory location

specified on the address pins will appear on the four output pins (O0 through O3) in

inverted (CY7C189) or non-inverted (CY7C190) format. The four output pins remain in

high-impedance state when chip select (CS) is HIGH or write enable (WE) is LOW.

ECADLAB(VHDL) 112


16x4 RAM DETAILS:

TRUTH TABLE:

INPUT OPERATION CONDITION

OF OUTPUT

CS΄ WE΄

L L WRITE HIGH

IMPEDENCE

L H READ COMPLEMENT

OF STORED

DATA

H X INHIBIT HIGH

IMPENDENCE

ECADLAB(VHDL) 113


INTERNAL DIAGRAM:

RAM OUTPUT EQUATIONS:

Write = CS`WE`

READ = CS`WE

INHIBIT = CS WE

ECADLAB(VHDL) 114

VHDL CODE:

library IEEE;


entity ram is

port (

cs: in STD_LOGIC;

we: in STD_LOGIC;

re: in STD_LOGIC;

mr: out STD_LOGIC;

mw: out STD_LOGIC

);

end ram;

architecture ram of ram is

begin

process (cs,we,re)

begin

if (cs='0'and we='1'and re='0')then

mr<='0';

mw<='1';

elsif (cs='0'and we='0'and re='1')then

mr<='1';

mw<='0';

end if;

end process;

end ram;


ECADLAB(VHDL) 115


INPUT OPERATION CONDITION OF

OUTPUT

CS΄ WE΄

0v 0v

Data is written

Into specified

location

Tristate

0v +5v Data is read

from specified

location

COMPLEMENT OF

STORED DATA

+5v X No write or read Tristate

X = don’t care


cs ='0'and we ='1'and re ='0'

memory read ='0'

memory write = '1'

cs ='0'and we='0'and re='1'

memory read ='1'

memory write = '0'

Fig: Compilation Report of RAM (16x4)

RESULTS (HARDWARE):

ECADLAB(VHDL) 116


X = don’t care

RESULTS (SOFTWARE):

ECADLAB(VHDL)

INPUT OPERATION CONDITION

OF OUTPUT

CS΄ WE΄

0v 0v Data is available

In specified

location

Tristate

0v +5v Data is retrieved

from specified

location

Complement Of

stored data is

available

+5v X INHIBIT Tristate

117


RESULT:

16X4 RAM internal structure is simulated and verified using Quartus-IISoftware and

in Hardware Lab Respectively.

INFERENCE:


and Hardware.






1)Apply the voltages to the IC as per the details given in the data sheets.

2)Apply the inputs to the respective pins.

3)First decide which one is MSB and LSB.

4)Take the outputs at appropriate pins.


1) Differentiate between combinational circuit and sequential circuit

Ans: Combinational circuit: In this memory unit is not required. Parallel adder is one

example of combinational circuit.

Sequential circuit: Memory unit is required to store the past history of input variables.

Serial adder is one the example for sequential circuit.

2) Differentiate between Moore and Mealy Machines.

Ans: Moore Machine: its output is a function of present state only Input changes does

not affect the output.

Mealy Machine: its output is a function of present state as well as present output.

Input changes may affect the output.

ECADLAB(VHDL) 118


3) How memory cells are organized in a RAM?

Ans: Memory cell organized in the form of array, in which each cell is capable of

storing one bit information

4) Differentiate between Static and Dynamic RAM.

Ans: Static RAM: Memories that consists of circuits capable of retaining their

state as long as power is applied are known as static memories. These are Random

Access Memories, hence combinely called Static RAM.

Dynamic RAM: Memories that store data as a charge on the capacitor are

called as Dynamic RAM’s.

5) Implement 256x2 Ram using 256x1 RAM?

ECADLAB(VHDL) 119


Ans:

6) Implement 32x4 RAM using 16x4 RAM?

ECADLAB(VHDL) 120


Ans:

7) Implement 256x2 Ram using 256x1 RAM?

Ans:

ECADLAB(VHDL) 121









ECADLAB(VHDL) 122

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