cad lab experiment

8/13/2019 Cad Lab Experiment

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EXPERIMENT NO. 1. A

AIM: To study transient and dc analysis of NMOS Inverter.

APPARATUS: Tanner software, PC and power supply.

THEORY:

An inverter circuit outputs a voltage representing the opposite logiclevel to its input.

Inverters can !e constructed using a single NMOS transistor or a single PMOS transistor

coupled with a resistor. Since this "resistivedrain# approach uses only a single type of

transistor, it can !e fa!ricated at low cost. There are two types of electrical co$ponents,

na$ely active and passive co$ponents. Passive components can#t introduce net energy into the

circuit. They also can#t rely on a source of power, e%cept for what is availa!le fro$ the &AC'

circuit they are connected to. As a conse(uence they can#t a$plify &increase the power of a

signal', although they $ay increase a voltage or current &such as is done !y a transfor$er or

resonant circuit'. Passive co$ponents include twoter$inal co$ponents such as resistors,

capacitors, inductors, and transfor$ers A purely passive load is when either a capacitor or

ideal inductor is connected to the load. In this case the current which flows through the

generator)load circuit is *+ degrees out of phase and there is no heat generated nor power

transferred to the load ele$ents. An NMOS inverter using passive load uses a resistor as a

load. A resistor is a passive co$ponent and hence the passive load.


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Nmos based inver ckt

Timing waveform

Spice Netlist for Nmos Based Inverter


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* SPICE netlist written by S-Edit Win32 7.00

* Written on Nov 11, 2013 at 1!02!2

* Wave"or# $robin% &o##ands

.$robe

.o$tions $robe"ilena#e'()ile e$1.dat(

+ $robesdb"ile'(C!sersNattyes/to$tannerES$i&e70)ile e$1.sdb(

+ $robeto$#odle'(odle0(

* ain &ir&it! odle0

1 b a 4nd 4nd N5S 6'2 W'22 '$ P'2 S'$ PS'2

2 8dd 8dd b 4nd N5S 6'2 W'22 '$ P'2 S'$ PS'2

.tran9o$ 10n 100n #et:od'bd"

.in&lde (C!sersNattyes/to$tannerE#odels#l2;12?10101010101010@A

v2 vdd 4N aA v>bA

.$ower v2 0 100n

* End o" #ain &ir&it! odle0


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Results

Power Analysis

Transistor Count


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RESULT: The study of transient and dc analysis of NMOS Inverter has !een done.


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EXPERIMENT NO. 1.B

AIM: To study transient analysis ,AC analysis and c analysis off CMOS Inverter using step

input.

APPARATUS: M-TISIM * software, PC and power supply.

THEORY:

CMOS is also so$eti$es referred to as compementa!"#s"mmet!" meta$o%i&e$

semicon&'cto! &or COSMOS'. The words /co$ple$entarysy$$etry/ refer to the fact that the

typical digital design style with CMOS uses co$ple$entary and sy$$etrical pairs of p t ype and

ntype $etal o % ide se$iconductor field effect transistors &MOS01Ts' for logic functions. CMOS

circuits are constructed in such a way that all PMOS transistors $ust have either an input fro$

the voltage source or fro$ another PMOS transistor. Si$ilarly, all NMOS transistors $ust have

either an input fro$ ground or fro$ another NMOS transistor. The co$position of a PMOS

transistor creates low resistance !etween its source and drain contacts when a low gate voltage is

applied and high resistance when a high gate voltage is applied.

B 2hen a low voltage &+ 3' is applied at the input, the top transitor &Ptype' is conducting

&switch closed' while the !otto$ transitor !ehaves li4e an open circuit.

B Therefore, the supply voltage &5 3' appears at the output.

B Conversely, when a high voltage &5 3' is applied at the input, the !otto$ transitor &N

type' is conducting &switch closed' while the top transitor !ehaves li4e an open circuit.

B 6ence, the ouput voltage is low &+ 3'.

B The function of this gate can !e su$$ari7ed !y the following ta!le8

Input Output

6igh ow

ow 6igh

B The output is the opposite of the input this gate inverts the input.
http://en.wikipedia.org/wiki/P-type_semiconductorhttp://en.wikipedia.org/wiki/N-type_semiconductorhttp://en.wikipedia.org/wiki/Electrical_resistancehttp://en.wikipedia.org/wiki/Gatehttp://en.wikipedia.org/wiki/N-type_semiconductorhttp://en.wikipedia.org/wiki/N-type_semiconductorhttp://en.wikipedia.org/wiki/Electrical_resistancehttp://en.wikipedia.org/wiki/Gatehttp://en.wikipedia.org/wiki/P-type_semiconductor


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B Notice that always one of the transistor will !e an open circuit and no current flows

fro$ the supply voltage to ground.

(IR(UIT )IA*RAM:

C#os Inverter

i#in% Wave"or#


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eslt nalysis

ransistor Cont

S$i&e Netlist

* SPICE netlist written by S-Edit Win32 7.00

* Written on Nov 11, 2013 at 1!1D!22

* Wave"or# $robin% &o##ands

.$robe

.o$tions $robe"ilena#e'()ile0.dat(

+ $robesdb"ile'(C!sersNattyes/to$tannerES$i&e70)ile0.sdb(

+ $robeto$#odle'(odle0(

* ain &ir&it! odle0

1 = 4nd 4nd N5S 6'2 W'22 '$ P'2 S'$ PS'2


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2 = 8dd 8dd P5S 6'2 W'22 '$ P'2 S'$ PS'2

.tran9o$ 10n 100n #et:od'bd"

.in&lde (C!sersNattyes/to$tannerE#odels#l2;12?101010101010@A

v2 vdd 4N aA v>bA

.$ower v2 0 100n

* End o" #ain &ir&it! odle0

Power nalysis


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10

EXPERIMENT NO. +

1sti$ation of 9esistance, Capacitance and Inductance

(apacitance Estimation

In a typical 3SI chip, the parasitic interconnect capacitances are a$ong the $ostdifficult para$eters to esti$ate accurately. 1ach interconnection line &wire' is a three

di$ensional structure in $etal and)or polysilicon, with significant variations of shape,

thic4ness, and vertical distance fro$ the ground plane &su!strate'. Also, each interconnect line

is typicallysurrounded !y a nu$!er of other lines, either on the sa$e level or on different levels. 0igure

:.;; shows a possi!le, realistic situation where interconnections on three different levels run in

close pro%i$ity of each other. The accurate esti$ation of the parasitic capacitances of thesewires with respect to the ground plane, as well as with respect to each other, is o!viously a

co$plicated tas4.

,i-'!e 11: 1%a$ple of si% interconnect lines running on three different levels.

-nfortunately for the 3SI designers, $ost of the conventional co$puteraided 3SI design tools

have a relatively li$ited capa!ility of interconnect parasitic esti$ation. This is true even for the

design tools regularly used for su!$icron 3SI design, where interconnect parasitics were shownto !e very do$inant. The designer should therefore !e aware of the physical pro!le$ and try to

incorporate this 4nowledge early in the design phase, when the initial floorplanning of the chip is

done.

0irst, consider the section of a single interconnect which is shown in 0ig;


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,i-'!e1+: Interconnect seg$ent running parallel to the surface, used for parasitic

capacitance esti$ations.

,i-'!e 1: Influence of fringing electric fields upon the parasitic wire capacitance.

0igure ;: shows the variation of the fringingfield factor 00 > Ctotal)Cpp, as a function of

&t)h', &w)h' and &w)l'. It can !e seen that the influence of fringing fields increases with thedecreasing &w)h' ratio, and that the fringingfield capacitance can !e as $uch as ;+


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,i-'!e#1/: 3ariation of the fringingfield factor with the interconnect geo$etry.

A set of si$ple for$ulas developed !y ?uan and Tric4 in the early ;*@+s can !e used toesti$ate the capacitance of the interconnect structures in which fringing fields co$plicate theparasitic capacitance calculation. The following two cases are considered for two differentranges of line width &w'.

&:.;'


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&:.


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,i-'!e#1: Capacitance of coupled interconnects, as a function of &w)h' and &t)h'.

0igure ;F shows the crosssection view of a dou!le$etal CMOS structure, where the individualparasitic capacitances !etween the layers are also indicated. The crosssection does not show aMOS01T, !ut Gust a portion of a diffusion region over which so$e $etal lines $ay pass. Theinterlayer capacitances !etween the $etal< and $etal;, $etal; and polysilicon, and $etal&A>>K'R AgtK>&AK'R endend$odule

$odule co$p &%,y,7,a,!'R

inputa,!R output

%,y,7R reg %Rreg yR

reg 7R

always &aor!'

!egin *E'1Fb0Gy1Fb0GHE'1Fb0Gif &a>>!'

*E'b1 Gelse if &a!'

yE'1Fb1Gelse if &a!'

HE'1Fb1G

end

end$odule

9esult8


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EXPERIMENT No. /

Analytical Modeling and si$ulation +of I3 characteristics of ap channel)n channel MOS01T

Ai$8To study the I8 C:annel C:ara&teristi&s o" P&:annel9N &:annel os"et

$$arats eired! i&rowind, PC, Power S$$ly.

:eory!

5S)E! layot, &ross-se&tion, sy#b ols

Jey ele#ents!

K inversion layer nder %ate >de$ endin% on %ate volta%eA

K :eavily-do$ ed re%ions rea&: nderneat: %ate in-version layer ele&tri&ally &onne&ts sor&e

and drain

K -ter#inal devi&e! bod y volta%e i#$ ortant

Cir&it sy#b ols

wo &o#$le#entary devi&es!

K n-&:annel devi&e >n-5S)EA on $-Si sbstrate


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>ses ele&tron inversion layerA

K $-&:annel devi&e >$-5S)EA on n-Si sbstrate

>ses :ole inversion layerA

I-8 &:ara&teristi&s

4eo#etry o" $roble#!


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I8 C:ara&teristi&s

I8 2

9esult8


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EXPERIMENT No. 0

odelin% and Si#lation o" N5S M C5S &ir&its sin% S$i&e

i#! o odel and si#late N5S M C5S &ir&its sin% S$i&e.

$$arats reired! S$i&e si#lation So"tware, PC, Power s$$ly.

:eory.

:e N5S M C5S &ir&its are #odelled and si#lated sin% t:e s$i&e si#lation so"tware tool.

8arios $ara#eters :as been analyHed as a reslt o" si#lation.

S&:e#ati& ia%ra#!


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nalysis


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Net ist

! SPIC" netlist written by S#"dit $in%& '())

! $ritten on Nov *&+ &)*% at *,-&%-%%

! $aveform probing commands

(probe

(options probefilename./0ilee1pnan(dat/

2 probesdbfile./C-34sers3Natty35esktop3tanner"5A3TSpice')30ilee1pnan(sdb/

2 probetopmodule./6odule)/

! 6ain circuit- 6odule)

6* N' B 7nd N8 N69S .&u $.&&u A5.::p P5.&,u AS.::p PS.&,u

6& 9ut A N' N& N69S .&u $.&&u A5.::p P5.&,u AS.::p PS.&,u

6% 9ut A ;dd N< P69S .&u $.&&u A5.::p P5.&,u AS.::p PS.&,u

6, 9ut B ;dd N, P69S .&u $.&&u A5.::p P5.&,u AS.::p PS.&,u

(tran=op *)n *))n met>od.bdf

(include /C-34sers3Natty35esktop3tanner"5A3models3ml&?*&


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eslt


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1QP19IM1NT NO E

Modeling and analysis of MOS capacitor S$all signal Analysis

Ai$8 To Model and analy7e the s$all signal analysis of MOS Capacitor.

Apparatus 9e(uired8 Microwind, Power Supply, PC

Sc4ematic )ia-!am:


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ayout of the circuit

Analysis of Capacitance


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3erilog Code for capacitance o!tained8

$odule c$osNand

cad lab experiment

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