Fiber Channel Video ControlleruArchitecture Review

Tsachy Kapchitz & Michael Grinkrug

Super.: Alex Gurevich

Technion Digital Lab, Elbit Systems

Project Goals

• Design a controller that receives FC traffic from an external receiver and passes to memory only video data directed to it.

• The controller should be with minimal latency.

Block Diagram

• Input:– HP Receiver

• Output:– SRAM

• Interface:– Config. Params

(address, video params etc.)

– Status Register

f/2

f

S I Tabley ns ft oe rm m a t i o n

SRAM

Dat

a [3

1:0]

Addr [XX:0]

Con

tain

er_D

ata

[31:

0]D

ata

[31:

0]

CO

M_W

RX

[7:0

]

RX

[15:

8]

RC

LK

CO

M_D

ET

BC

Val

id_C

ont_

Dat

a_R

eady

F ram e_S ta tus_R eg is te r

C on ta ine r_S ta tus_R eg is te r

M EM O RYUNIT

CO NTAIN ERCO NTR O LLER

FR AM ECO NTR O LLER

IN PU TU N IT

New

_Con

tain

er

WE

f/2 C lock

BE

set_next_addr

set_new_object

Status Interface

2f

f/2

Index[15:0]

G et_Index

Ancillary_Inside

Block

Resolution

New

Input Unit

• Functionality:– Get data [words], comma

and clock from HP receiver

– Combine the data into DW and pass to Frame Controller

– Generate clock of half the frequency of the clock provided by HP receiver

– Pass COM_DET signal with the relevant DW

• Input: (from HP receiver)– Data [15:0]

– COM_DET signal

– Clock (RBC)

• Output: (to Frame Controller)– Data [31:0]

– Comma signal

– Clock (half the frequency of RBC)

Input Unit - uArch

D1 D0 C om m a_Extender

com m a

Rx [15:0]

LD1 LD0

To Fram e C ontro lle r D ata [31:0 ] , C om m a

From H P R ece iver D ata [15:0 ] , C om m a

Com m a_Extender

0

1

LD0 = 1LD1 = 0

com m a#LD0 = 0LD1 = 1

commaLD0 = 1LD1 = 0

Input Unit - clock generation

R B C 0 (c lockfrom H P

R ece ive r)

G ene ra tedc lock fo r the

in te rna l b locks

'1 '

Reset

G enerated C lock

RBC0

• This clock (f/2) will be the operating clock of the controller (Frame / container controllers)

• Memory Unit (address placement and SRAM interface) will work @ 2f

Input Unit - Assumptions

• HP Receiver operates in 2-Bytes per clock mode (not Ping-Pong)

• FC frames are DW aligned, so comma always will be passed in parallel with SOF / EOF

• The data from HP is in 8 bits per Byte format (after 10 to 8 conversion)

Frame Controller

• Functionality:– Receive data from Input

Unit by DW

– Analyze the data on FC Header level

– Pass the relevant payload to Container Controller

– Generate FC frame status

• Input: (from Input Unit)– Data [31:0]

– Clock (half of RBC)

– Comma signal

• Output: (to Container Controller)– Data [31:0]

– Valid + BC

– New_Container

– Frame Status Register

Frame Controller - functionalityS O F = S O Fn4

D_ID M atch

R _C T L[7 :4 ] = V ideo

Yes

Yes

TYP E = V en.U n ique

Yes

Sequence Analyse

S E Q _ID = P rev_S E Q _ ID

S E Q _C N T = 0

SEQ_CNT =Prev_SEQ_CNT+1

Yes

No

N ew _C on t_S igna lP rev_S E Q _ ID := S E Q _ ID

Yes

Transfer PayloadTo C ontainer C ontro ller

Prev_SEQ _C N T := SEQ _C N T

Yes

Yes

Dis

ca

rd

No

No

No

No

No

No

Yes

Frame Controller - Block Diagram

• Frame header Analyzer - main FSM, that parses FC frame header fields

• Sequence Follower - figures the next expected sequence num. and sequence count

• CRC is only compared and OK/NOK bit set in status register

• Suspender - FIFO of depth 2 that suspends the data in order to get the end of the frame (CRC)

Fram e HeaderAnalyzer

FSM

S equence Fo llowerFS M

C R C com para tor

D ata[31 :0 ]

S ta tusR egiste r

Fram e Contro ller

com m a

New_container

Valid_4Cont

BC

com m a

S uspender

Byte_filling#

CR

C R

egis

ter

C R C _bus

D ata[31 :0 ]

ExpectedSEQ_ID

SEQ_CNT

New_container

Valid_4Cont

CRC_OK

CRC_chk

Frame Controller - uArchFrame Header Analyzer

W ait_For_SOF

Check_SOF_EOF

SOF_det#, com m a#init_fram e_chk

com m a

Check_R_CTL_

DID

dum m y

Check_Type

Check_SEQ

W ait_For_

Payload2

W ait_For_EOF

com m a

SOF_det,com m a#

com m a#

R_CTL,DID,

com m a#

Type#, com m a#init_fram e_chk

com m a

Type,com m a#

SEQ#, com m a#init_fram e_chk

com m a

SEQ,com m a#

com m a#valid_4Cont=1 if bad_sequence#

com m achk_fram eCRC_chk

com m a#

com m a

com m a

com m a#valid_4Cont=1 ifbad_sequence#

com m a

W ait_For_

Payload1

com m a#

com m a

(R_CTL or DID)#,com m a#

Frame Controller - uArchSequence Follower

• New_container is a pulse that accompanies the first DW of container header

W ait_ fo r_new _con ta ine r

new_cnt!=0Seq_Det=0bad_sequence=1

ge tting_con ta ine r new_container_start

(new_cnt==cnt+1 ornew_cnt==0),this_seq==seqcnt=new_cntseq_det=1

new_cnt==0fetch(seq)

cnt=0seq_det=1

pre_new_container=1

(new_cnt!=0),(new_cnt!=cnt+1)seq_det=0

(new_cnt==0),(this_seq!=seq)fetch(seq)

cnt=0seq_det=1

(new_cnt==0),(this_seq!=seq)fetch(seq)

cnt=0seq_det=1

(new_cnt==cnt+1),(this_seq==seq)cnt=new_cntseq_det=1

pre_new_container new_container

Frame Controller - uArchSuspender

• BC :– 11 - DW

– 10 - 3 Bytes

– 01 - 2 Bytes

– 00 - 1 Byte

– @comma - #byte_fill

valid_4Cont new_containerDATA [31:0]

BC

'11' byte_fill#

com m a

To CRC Com parator

0 1

Frame Controller - Assumptions

• Sequence on FC level 1 video container

• Single sequence at a time (one video stream)

• The link is FIFO (no surpassing frames)

• Point to point connection (single sender)

• If an error on FC frame level occurs - current sequence will be discarded (thus current video frame will be partially lost)

• Upon CRC error only, the data will be passed through and an appropriate status will be generated

Container Controller

• Functionality:– Get container from

Frame Controller and write video objects to memory using an appropriate method, according to video system (with help of Memory Unit)

– Write ancillary object to a separate memory

• Input: (from Frame Controller)– Data [31:0]

– BC

– Valid

– New_Container

– Memory Unit interface

• Output: (to Memory Unit)– SRAM interface

– Memory Unit interface

Container Header

Container Controller -

Block Diagram

H eaderA na lyzer

O b jectsIn fo rm ation

O bjectsE xtracto r

A ligner

oe_oi_ctrl

data

[31

:0]

valid

bc

new

_con

tain

er

s ize_offset [63:0]

data

[31

:0]

valid

bc

new

_con

tain

er

data

[31

:0]

valid

be1

new

_o

bj

data

[31

:0]

we

be

get_index

ancillary_inside

index[15:0]

oi_oe_data[31:0]

block

set_next_addr

be2

C onta inerC ontro ller

set_new_object

Me

mo

ry U

nit

SRAM

new_container

resolution

extr

act

load_size_offset

init

W ait fo rnew

con ta ine r

S k ip toob jec t

0

C heckanc illa ry

ob jec ts ize

Loadanc illa ry

ob jec ts ize_o ffse t

S k ip toob jec t 2

C heckob jec t 2

s ize

Loadob jec t 2

s ize_o ffse t

S k ip toob jec t 3

C heckob jec t 3

s ize

Loadob jec t 3

s ize_o ffse t

F e tchindex

ifTY P E =10h

new_container

DW _offset = 14

TYPE = 10h

size > 0load_size_offset

size > 0load_size_offset

.extract

new_container#init = 0

DW _offset != 7

DW _offset = 18

DW _offset != 14

DW _offset = 7size > 0

load_size_offset

size = 0

TYPE != 10h

size = 0

F etchindex

ifTY P E =10h

size > 0load_size_offset

TYPE != 10h

size = 0

Container Controller - Header Analyzer

Container Controller -Header Analyzer (cont.)

• Data flows through the block and relevant fields are checked and loaded into Object Information registers

• Objects size is loaded into a “temp” register and transferred together with offset

Data

SIZE

Object Info

Frame Contrl.

Obj. Extractor

Container Controller - Objects Information

rs t

rs t

rs t

in it

size

_off

set

fe tch_ob j_ in fo

load1

load2

load3ld

ld

ld

1

10

0

Mux_1

Mux_2

Mux_3

load_s ize_o ffse t#

load_s ize_o ffse t#

load_s ize_o ffse t#

load_s ize_o ffse tload1

load_s ize_o ffse tload2

anystate

Mux_1

in it#

Container Controller - Object Extractor

O bject Extractor

O bjects In fo

H eader Analyzer

valid

new

bc

offse t2 size2

Data

Control

offse t1 size1

valid

new

BE

splt

Aligner

b lock

O bjectE xtractor

FS M

data

fetc

h_

ob

j_in

fo

Container Controller - Object Extractor FSM

wait_ for_valid_ in fo

wait_ for_object

(cnt>=offset1+1) &(cnt>=offset1+size1+1)&(size2=0)pass

cnt<offset1+1

E xtract_ob ject

(cnt>=offset1+1)&(cnt<offset1+size1+1)pass

(cn t>= o ffse t1+s ize1+1)& (s ize2=0 o r(o ffse t2+1 < cn t-bc )pass

cnt < offset1+size1+1pass

(cnt>=offset1+size1+1)&(cnt-bc<=offset2+1<=cnt)&(size2!=0))pass, split, fetch_bj_info

A nyS ta tewait_ for_valid_ in fo

block

extract# or b lock

(cnt>=offset1+size1+1)&(size2!=0)&(cnt>=offset2+1)passfetch_obj_info

(cnt>=offset1+1)&(cnt>=offset1+size1+1)&(size2!=0)&(cnt>=offset2+1)passsplitfetch_obj_info

(cnt>=offset1+1)&(cnt>=offset1+size1+1)&(size2!=0)&(cnt<_offset2+1)pass

extrac t .fe tch_ob j_ in fo

Container Controller -

Aligner0 1

23

__________aligner_load

new`

new`

new`

Counter

'00'

== resolution

aligner_load

state

inc ld

data[31:0] be splitnew

new '

vld sp

data[31:0] be[3:0]we

set_next_addr

set_new_obj

Mem

ory

Un

it

Object Extractor

SRAM

Aligner

ld ld ld

Container Controller -

Memory UnitV ideoSystem

Infrom ation

index

Ancilla ryIn form ationget_ index

ld

1

0

M em -U nitFSM

Addressing

se t_next_add r

ancillary_ ins ide

ob j_ended

write_ancillary

-interlaced / non-interlaced-num of pixels per line-num of lines per video fram e-resolution-bad system

bad_sys tem

reso lution

external_ in fo

external_ contro l

ExternalEnvironment

new

se t_new _ob j

address

b lock

SRAM

Head

er A

na

lyzer

Alig

ner

Ob

ject E

xtra

cto

r

Container Controller - Memory Unit FSM

IDLE

CHECK

W RITEOBJ_1

W RITEOBJ_2

W RITEANCILLARY

getindex#block

getindexancillary_ ins ide# &bad_system

ancillary_ ins ide# &bad_system #

ancillary_ ins ide

set_new_obj#write_ancillary

set_new_obj &bad_system #

set_new_obj &bad_system

obj_ended# &start_new_obj#

obj_ended |s tart_new_obj

obj_ended#

obj_ended

anystate

IDLE

new

Container Controller - Assumptions

• Memory Unit gets Index of the first valid (TYPE & Size) object

• @ interlaced mode - video field object• Single video stream