fee2006 perugia [email protected] politecnico di milano & infn a cmos circuit for silicon...

FEE2006 Perugia [email protected] di Milano & INFN

A CMOS circuit for Silicon Drift Detectors readoutin exotic atom research

L. Bombelli, C. Fiorini, T. Frizzi, A. LongoniPolitecnico di Milano and INFN, Milano, Italy

Work supported by Italian INFN and EC (SIDDHARTA project)


What it as ‘exotic’ atom?

pp

e-e-KK--

KK--

pp

n=25n=25

n=2n=2

n=1n=1

2p->1s (K2p->1s (K))

X ray of interestX ray of interest

n=1n=1

Hydrogen atomHydrogen atom Kaonic HydrogenKaonic Hydrogen

.m.es1p2

measureds1p2 EE


Main measurement issues:- peak stability (< 1‰)- E resolution (< 150eV FWHM)- background suppression by triggering with Kaon monitor

Shift ε = ≈ 300eV

Width Г= ≈ 450eV

(DEAR experiment)


Frascati-LNF-INFN DAFNE collider

The Siddharta collaboration:LNF-INFN Frascati, ItalyMPI, PNSensor Munich, GermanyPolitecnico–INFN Milano, ItalyIMEP Wien, AustriaIFIN-HH Bucarest, Romania...


3 SDD (1cm2 each) with on-chip JFET and feedback cap

detector+readout module

SDD board

readout board


Shaper

BaselineHolder

Pole-zero

CHANNEL 1

CHANNEL 2

CHANNEL 8

SHIFT REGISTERthreshold and kill channel programming

MUX8:1

FIFO

Preamp

AnalogDifferential

Output Buffer

Positive out

Negative out

LT 1Data in

CK_D

Gain setting Peaking time setting

SDD Array

8 channel ASIC

Drain control

ChannelLogic

rese

t

Peak

detect.

LT1

AddressEncoder

8

clock

ACK

LT 2

LT 8 LTReal time

trigger

Peak Stretcher

OtherLogic HT

Out of rangeInformation

Chip architecture


• 8 analog channels

• Charge amplifier

• Shaper (3us, 1.5us, 750ns, 680ns)

• Fast Shaper & PileUp Rejector

• BLH

• Peak Stretcher

• LT and HT triggers

• Digital section

• Address

• LT (real time)

• Differential Analog MUX

• Acknowledge input

Features

33mm2, AMS 0.35m


channel e-

h+

driftingelectronsmultiplication region

channel (n)

deep guard (p) bulk (n)

back electrode (p+)symmetryaxis

gate (p+)source (n+)

guard (p+)

anode (n+)drain (n+)

h+

-AI0

Isignal

CF

Rg

Preout

C1R1

A1

Cgd

Detector chip

high-freq.loop

low-freq.loop

“Drain feedback” Charge Preamplifier configuration

Rg: dynamic resistance

of the ‘weak’ avalanchereset mechanism


Preamplifier response well approximated by a single pole:

1

111

g

in

0

A

CRsK1

1

A

R

I

V

-AI0

Isignal

CF

Rg

Preout

C1R1

A1

Cgd

high-freq.loop

low-freq.loop

• decay independent from Rg, therefore from leakage+signal current

• Pole/Zero compensation possible by means of A1 (exploited in the chip)

K = Cf

Cgd

decay = K A1

R1C1


The CMOS implementation

-AI0

Shaper

Isignal

CF

Rg

Preout

C1

Detectorchip

Gm

RA

R1

RZ

CZ

gain adjustabletransconductanceamplifier

Ibuf

CMOS chip

Cgd

15 V compatible devices in the 3.3V-0.35m

voltage gain A1 = GmR1

= K C1 R1

GmR1K = Cf

Cgd

adjustment of the decay time


The main amplifier

voltage gain = gmJFET·RA > 5000 RA ~ 10M

1:

1:

ICON

IR IR/

R

Iout=IR/A

IR

VOUTRA = R·

ICONI in

I0

VOUT = Iin·R·

RA = R·

low-noisecurrent de-multiplier

R.L. Chase, et al., NIM A409,1998 C. Fiorini, M. Porro, IEEE TNS, 2004

-AI0

Isignal

CFPreout

RAIbuf

gmVin


The adjustable pole-zero network

RZCZ = preamplifier

fixed adjustable

-AI0

Isignal

CFPreout

RAIbuf

ShaperRZ

CZ

R

Iout=IR/VOUT/R

A

IR

VOUT

I in

I0

CZ

which is already available in the transimpedance stage and need just tobe duplicated and sentto the shaper

the role of RZ is to providea current

not preciselyknown a priori

IS=VOUT/RZ

IS


Implemented baseline holder (BLH)

-AI0

Shaper

Isignal

CF

Rg

Preout

C1

Gm

RA

R1

RZ

CZIbuf

Vdrain

Ireset

• The JFET Drain voltage drifts due to changes of the reset current

• Drain, preamplifier output, shaper output are all DC coupled

• Required Drain DC shifts are provided by the BLH whose extended action back to the preamplifier stabilize also this last one

• Low-pass filter guarantees unchanged signal processing

Vbaseline

CB

RB


preamplifierRz

Cz

C

Req

6th order unipolar shaping

The shaping amplifier

shaper

preamplifier

4 selectable peaking times(0.6-0.75-1.5-3s)


Experimental results

SDD detectors

Siddharta CHIP

Analog output

Digital output

8 channel input

Preout

Cstray

Cload = Cstray (~10pF)

Cload = Cstray +33pF


external continuous control of the decay time of the preamplifier…

1.8V

… and of the pole-zero adjustment of the shaper waveform


Temperature: -20°C

5mm2 SDD

Spectroscopy measurements


Integral non- linearity error at the Multiplexer output within ±0.1% in the 2-20keV range

Linearity


Multiplexer logic


OUT SHAPER

BUFFER OUT +

BUFFER OUT -

LT

ACK

HT


0

0

0

0

0

1

1° event amplitude (on channel 0)

2° event (on Channel 4)


0

0

0

0

0

1

1

1° event amplitude (on channel 0)

2° event (on Channel 4)

amplitude out ofrange:- amplitude discarded- event occurrence and address both recorded


two photons detected by 2° fast shaper

this events are directly rejected inside the chip

Pile-up rejection


20ns

OUT+

LT

ACK

Different events close occurring on different channels

lost events occurring on different channels at a rateof 100kcounts/s/channel:~ 3% (foreseen)

(to be compared with about>5% pile-up rejection on each single channel)


Conclusions

• A 8 channels prototype of CMOS readout chip for the Siddharta experiment with pre-shaper, fast MUX readout, channel address and timing signals has been developed and tested

• Functionalities and noise performances are satisfactory

• Deeper tests are on the way at LNL-INFN and installation in the experiment is foreseen in early 2007

fee2006 perugia [email protected] politecnico di milano & infn a cmos circuit for silicon...

Documents

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