fabrication and characterization of emerging nanoscale memory · stanford university 9 h.-s. philip...

Stanford University

Department of Electrical Engineering2008.12.11Center for Integrated Systems

Fabrication and Characterization of Emerging Nanoscale Memory

Yuan Zhang, SangBum Kim, Byoungil Lee, Marissa Caldwell(*), and H.-S. Philip WongDepartment of Electrical Engineering (*) Chemistry DepartmentStanford University, Stanford, California, U.S.A.

http://nano.stanford.edu

Stanford University

Department of Electrical Engineering2008.12.11H.-S. Philip Wong2

Non-Volatile Memory Technology Research Initiative (NMTRI) at Stanford University

ITEXAS

NSTRUMENTS

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Memory In Your Hands (~2010)

C. Kim, “Future Memory Technology: Trends and Challenges,” Plenary paper, ISQED (2006).

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Outline

Opportunities for emerging memories

Study of phase change nanodots

NiO Resistance change memory

Beyond the memory cell– Integration of nanowire selective diode with phase

change memory cell

Summary

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Memory Market: DRAM and Flash Dominate

Source: Gary Bronner (Rambus), Stanford EE 309 lecture, Fall 2007.

Ref: iSuppli, 3Q 2006

0

20

40

60

80

2005 2006 2007 2008 2009 2010

Other MemoryOther Non-volatile MemoryNORNANDSRAMDRAM

DRAM

Flash

Bill

ions

of D

olla

rs

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Phase Change Memory

Phase change principal:

Basic Structure:

Switching behavior:

S. Lai, "Current status of the phase change memory and its future," IEDM Tech. Dig., pp. 255 - 258, December 2003.

Operation Principle: Device operates by switching between low resistance SET state and high resistance RESET state.

V+

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Reset Current Reduction

Reducing reset current is one of the most important issues of phase change memory– Reduce contact area (brute force)

– Engineer the device structure to achieve highest heating for a certain current

– Engineer the interface thermal and electrical resistance of the GST / electrode interface

– Engineer the electrical and thermal properties of the phase change material

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Reset Current Reduction NeededTypical high performance transistor drive current ~ 1mA/μmAt 32 nm, for W/L=4, I=128 μA

IRESET = 128 μA

Diameter = 18 nm (S. Lai et al.)

A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, S. Hudgens, and R. Bez, "Scaling analysis of phase-change memory technology," IEDM Tech. Dig., pp. 699 - 702, December 2003.

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Phase Change Nanodot by Self-Assembly

AIST nanodots

PS hole size distribution

0 10 20 30 400

0.05

0.1

0.15

0.2

Sizes of PMMA Holes (nm)

Den

sity

Diameterfitting curve

Mean:~18.5nm

200nm 200nm

• Diblock copolymer PS-PMMA template and lift-off process

Y. Zhang, S. Raoux, D. Krebs, L.E. Krupp, T. Topuria, M. Caldwell, D.J. Milliron, P.M. Rice, J. Jordan-Sweet, H.-S. P. Wong, “Crystallization Characteristics of Phase Change Nanoparticle Arrays Fabricated by Self-Assembly Based Lithography,” Materials Research Society (MRS) Symposium, San Francisco, CA, USA, paper G8.5, March 24 – 28, 2008

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15 – 20 nm Phase Change Nanodots

Y. Zhang, S. Raoux, J. N. Cha, L. E. Krupp, C. T. Rettner, H.-S. P. Wong, “Transition Behavior of High Density Ordered Phase Change Nanostructure from Diblock Copolymer Template”, MRS Spring Meeting, Symposium I, paper I-12.8, April 10-12, San Francisco, 2007.

200nm

Ge2Sb2Te5 GeSb AIST (AgInSbTe)

AIST

GeSb

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XRD Results of GeSb Nanodots

Nanodots start to crystallize at much higher temperature than blanket films.

15nm film 2.5nm film Thin film

Nanodots

(003) (003)

(003)

(012)

nanodots


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XRD Results of GST Nanodots

For thicker film, crystallization transit into fcc phase at 160oC, and hcp phase at 380oC.For thin film, the transition is directly into rhombohedral phase at 350oC.For nanodots, the fcc phase transition does not happen, consistent with very thin GST blanket film.

3.6nm film (004)

(101)

15nm film (004)

(101)(111)

(200)

(101)

nanodots


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Metal Oxide M-I-M Memory

Motivation:– Low programming voltage (< 3V)– Low programming current– Uni-directional programming

• Easier to build cross-point array– Material set compatible with conventional semiconductor

processing (e.g Ni)

Key issues:– Physics of resistive switching– Device scaling properties

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NiO Microstructure

D.C. Kim, M.J. Lee et al., “Improvement of resistive memory switching in NiO using IrO2,” Appl. Phys. Lett., Vol. 88, p. 232106 (2006)

B.I. Lee, H.-S. P. Wong, unpublished.

PtNiOPt

200 nm

Columnar grains

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Fabricated Structure

SiO2

Si

Pt

Pt

NiO

Cross-section

< Schematic of the fabricated structure. NiO thickness = 20nm >

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Beyond The Memory Cell

Cell selection device for cross-

point memory

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Cross-Point Memory Cell Selection DeviceRequirements:

Stackable, low temperature processingEnough current drive for programmingUnidirectional and (ideally, bi-directional) programming

WLm

WLm-1

WLm+1

BLn-1 BLn+1BLn

V

V/2

V/2

V/2 V/20

Selected cell

Half-Selected cell

Leakage current

WLm

WLm-1

WLm+1

BLn-1 BLn+1BLn

V

0

0

V V0

Selected cell

With DiodeWithout Diode

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Oxide Diode For 3D Stacking of Crosspoints

Silicon or Oxide Diode

- Uses NiO as p-type, TiO2 as n-type semiconductor with φ50um .(~102A/cm2)

- Process temperature < 300℃.

- Current density needs to be increased by a few orders for reasonably small OxRRAM cells.

-5 -4 -3 -2 -1 0 1 2 3 4 510-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

Cur

rent

(A)

Voltage (V)-2 -1 0 1 210-11

10-10

10-910-810-710-610-510-410-310-210-1

On stateOff state

Cur

rent

(A)

Voltage (V)-5 -4 -3 -2 -1 0 1 2 3 4 5

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

On state Off state

Curr

ent (

A)

Voltage (V)

Oxide diode propertySwitching combined with oxide diodeBinary oxide switching

TE

P-type oxide

N-type oxide

BE

Binary Oxide

TE

P-type oxide

N-type oxide

BE

Binary Oxide

Source: S. Seo (2006)

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SL

m-1

SL

m+1SL

WL

n-1

WL

n+1

Diode plus memory element

Wordline(W/L)

WL

n

WL

n

WL

n

WL

n

WL

n

WL

n

WL

n

WL

n

WL

n

Bitline (B/L)

Nanowire diode

Memory element

Top electrode

Bottom electrode

Y. Zhang, S. Kim, J.P. McVittie, H. Jagannathan, J.B. Ratchford, C.E.D. Chidsey, Y. Nishi, and H.-S. P. Wong, “An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory,” Symp. VLSI Technology, pp. 98 – 99, June 12 – 14, 2007, Kyoto, Japan.

Cross-Point Memory Array with Selective NanowireDiode

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Nanowire Bottom ElectrodeSmall diameter electrode, reduces programming currentRoute to pn-junction diode selection deviceLow-temperature (<350C) nanowire synthesis


P-type Si (111)

SiO200nm SiO2 SiO2

25nm GST

100nm TiN40nm N-type Ge nanowire

Ge nanowires

Si Substrate

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Nanowire Diode + Phase Change Memory

-5 0 50

100200300400500

Vforward (V)

I forw

ard (u

A) 10µm

5µm2µm1µm500nm


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Repetitive Pulse SET/RESET Programming

2µm × 2µm pad sizePulse conditions– RESET : 8.5V 5ns/1µs/5ns– SET : 5.5V 100ns/20µs/100ns* type : amplitude(V) rising time /pulse width / falling time

• Programming Current – RESET : 173µA– SET : 45.5µA

0 10 20 30 40 50 60 70 80

1M

10M

100M

R (Ω

)

Times

Resistance @ VREAD=3V

0 20 40 60 800.0

5.0x10-5

1.0x10-4

1.5x10-4

2.0x10-4

Cur

rent

(A)

Times

Programming Current


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ConclusionsNew materials enable new memory devices– Plenty of new materials, difficult to satisfy memory requirements

Scalability is a key issue– Material property, stackable, small cell size, multi-bit/cell

Nanofabrication techniques has been applied to study nano-scale memory device characteristics– Nanocrystal synthesis and diblock copolymer method for sub-

20nm phase change nanodots

– Ebeam lithography for sub-100nm NiO memory arrays

– Nanowire diode as selection device for PCM cell

Future applications will be enabled by new memory technologies

fabrication and characterization of emerging nanoscale memory · stanford university 9 h.-s. philip...

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