ex no.1 simulation and implementation of half …

1

DEPARTMENT SUBJECT COLLEGE

ECE VLSI DESIGN LAB MSEC, Chennai-24

Ex No.1 SIMULATION AND IMPLEMENTATION OF

HALF ADDER CIRCUIT

AIM:

To write a verilog code to simulate a half adder and implement it on Field Programmable

Gate Array (FPGA) kit.

APPARATUS REQUIRED:

PC with P4 processor, Xilinx ISE9.1i Simulator and FPGA Kit

THEORY:

An Adder is a device which takes two operands and performs arithmetic addition on it.

Adders can be implemented by using both Combinational Logic Circuits and Sequential Logic

Circuits.

Half adder:

A Combinational adder is the one which performs addition using logic gates without any

memory elements. A logic circuit used for the addition of two 1-bit numbers is referred to as a

half adder. It takes A and B as input and produces sum and carry as outputs.

The logical equations for carry and sum can be written as

Sum= A xor B

Carry= A and B

RTL SCHEMATIC:

PROGRAM:

HALF ADDER:

module ha(a, b, sum, carry); input a; input b; output sum; output carry; reg sum,carry; always@(a,b)

www.vidyarthiplus.com

2



LOGICAL DIAGRAM:

TRUTH TABLE:

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1


3



begin sum=a^b; carry=a&b; end endmodule TESTBENCH FOR HALF ADDER:

module tha(); reg a,b; wire sum,carry; ha i1(a,b,sum,carry); initial begin a=0;b=0; #10 a=0;b=1; #10 a=1;b=0; #10 a=1;b=1; end initial $monitor($time,"a=%b\t,b=%b\t,sum=%b\t,carry=%b\t",a,b,sum,carry); initial #50 $finish; endmodule TRANSCRIPTED VIEW:

0 a=0 ,b=0 ,sum=0 ,carry=0 # 10a=0 ,b=1 ,sum=1 ,carry=0 # 20a=1 ,b=0 ,sum=1 ,carry=0 # 30a=1 ,b=1 ,sum=0 ,carry=1

USER CONSTRAINT FILE:

NET "a" LOC = "p74" ; NET "b" LOC = "p76" ; NET "carry" LOC = "p100" ; NET "sum" LOC = "p102" ;

WAVEFORM:


4



PROCEDURE:

• Open the software Xilinx ISE.

• File New Project � New project wizard appears. � Type project name and location. Enter next. � In the next window, set the device properties (or leave of with default). � Create new source window, press next. � Add existing source, press next. � Click finish.

• A new project is created.

• In the source window, right click on project name and press create new source � In the new source wizard – select verilog module and type file name. Press next. � Enter input, output ports and set their directions accordingly in the define module

window. � Enter finish.

• Filename.v window appears. Type in the program and save it. This program is called as design block.

Creating a test bench for simulation

• Right click on the project and select new source.

• In the new source wizard – select verilog module and type the file name (filename should not be same as the project name). Press next. This stimulus block is also commonly called a test bench.

• Stimulus block/ test bench has no input and output ports.

• Declare all inputs in design block as registers in stimulus block.

• Declare all outputs in design block as wires in stimulus block.

• Call the respective program as an instance.

• Specify the various combinations of inputs and specify the time interval between each combination inside the initial block.

• For the transcript view specify all the input and output variables along with their data type representation using $ monitor system task.

• Save the file.

• The stimulus block becomes the top level block.

• Go to process window and check for syntax errors by clicking on “check syntax”.

• In the source window select “Behavioral simulation”.

• In the process window click on Model simulator.

• Simulation window appears showing the wave form of the outputs for the specified combination of the inputs.

DOWNLOADING PROCEDURE:

• Select sources for Synthesis/Implementation

• Select the created module(*.v file) in the source window.

• Select user constraint in the process window, double click edit constraint to create user constraint file(UCF).

• Type the net list to define the I/O pins & save it.


5



• Double click implement design in the process window.

• Double click Generate programming file & select the respective created bit file (*.bit)

• Double click configure device (iMPACT). In the impact window, Select configure device using boundary scan. Click finish

• Right click on the created xilinx model & select the program, give OK on the displayed window.

• The bit file is downloaded into the FPGA if the message “PROGRAM SUCCEEDED” is displayed

• Change the status of the switches and verify the status of the LEDs.

RESULT

The simulation and implementation of half adder circuits is performed using Xilinx 9.1i and FPGA kit.


6




FULL ADDER CIRCUIT

AIM:

To write a verilog code to simulate a half adder and implement it on Field Programmable

Gate Array(FPGA) kit.

APPARATUS REQUIRED:


THEORY:

A Full Adder is a combinational circuit which takes two 1-bit numbers and also any input carry (if it comes from previous bit addition) as input and produces sum and carry as outputs. The logical equations for carry and sum can be written as

Sum= A xor B xor C

Carry= (A and B) or (B and C) or (C and A)

RTL SCHEMATIC:

PROGRAM:

FULL ADDER USING HALF ADDER:

module fa(a, b, c, sum, carry); input a; input b; input c; output sum; output carry; wire s1,c1,c2; ha i1(a,b,s1,c1); ha i2(s1,c,sum,c2);


7



LOGIC DIAGRAM:

TRUTH TABLE:

A B C Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1


8



or g1(carry,c1,c2); endmodule TESTBENCH FOR FULL ADDER:

module tfa(); reg a,b,c; wire sum,carry; fa i1(a,b,c,sum,carry); initial begin a=0;b=0;c=0; #10 a=0;b=0;c=1; #10 a=0;b=1;c=0; #10 a=0;b=1;c=1; #10 a=1;b=0;c=0; #10 a=1;b=0;c=1; #10 a=1;b=1;c=0; #10 a=1;b=1;c=1; end initial $monitor($time,"a=%b\t,b=%b\t,c=%b\t,sum=%b\t,carry=%b\t",a,b,c,sum,carry); initial #80 $finish; endmodule

TRANSCRIPTED VIEW:

# 0a=0 ,b=0 ,c=0 ,sum=0 ,carry=0 # 10a=0 ,b=0 ,c=1 ,sum=1 ,carry=0 # 20a=0 ,b=1 ,c=0 ,sum=1 ,carry=0 # 30a=0 ,b=1 ,c=1 ,sum=0 ,carry=1 # 40a=1 ,b=0 ,c=0 ,sum=1 ,carry=0 # 50a=1 ,b=0 ,c=1 ,sum=0 ,carry=1 # 60a=1 ,b=1 ,c=0 ,sum=0 ,carry=1 # 70a=1 ,b=1 ,c=1 ,sum=1 ,carry=1 USER CONSTRAINT FILE:

NET "a" LOC = "p74" ; NET "b" LOC = "p76" ; NET "c" LOC = "p77" ; NET "carry" LOC = "p100" ; NET "sum" LOC = "p102" ;


9



WAVEFORM:

PROCEDURE:















10





• Save the file.

















RESULT

The simulation and implementation of full adder circuits is performed using Xilinx 9.1i and FPGA kit.


11




MULTIPLEXER CIRCUITS AIM:

To write a verilog code to simulate multiplexers and implement it on Field

Programmable Gate Array (FPGA) kit.

APPARATUS REQUIRED:


THEORY:

In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth. A multiplexer is also called a data selector. RTL SCHEMATIC:

MUX 2X1

MUX 8X1


12



2:1 MUX

LOGICAL DIAGRAM

TRUTH TABLE

4:1 MUX

LOGIC DIAGRAM

TRUTH TABLE

S D0 D1 Y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

S0 S1 D[0] D[1] D[2] D[3] O

0 0 1 X X X 1

0 0 0 X X X 0

0 1 X 1 X X 1

0 1 X 0 X X 0

1 0 X X 1 X 1

1 0 X X 0 X 0

1 1 X X X 1 1

1 1 X X X 0 0


13



PROGRAM:

2:1 MULTIPLEXER:

module mux21(a, s, y); input [1:0] a; input s; output y; reg y; always@(a,s) begin y=0; y=(a[1]&~s)|(a[0]&s); end endmodule TESTBENCH FOR 2:1 MULTIPLEXER:

module tmux21(); reg [1:0] a; reg s; wire y; mux21 i1(a, s, y); initial begin a[1]=0;a[0]=0;s=0; #10 a[1]=1;a[0]=0;s=0; #10 a[1]=0;a[0]=1;s=1; end initial $monitor($time,"a[1]=%b\t,a[0]=%b\t,s=%b\t,y=%b\t,",a[1],a[0],s,y); initial #30 $finish; endmodule TRANSCRIPTED VIEW:

# 0a[1]=0 ,a[0]=0 ,s=0 ,y=0 , # 10a[1]=1 ,a[0]=0 ,s=0 ,y=1 , # 20a[1]=0 ,a[0]=1 ,s=1 ,y=1 , USER CONSTRAINT FILE:

NET " a[1]" LOC = "p74" ; NET " a[0]" LOC = "p76" ; NET " s" LOC = "p77" ; NET " y" LOC = "p100" ;


14



WAVEFORM:

4:1 MULTIPLEXER:

PROGRAM:

USING DATA FLOW MODELING:

module mux4 ( out,i0,i1,i2,i3,s0,s1); input s0,s1; output out; assign out = s1 ? ( s0 ? i3 : i2 ) : ( s0 ? i1 : i0 ) ; endmodule USING BEHAVIORAL MODELING:

module mux4 (out,io,i1,i2,i3,s0,s1); input i0,i1,i2,i3,s0,s1; output out; reg out; always@(s0 or s1 or i0 or i1 or i2 or i3) begin case ({s0,s1}) 2’b00: out=i0; 2’b01: out=i1; 2’b10: out=i2; 2’b11: out=i3; endcase end end module


15



USING GATE LEVEL MODELING:

module mux4 ( out,i0,i1,i2,i3,s0,s1); input i0,i1,i2,i3,s0,s1; output out; wire a,b,c,d,e,f; not(e,s0); not(f,s1); and(a,i0,e,f); and(b,i1,e,s1); and(c,i2,s0,f); and(d,i3,s0,s1); or(out,a,b,c,d); end module TESTBENCH FOR 4:1 MULTIPLEXER:

module tmux41(); reg [3:0] a; reg [1:0] s; wire y; mux41 i1(a, s, y); initial begin a[3]=0;a[2]=0;a[1]=0;a[0]=0;s[1]=0;s[0]=0; #10 a[3]=1;a[2]=0;a[1]=0;a[0]=0;s[1]=0;s[0]=0; #10 a[3]=0;a[2]=1;a[1]=0;a[0]=0;s[1]=0;s[0]=1; #10 a[3]=0;a[2]=0;a[1]=1;a[0]=0;s[1]=1;s[0]=0; #10 a[3]=0;a[2]=0;a[1]=0;a[0]=1;s[1]=1;s[0]=1; end initial $monitor($time,"a[3]=%b\t,a[2]=%b\t,a[1]=%b\t,a[0]=%b\t,s[1]=%b\t,s[0]=%b\t,y=%b\t,",a[3],a[2],a[1],a[0],s[1],s[0],y); initial #50 $finish; endmodule TRANSCRIPTED VIEW:

# 0a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,s[1]=0 ,s[0]=0 ,y=0 # 10a[3]=1 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,s[1]=0 ,s[0]=0 ,y=1 # 20a[3]=0 ,a[2]=1 ,a[1]=0 ,a[0]=0 ,s[1]=0 ,s[0]=1 ,y=1 # 30a[3]=0 ,a[2]=0 ,a[1]=1 ,a[0]=0 ,s[1]=1 ,s[0]=0 ,y=1 # 40a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=1 ,s[1]=1 ,s[0]=1 ,y=1


NET " a[3]" LOC = "p74" ; NET " a[2]" LOC = "p76" ; NET " a[1]" LOC = "p77" ;


16



NET " a[0]" LOC = "p79" ; NET " s[1]” LOC = "p78" ; NET " s[0]” LOC = "p82" ; NET " y” LOC = "p100" ; WAVEFORM:

PROGRAM:

8:1 MULTIPLEXER USING 2:1 MULTIPLEXER:

module mux81(a, s, y); input [7:0] a; input [2:0] s; output y; wire x1,x2,x3,x4,x,x6; mux21 i1(a[0],a[2],s[2],x1); mux21 i2(a[4],a[6],s[2],x2); mux21 i3(a[1],a[3],s[2],x3); mux21 i4(a[5],a[7],s[2],x4); mux21 i5(x1,x2,s[1],x5); mux21 i6(x3,x4,s[1],x6); mux21 i7(x5,x6,s[0],y); endmodule

TESTBENCH FOR 8:1 MULTIPLEXER:

module tmux81(); reg [7:0] a; reg [2:0] s; wire y; mux81 i1(a, s, y);


17



initial begin a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0;s[2]=0;s[1]=0;s[0]=0; #10 a[7]=1;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0;s[2]=0;s[1]=0;s[0]=0; #10 a[7]=0;a[6]=1;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0;s[2]=0;s[1]=0;s[0]=1; #10 a[7]=0;a[6]=0;a[5]=1;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0;s[2]=0;s[1]=1;s[0]=0; #10 a[7]=0;a[6]=0;a[5]=0;a[4]=1;a[3]=0;a[2]=0;a[1]=0;a[0]=0;s[2]=0;s[1]=1;s[0]=1; #10 a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=1;a[2]=0;a[1]=0;a[0]=0;s[2]=1;s[1]=0;s[0]=0; #10 a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=1;a[1]=0;a[0]=0;s[2]=1;s[1]=0;s[0]=1; #10 a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=1;a[0]=0;s[2]=1;s[1]=1;s[0]=0; #10 a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=1;s[2]=1;s[1]=1;s[0]=1; end initial $monitor($time,"a[7]=%b\t,a[6]=%b\t,a[5]=%b\t,a[4]=%b\t,a[3]=%b\t,a[2]=%b\t,a[1]=%b\t, a[0]=%b\t,s[2]=%b\t,s[1]=%b\t,s[0]=%b\t,y=%b\t,",a[7],a[6],a[5],a[4],a[3],a[2],a[1],a[0],s[2], s[1],s[0],y); initial #90 $finish; Endmodule TRANSCRIPTED VIEW:

# 0a[7]=0 ,a[6]=0 ,a[5]=0 ,a[4]=0 ,a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,s[2]=0 ,s[1]=0 ,s[0]=0 ,y=0 # 10a[7]=1 ,a[6]=0 ,a[5]=0 ,a[4]=0 ,a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,s[2]=0 ,s[1]=0 ,s[0]=0 ,y=1 # 20a[7]=0 ,a[6]=1 ,a[5]=0 ,a[4]=0 ,a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,s[2]=0 ,s[1]=0 ,s[0]=1 ,y=1 # 30a[7]=0 ,a[6]=0 ,a[5]=1 ,a[4]=0 ,a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,s[2]=0 ,s[1]=1 ,s[0]=0 ,y=1 # 40a[7]=0 ,a[6]=0 ,a[5]=0 ,a[4]=1 ,a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,s[2]=0 ,s[1]=1 ,s[0]=1 ,y=1 # 50a[7]=0 ,a[6]=0 ,a[5]=0 ,a[4]=0 ,a[3]=1 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,s[2]=1 ,s[1]=0 ,s[0]=0 ,y=1 # 60a[7]=0 ,a[6]=0 ,a[5]=0 ,a[4]=0 ,a[3]=0 ,a[2]=1 ,a[1]=0 ,a[0]=0 ,s[2]=1 ,s[1]=0 ,s[0]=1 ,y=1 # 70a[7]=0 ,a[6]=0 ,a[5]=0 ,a[4]=0 ,a[3]=0 ,a[2]=0 ,a[1]=1 ,a[0]=0 ,s[2]=1 ,s[1]=1 ,s[0]=0 ,y=1 # 80a[7]=0 ,a[6]=0 ,a[5]=0 ,a[4]=0 ,a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=1 ,s[2]=1 ,s[1]=1 ,s[0]=1 ,y=1


NET " a[7]" LOC = "p74" ; NET " a[6]" LOC = "p76" ; NET " a[5]" LOC = "p77" ; NET " a[4]" LOC = "p79" ; NET " a[3]" LOC = "p78" ; NET " a[2]" LOC = "p82" ; NET " a[1]" LOC = "p80" ; NET " a[0]" LOC = "p83" ; NET " s[2]” LOC = "p84" ; NET " s[1]” LOC = "p85" ; NET " s[0]” LOC = "p86" ; NET " y” LOC = "p100" ;


18



WAVEFORM:

PROCEDURE














19






• Save the file.

















RESULT

The simulation and implementation of multiplexers is performed using Xilinx 9.1i and

FPGA kit.


20




DEMULTIPLEXER CIRCUITS AIM:

To write a verilog code to simulate demultiplexers and implement it on Field


APPARATUS REQUIRED:


THEORY:

A demultiplexer, sometimes abbreviated dmux, is a circuit that has one input and more than one output. It is used when a circuit wishes to send a signal to one of many devices. This description sounds similar to the description given for a decoder, but a decoder is used to select among many devices while a demultiplexer is used to send a signal among many devices. RTL SCHEMATIC: DMUX 1X2

DMUX 1X8


21



1:2 DEMUX

LOGICAL DIAGRAM

TRUTH TABLE

S Y0 Y1

0 D X

1 X D

1:4 DEMUX

LOGICAL DIAGRAM

TRUTH TABLE


22



PROGRAM:

1:2 DEMULTIPLEXER:

module dmux12(a, s, y); input a; input s; output [1:0] y; reg [1:0] y; always@(a,s) begin y[1]=0;y[0]=0; case(s) 1'b0:y[1]=a; 1'b1:y[0]=a; endcase end endmodule TESTBENCH FOR 1:2 DEMULTIPLEXER:

module tdmux12(); reg a,s; wire [1:0] y; dmux12 i1(a, s, y); initial begin a=0;s=0; #10 a=1;s=0; #10 a=1;s=1; end initial $monitor($time,"a=%b\t,s=%b\t,y[1]=%b\t,y[0]=%b\t",a,s,y[1],y[0]); initial #30 $finish; endmodule TRANSCRIPTED VIEW:

# 0a=0 ,s=0 ,y[1]=0 ,y[0]=0 # 10a=1 ,s=0 ,y[1]=1 ,y[0]=0 # 20a=1 ,s=1 ,y[1]=0 ,y[0]=1 USER CONSTRAINT FILE:

NET " a" LOC = "p74" ; NET " s” LOC = "p76" ; NET " y[1]” LOC = "p100" ;


23



NET " y[0]” LOC = "p102" ;

WAVEFORM:

PROGRAM:

1:4 DEMULTIPLEXER:

module dmux14(a, s, y); input a; input [1:0] s; output [3:0] y; reg [3:0] y; always@(a,s) begin y[3]=0;y[2]=0;y[1]=0;y[0]=0; case(s) 2'b00:y[3]=a; 2'b01:y[2]=a; 2'b10:y[1]=a; 2'b11:y[0]=a; endcase end endmodule TESTBENCH FOR 1:4 DEMULTIPLEXER:

module tdmux14(); reg a; reg [1:0] s; wire [3:0]y; dmux14 i1(a,s,y); initial begin a=0;s[1]=0;s[0]=0;


24



#10 a=1;s[1]=0;s[0]=0; #10 a=1;s[1]=0;s[0]=1; #10 a=1;s[1]=1;s[0]=0; #10 a=1;s[1]=1;s[0]=1; end initial $monitor($time,"a=%b\t,s[1]=%b\t,s[0]=%b\t,y[3]=%b\t,y[2]=%b\t,y[1]=%b\t,y[0]=%b\t,",a,s[1],s[0],y[3],y[2],y[1],y[0]); initial #50 $finish; endmodule TRANSCRIPTED VIEW:

# 0a=0 ,s[1]=0 ,s[0]=0 ,y[3]=0 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 10a=1 ,s[1]=0 ,s[0]=0 ,y[3]=1 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 20a=1 ,s[1]=0 ,s[0]=1 ,y[3]=0 ,y[2]=1 ,y[1]=0 ,y[0]=0 # 30a=1 ,s[1]=1 ,s[0]=0 ,y[3]=0 ,y[2]=0 ,y[1]=1 ,y[0]=0 # 40a=1 ,s[1]=1 ,s[0]=1 ,y[3]=0 ,y[2]=0 ,y[1]=0 ,y[0]=1 USER CONSTRAINT FILE:

NET " a" LOC = "p74" ; NET " s[1]” LOC = "p76" ; NET " s[0]” LOC = "p77" ; NET " y[3]” LOC = "p100" ; NET " y[2]" LOC = "p102" ; NET " y[1]" LOC = "p124" ; NET " y[0]" LOC = "p103" ; WAVEFORM:


25



PROGRAM:

1:8 DEMULTIPLEXER:

module dmux18(a, s, y); input a; input [2:0] s; output [7:0] y; reg [7:0] y; always@(a,s) begin y[7]=0;y[6]=0;y[5]=0;y[4]=0;y[3]=0;y[2]=0;y[1]=0;y[0]=0; case(s) 3'b000:y[7]=a; 3'b001:y[6]=a; 3'b010:y[5]=a; 3'b011:y[4]=a; 3'b100:y[3]=a; 3'b101:y[2]=a; 3'b110:y[1]=a; 3'b111:y[0]=a; endcase end endmodule TESTBENCH FOR 1:8 DEMULTIPLEXER:

module tdmux18(); reg a; reg [2:0] s; wire [7:0] y; dmux18 i1(a,s,y); initial begin a=0;s[2]=0;s[1]=0;s[0]=0; #10 a=1;s[2]=0;s[1]=0;s[0]=0; #10 a=1;s[2]=0;s[1]=0;s[0]=1; #10 a=1;s[2]=0;s[1]=1;s[0]=0; #10 a=1;s[2]=0;s[1]=1;s[0]=1; #10 a=1;s[2]=1;s[1]=0;s[0]=0; #10 a=1;s[2]=1;s[1]=0;s[0]=1; #10 a=1;s[2]=1;s[1]=1;s[0]=0; #10 a=1;s[2]=1;s[1]=1;s[0]=1; end initial $monitor($time,"a=%b\t,s[2]=%b\t,s[1]=%b\t,s[0]=%b\t,y[7]=%b\t,y[6]=%b\t,y[5]=%b\t,y[4]=%b\t,y[3]=%b\t,y[2]=%b\t,y[1]=%b\t,y[0]=%b\t,",a,s[2],s[1],s[0],y[7],y[6],y[5],y[4],y[3],y[2],y[1],y[0]); initial


26



#90 $finish; endmodule TRANSCRIPTED VIEW:

# 0a=0 ,s[2]=0 ,s[1]=0 ,s[0]=0 ,y[7]=0 ,y[6]=0 ,y[5]=0 ,y[4]=0 ,y[3]=0 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 10a=1 ,s[2]=0 ,s[1]=0 ,s[0]=0 ,y[7]=1 ,y[6]=0 ,y[5]=0 ,y[4]=0 ,y[3]=0 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 20a=1 ,s[2]=0 ,s[1]=0 ,s[0]=1 ,y[7]=0 ,y[6]=1 ,y[5]=0 ,y[4]=0 ,y[3]=0 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 30a=1 ,s[2]=0 ,s[1]=1 ,s[0]=0 ,y[7]=0 ,y[6]=0 ,y[5]=1 ,y[4]=0 ,y[3]=0 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 40a=1 ,s[2]=0 ,s[1]=1 ,s[0]=1 ,y[7]=0 ,y[6]=0 ,y[5]=0 ,y[4]=1 ,y[3]=0 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 50a=1 ,s[2]=1 ,s[1]=0 ,s[0]=0 ,y[7]=0 ,y[6]=0 ,y[5]=0 ,y[4]=0 ,y[3]=1 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 60a=1 ,s[2]=1 ,s[1]=0 ,s[0]=1 ,y[7]=0 ,y[6]=0 ,y[5]=0 ,y[4]=0 ,y[3]=0 ,y[2]=1 ,y[1]=0 ,y[0]=0 # 70a=1 ,s[2]=1 ,s[1]=1 ,s[0]=0 ,y[7]=0 ,y[6]=0 ,y[5]=0 ,y[4]=0 ,y[3]=0 ,y[2]=0 ,y[1]=1 ,y[0]=0 # 80a=1 ,s[2]=1 ,s[1]=1 ,s[0]=1 ,y[7]=0 ,y[6]=0 ,y[5]=0 ,y[4]=0 ,y[3]=0 ,y[2]=0 ,y[1]=0 ,y[0]=1


NET " a” LOC = "p74" ; NET " s[2]” LOC = "p76" ; NET " s[1]” LOC = "p77" ; NET " s[0]” LOC = "p79" ; NET " y[7]" LOC = "p100" ; NET " y[6]" LOC = "p102" ; NET " y[5]" LOC = "p124" ; NET " y[4]" LOC = "p103" ; NET " y[3]" LOC = "p105" ; NET " y[2]" LOC = "p107" ; NET " y[1]" LOC = "p108" ; NET " y[0]" LOC = "p113" ;


27



WAVEFORM:

PROCEDURE














28






• Save the file.

















RESULT

The simulation and implementation of demultiplexers is performed using Xilinx 9.1i and

FPGA kit.


29




ENCODER CIRCUITS AIM:

To write a verilog code to simulate encoder and implement it on Field Programmable Gate

Array (FPGA) kit.

APPARATUS REQUIRED:


THEORY:

An encoder performs the inverse operation of a decoder.It has 2N inputs, and N output

lines. Only one input can be logic 1 at any given time (active input). All other inputs must be 0’s.Output lines generate the binary code corresponding to the active input. RTL SCHEMATIC:

PROGRAM:

module enc(a, y); input [7:0] a; output [2:0] y; reg [2:0] y; always@(a) begin y[2]=0;y[1]=0;y[0]=0; y[2]=a[4]|a[5]|a[6]|a[7]; y[1]=a[2]|a[3]|a[6]|a[7]; y[0]=a[1]|a[3]|a[5]|a[7]; end endmodule TESTBENCH FOR ENCODER:

reg [7:0] a; wire [2:0] y; enc i1(a,y); initial


30



8:3 ENCODER

LOGIC DIAGRAM

TRUTH TABLE


31



begin a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; #10 a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=1; #10 a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=1;a[0]=0; #10 a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=1;a[1]=0;a[0]=0; #10 a[7]=0;a[6]=0;a[5]=0;a[4]=0;a[3]=1;a[2]=0;a[1]=0;a[0]=0; #10 a[7]=0;a[6]=0;a[5]=0;a[4]=1;a[3]=0;a[2]=0;a[1]=0;a[0]=0; #10 a[7]=0;a[6]=0;a[5]=1;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; #10 a[7]=0;a[6]=1;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; #10 a[7]=1;a[6]=0;a[5]=0;a[4]=0;a[3]=0;a[2]=0;a[1]=0;a[0]=0; end initial $monitor($time,"a[7]=%b\t,a[6]=%b\t,a[5]=%b\t,a[4]=%b\t,a[3]=%b\t,a[2]=%b\t,a[1]=%b\t,a[0]=%b\t,y[2]=%b\t,y[1]=%b\t,y[0]=%b\t",a[7],a[6],a[5],a[4],a[3],a[2],a[1],a[0],y[2],y[1],y[0],); initial #90 $finish; endmodule TRANSCRIPTED VIEW:

# 0a[7]=0 ,a[6]=0 ,a[5]=0 ,a[4]=0 ,a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 10a[7]=0 ,a[6]=0 ,a[5]=0 ,a[4]=0 ,a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=1 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 20a[7]=0 ,a[6]=0 ,a[5]=0 ,a[4]=0 ,a[3]=0 ,a[2]=0 ,a[1]=1 ,a[0]=0 ,y[2]=0 ,y[1]=0 ,y[0]=1 # 30a[7]=0 ,a[6]=0 ,a[5]=0 ,a[4]=0 ,a[3]=0 ,a[2]=1 ,a[1]=0 ,a[0]=0 ,y[2]=0 ,y[1]=1 ,y[0]=0 # 40a[7]=0 ,a[6]=0 ,a[5]=0 ,a[4]=0 ,a[3]=1 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,y[2]=0 ,y[1]=1 ,y[0]=1 # 50a[7]=0 ,a[6]=0 ,a[5]=0 ,a[4]=1 ,a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,y[2]=1 ,y[1]=0 ,y[0]=0 # 60a[7]=0 ,a[6]=0 ,a[5]=1 ,a[4]=0 ,a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,y[2]=1 ,y[1]=0 ,y[0]=1 # 70a[7]=0 ,a[6]=1 ,a[5]=0 ,a[4]=0 ,a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,y[2]=1 ,y[1]=1 ,y[0]=0 # 80a[7]=1 ,a[6]=0 ,a[5]=0 ,a[4]=0 ,a[3]=0 ,a[2]=0 ,a[1]=0 ,a[0]=0 ,y[2]=1 ,y[1]=1 ,y[0]=1 USER CONSTRAINT FILE: NET " a[7]" LOC = "p74" ; NET " a[6]" LOC = "p76" ; NET " a[5]" LOC = "p77" ; NET " a[4]" LOC = "p79" ; NET " a[3]" LOC = "p78" ; NET " a[2]" LOC = "p82" ; NET " a[1]" LOC = "p80" ; NET " a[0]" LOC = "p83" ; NET " y[2]” LOC = "p100" ; NET " y[1]” LOC = "p102" ; NET " y[0]” LOC = "p124" ;


32



WAVEFORM:

PROCEDURE











33









• Save the file.

















RESULT

The simulation and implementation of encoder is performed using Xilinx 9.1i and FPGA

kit.


34




DECODER CIRCUIT AIM:

To write a verilog code to simulate decoder and implement it on Field Programmable

Gate Array (FPGA) kit.

APPARATUS REQUIRED:


THEORY:

A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines.

RTL SCHEMATIC:

PROGRAM:

module dec(a, y); input [2:0] a; output [7:0] y; reg [7:0] y; always@(a) begin y[7]=0;y[6]=0;y[5]=0;y[4]=0;y[3]=0;y[2]=0;y[1]=0;y[0]=0; y[0]=(~a[2]&~a[1]&~a[0]); y[1]=(~a[2]&~a[1]&a[0]); y[2]=(~a[2]&a[1]&~a[0]); y[3]=(~a[2]&a[1]&a[0]); y[4]=(a[2]&~a[1]&~a[0]); y[5]=(a[2]&~a[1]&a[0]); y[6]=(a[2]&a[1]&~a[0]); y[7]=(a[2]&a[1]&a[0]); end endmodule


35



3:8 DECODER

LOGIC DIAGRAM

TRUTH TABLE

INPUTS OUTPUTS

e a b c Z(7) Z(6) Z(5) Z(4) Z(3) Z(2) Z(1) Z(0)

0 X X X 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 1

1 0 0 1 0 0 0 0 0 0 1 0

1 0 1 0 0 0 0 0 0 1 0 0

1 0 1 1 0 0 0 0 1 0 0 0

1 1 0 0 0 0 0 1 0 0 0 0

1 1 0 1 0 0 1 0 0 0 0 0

1 1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0


36



TESTBENCH FOR DECODER:

module tdec(); reg [2:0] a; wire [7:0] y; dec i1(a,y); initial begin a[2]=0;a[1]=0;a[0]=0; #10 a[2]=0;a[1]=0;a[0]=1; #10 a[2]=0;a[1]=1;a[0]=0; #10 a[2]=0;a[1]=1;a[0]=1; #10 a[2]=1;a[1]=0;a[0]=0; #10 a[2]=1;a[1]=0;a[0]=1; #10 a[2]=1;a[1]=1;a[0]=0; #10 a[2]=1;a[1]=1;a[0]=1; end initial $monitor($time,"a[2]=%b\t,a[1]=%b\t,a[0]=%b\t,y[7]=%b\t,y[6]=%b\t,y[5]=%b\t,y[4]=%b\t,y[3]=%b\t,y[2]=%b\t,y[1]=%b\t,y[0]=%b\t",a[2],a[1],a[0],y[7],y[6],y[5],y[4],y[3],y[2],y[1],y[0]); initial #80 $finish; endmodule TRANSCRIPTED VIEW:

# 0a[2]=0 ,a[1]=0 ,a[0]=0 ,y[7]=0 ,y[6]=0 ,y[5]=0 ,y[4]=0 ,y[3]=0 ,y[2]=0 ,y[1]=0 ,y[0]=1 # 10a[2]=0 ,a[1]=0 ,a[0]=1 ,y[7]=0 ,y[6]=0 ,y[5]=0 ,y[4]=0 ,y[3]=0 ,y[2]=0 ,y[1]=1 ,y[0]=0 # 20a[2]=0 ,a[1]=1 ,a[0]=0 ,y[7]=0 ,y[6]=0 ,y[5]=0 ,y[4]=0 ,y[3]=0 ,y[2]=1 ,y[1]=0 ,y[0]=0 # 30a[2]=0 ,a[1]=1 ,a[0]=1 ,y[7]=0 ,y[6]=0 ,y[5]=0 ,y[4]=0 ,y[3]=1 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 40a[2]=1 ,a[1]=0 ,a[0]=0 ,y[7]=0 ,y[6]=0 ,y[5]=0 ,y[4]=1 ,y[3]=0 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 50a[2]=1 ,a[1]=0 ,a[0]=1 ,y[7]=0 ,y[6]=0 ,y[5]=1 ,y[4]=0 ,y[3]=0 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 60a[2]=1 ,a[1]=1 ,a[0]=0 ,y[7]=0 ,y[6]=1 ,y[5]=0 ,y[4]=0 ,y[3]=0 ,y[2]=0 ,y[1]=0 ,y[0]=0 # 70a[2]=1 ,a[1]=1 ,a[0]=1 ,y[7]=1 ,y[6]=0 ,y[5]=0 ,y[4]=0 ,y[3]=0 ,y[2]=0 ,y[1]=0 ,y[0]=0 USER CONSTRAINT FILE:

NET " a[2]” LOC = "p74" ; NET " a[1]” LOC = "p76" ; NET " a[0]” LOC = "p77" ; NET " y[7]" LOC = "p100" ; NET " y[6]" LOC = "p102" ; NET " y[5]" LOC = "p124" ; NET " y[4]" LOC = "p103" ; NET " y[3]" LOC = "p105" ; NET " y[2]" LOC = "p107" ; NET " y[1]" LOC = "p108" ;


37



NET " y[0]" LOC = "p113" ;

WAVEFORM:

PROCEDURE










38










• Save the file.

















RESULT

The simulation and implementation of encoder is performed using Xilinx 9.1i and FPGA

kit.


39




RIPPLE CARRY ADDER

AIM:

To write a verilog code to simulate ripple carry adder and implement it on Field


APPARATUS REQUIRED:


THEORY:

It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is called a ripple-carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder.

The layout of a ripple-carry adder is simple, which allows for fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder.

RTL SCHEMATIC:

PROGRAM:

FULL ADDER:

module fa(a, b, c, sum, carry); input a; input b; input c; output sum; output carry; reg sum,carry; always@(a,b,c)


40



4 BIT RIPPLE CARRY ADDER

TRUTHTABLE


41



begin sum=a^b^c; carry=(a&b)|(b&c)|(c&a); end endmodule RIPPLE CARRY ADDER:

module ripple(a, b, cin, s, cout); input [3:0] a; input [3:0] b; input cin; output [3:0] s; output cout; wire [2:0] c; fa i1(a[0], b[0], cin, s[0], c[0]); fa i2(a[1], b[1], c[0], s[1], c[1]); fa i3(a[2], b[2], c[1], s[2], c[2]); fa i4(a[3], b[3], c[2], s[3], cout); endmodule TESTBENCH FOR RIPPLE CARRY ADDER:

module tripple(); reg [3:0] a; reg [3:0] b; reg cin; wire [3:0] s; wire cout; ripple i1(a, b, cin, s, cout); initial begin a=4'b0001;b=4'b0001;cin=1'b0; #10 a=4'b0101;b=4'b0001;cin=1'b0; #10 a=4'b1111;b=4'b0111;cin=1'b0; #10 a=4'b0001;b=4'b1101;cin=1'b0; end initial $monitor($time,"a=%b\t,b=%b\t,cin=%b\t,s=%b\t,cout=%b\t",a,b,cin,s,cout); initial #40 $finish; endmodule TRANSCRIPTED VIEW:

# 0a=0001 ,b=0001 ,cin=0 ,s=0010 ,cout=0 # 10a=0101 ,b=0001 ,cin=0 ,s=0110 ,cout=0 # 20a=1111 ,b=0111 ,cin=0 ,s=0110 ,cout=1 # 30a=0001 ,b=1101 ,cin=0 ,s=1110 ,cout=0


42




NET " a[3]" LOC = "p74" ; NET " a[2]" LOC = "p76" ; NET " a[1]" LOC = "p77" ; NET " a[0]" LOC = "p79" ; NET " b[3]" LOC = "p78" ; NET " b[2]" LOC = "p82" ; NET " b[1]" LOC = "p80" ; NET " b[0]" LOC = "p83" ; NET "cin” LOC = "p84" ; NET " s[3]" LOC = "p100" ; NET " s[2]" LOC = "p102" ; NET " s[1]" LOC = "p124" ; NET " s[0]" LOC = "p103" ; NET "cout" LOC = "p105" ;

WAVEFORM:

PROCEDURE





43















• Save the file.

















RESULT

The simulation and implementation of ripple carry adder is performed using Xilinx 9.1i

and FPGA kit.


44




MAGNITUDE COMPARATOR

AIM:

To write a verilog code to simulate magnitude comparator and implement it on Field


APPARATUS REQUIRED:


THEORY: A digital comparator or magnitude comparator is a hardware electronic device that takes two numbers as input in binary form and determines whether one number is greater than, less than or equal to the other number. Comparators are used in central processing units (CPUs) and microcontrollers (MCUs). The analog equivalent of digital comparator is the voltage comparator. Consider two numbers, A and B, with four digits each: A=A0A1A2A3, B=B0B1B2B3. To determine if A is greater than or less than B, we inspect the relative magnitudes of significant digits. If the two digits are equal, we compare the next lower significant pair of digits. The comparison continues until a pair of unequal digits is reached.

RTL SCHEMATIC:

PROGRAM:

MAGNITUDE COMPARATOR:

module magcom(a, b, gr, ls, eq); input [3:0] a; input [3:0] b; output gr; output ls; output eq; reg gr,ls,eq; always@(a,b)


45



begin if(a>b) begin gr=1;ls=0;eq=0; end else if(a<b) begin gr=0;ls=1;eq=0; end else begin gr=0;ls=0;eq=1; end end endmodule

TESTBENCH FOR MAGNITUDE COMPARATOR:

module tmagcom(); reg [3:0] a; reg [3:0] b; wire gr,ls,eq; magcom i1(a,b,gr,ls,eq); initial begin a=4'b0000;b=4'b0100; #10 a=4'b1011;b=4'b1100; #10 a=4'b1010;b=4'b1010; #10 a=4'b1111;b=4'b0111; #10 a=4'b0010;b=4'b0010; #10 a=4'b1000;b=4'b0110; end initial $monitor($time,"a=%b\t,b=%b\t,gr=%b\t,ls=%b\t,eq=%b\t",a,b,gr,ls,eq); initial #60 $finish; Endmodule TRANSCRIPTED VIEW:

# 0a=0000 ,b=0100 ,gr=0 ,ls=1 ,eq=0 # 10a=1011 ,b=1100 ,gr=0 ,ls=1 ,eq=0 # 20a=1010 ,b=1010 ,gr=0 ,ls=0 ,eq=1 # 30a=1111 ,b=0111 ,gr=1 ,ls=0 ,eq=0 # 40a=0010 ,b=0010 ,gr=0 ,ls=0 ,eq=1 # 50a=1000 ,b=0110 ,gr=1 ,ls=0 ,eq=0 USER CONSTRAINT FILE:

NET " a[3]” LOC = "p74" ; NET " a[2]” LOC = "p76" ;


46



NET " a[1]” LOC = "p77" ; NET " a[0]" LOC = "p79" ; NET " b[3]" LOC = "p78" ; NET " b[2]" LOC = "p82" ; NET " b[1]" LOC = "p80" ; NET " b[0]" LOC = "p83" ; NET " gr" LOC = "p100" ; NET " ls" LOC = "p102" ; NET " eq" LOC = "p124" ; WAVEFORM:

PROCEDURE








47












• Save the file.

















RESULT

The simulation and implementation of magnitude comparator is performed using Xilinx

9.1i and FPGA kit.


48




(DELAY) D FLIP FLOP

AIM:

To perform simulation and implementation of D flip-flop using Xilinx 9.1i.

APPARATUS REQUIRED:

System with P4 processor, FPGA kit.

SOFTWARE REQUIRED:

Xilinx ISE 9.1i,Modelsim 5.7f

THEORY:

The D flip-flop is widely used. It is also known as a data or delay flip-flop.The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change. The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line. These flip-flops are very useful, as they form the basis for shift registers, which are an essential part of many electronic devices. RTL SCHEMATIC:

PROGRAM:

D FLIP FLOP:

module dff(din, clk, rst, dout, doutb); input din; input clk; input rst; output dout; output doutb;


49



LOGIC DIAGRAM

TRUTH TABLE


50



reg dout,doutb; initial dout=1'b0; always@(negedge clk) begin if(rst) begin dout=1'b0; doutb=(~dout); end else begin dout=din; doutb=(~dout); end end endmodule

TESTBENCH FOR D FLIP FLOP:

module tdff(); reg din,clk,rst; wire dout,doutb; dff i1(din, clk, rst, dout, doutb); initial begin clk=0; din=0; rst=0; end always #1 rst=~rst; always #3 clk=~clk; always #5 din=~din; initial $monitor($time,"rst=%b\t,clk=%b\t,din=%b\t,dout=%b\t,doutb=%b\t",rst,clk,din,dout,doutb); endmodule

TRANSCRIPTED VIEW:

# 0rst=0 ,clk=0 ,din=0 ,dout=0 ,doutb=1 # 1rst=1 ,clk=0 ,din=0 ,dout=0 ,doutb=1 # 2rst=0 ,clk=0 ,din=0 ,dout=0 ,doutb=1 # 3rst=1 ,clk=1 ,din=0 ,dout=0 ,doutb=1 # 4rst=0 ,clk=1 ,din=0 ,dout=0 ,doutb=1 # 5rst=1 ,clk=1 ,din=1 ,dout=0 ,doutb=1 # 6rst=0 ,clk=0 ,din=1 ,dout=1 ,doutb=0 # 7rst=1 ,clk=0 ,din=1 ,dout=1 ,doutb=0


51



# 8rst=0 ,clk=0 ,din=1 ,dout=1 ,doutb=0 # 9rst=1 ,clk=1 ,din=1 ,dout=1 ,doutb=0 # 10rst=0 ,clk=1 ,din=0 ,dout=1 ,doutb=0 # 11rst=1 ,clk=1 ,din=0 ,dout=1 ,doutb=0 # 12rst=0 ,clk=0 ,din=0 ,dout=0 ,doutb=1 # 13rst=1 ,clk=0 ,din=0 ,dout=0 ,doutb=1 # 14rst=0 ,clk=0 ,din=0 ,dout=0 ,doutb=1 # 15rst=1 ,clk=1 ,din=1 ,dout=0 ,doutb=1 # 16rst=0 ,clk=1 ,din=1 ,dout=0 ,doutb=1 # 17rst=1 ,clk=1 ,din=1 ,dout=0 ,doutb=1 # 18rst=0 ,clk=0 ,din=1 ,dout=1 ,doutb=0 # 19rst=1 ,clk=0 ,din=1 ,dout=1 ,doutb=0 # 20rst=0 ,clk=0 ,din=0 ,dout=1 ,doutb=0 USER CONSTRAINT FILE:

NET "rst” LOC = "p74" ; NET "clk” LOC = "p76" ; NET "din” LOC = "p77" ; NET "dout” LOC = "p100" ; NET " doutb” LOC = "p102" ; WAVEFORM:

PROCEDURE:




• In the source window, right click on project name and press create new source � In the new source wizard – select verilog module and type file name. Press next.


52



� Enter input, output ports and set their directions accordingly in the define module window.

� Enter finish.


• Go to process window and double click synthesis XST.










• Save the file.







1. Select sources for Synthesis/Implementation 2. Select the created module(*.v file) in the source window. 3. Select user constraint in the process window, double click edit constraint to create user

constraint file(UCF). 4. Type the net list to define the I/O pins & save it. 5. Double click implement design in the process window. 6. Double click Generate programming file & select the respective created bit file (*.bit) 7. Double click configure device (iMPACT). In the impact window, Select configure device

using boundary scan. Click finish 8. Right click on the created xilinx model & select the program, give OK on the displayed

window. 9. The bit file is downloaded into the FPGA if the message “PROGRAM SUCCEEDED” is

displayed 10. Change the status of the switches and verify the status of the LEDs.

RESULT

The simulation and implementation of D flip-flop is performed using Xilinx 9.1i and FPGA kit.


53



Ex No.10 IMPLEMENTATION OF COUNTER AIM:

To implement a 4-bit updown counter using Xilinx 9.1i.

APPARATUS REQUIRED:


SOFTWARE REQUIRED:


RTL SCHEMATIC:

THEORY:

A register that goes through a prescribed sequence of states up on application of input

pulses is called a counter. It is a sequential circuit. Counter is the widest application of flip-flops.

It is a group of flip-flops with a clock signal applied. Counters count the number of clock pulse.

Hence with some modification it can be used for measuring frequency or time period.

Counters are basically of two types

(1)Asynchronous or ripple counters

(2)Synchronous counters.

Asynchronous or ripple counters: for these counters the external clock signal is applied to one

flip-flop and then the output of preceding flip-flop is connected to the clock of next flip-flop.

Synchronous counters: In synchronous counter all the flip=flops receive the external clock pulse

simultaneously. Ring counter and Johnson counter are the example of synchronous counter.


54



PROGRAM:

COUNTER:

module count(clk, reset, updown, count); input clk; input reset; input updown; output [3:0] count; reg [3:0] count; integer timer_count1=0,timer_count2=0; reg clk_msec,clk_sec; always@(posedge clk) begin if(timer_count1==3999) begin timer_count1=0; clk_msec=1'b1; end else begin timer_count1=timer_count1+1; clk_msec=1'b0; end end always@(posedge clk_msec) begin if(timer_count2==999) begin timer_count2=0; clk_sec=1'b1; end else begin timer_count2=timer_count2+1; clk_sec=1'b0; end end always@(posedge clk_sec) begin if(updown==0) begin if(~reset) count=4'b0000; else count=count-1; end if(updown==1)


55



begin if(~reset) count=4'b0000; else count=count+1; end end endmodule


NET "clk” LOC = "p52" ; NET "reset” LOC = "p74" ; NET "updown” LOC = "p76" ; NET “count[3]” LOC = "p100" ; NET "count[2]” LOC = "p102" ; NET "count[1]” LOC = "p124" ; NET "count[0]” LOC = "p103" ;

PROCEDURE:
















56







RESULT

The implementation of 4 bit updown counter is performed using Xilinx 9.1i and FPGA kit.


57



Ex No.11 SIMULATION OF ACCUMULATOR

AIM:

To perform simulation of Accumulator using Xilinx 9.1i.

APPARATUS REQUIRED:

System with P4 processor.

SOFTWARE REQUIRED:


THEORY:

In a computer's central processing unit (CPU), an accumulator is a register in which intermediate arithmetic and logic results are stored. Without a register like an accumulator, it would be necessary to write the result of each calculation (addition, multiplication, shift, etc.) to main memory, perhaps only to be read right back again for use in the next operation. Access to main memory is slower than access to a register like the accumulator because the technology used for the large main memory is slower (but cheaper) than that used for a register.

The canonical example for accumulator use is summing a list of numbers. The accumulator is initially set to zero, and then each number in turn is added to the value in the accumulator. Only when all numbers have been added is the result held in the accumulator written to main memory or to another, non-accumulator, CPU register.

PROGRAM:

ACCUMULATOR:

module acc(c, clr, d, q); input c; input clr; input [3:0] d; output [3:0] q; reg [3:0] tmp; initial tmp=4'b0000; always@(posedge c or posedge clr) begin if(clr) tmp=4'b0000; else tmp=tmp+d; end assign q=tmp; endmodule


58



TESTBENCH FOR ACCUMULATOR:

module tacc(); reg c,clr; reg [3:0] d; wire [3:0] q; acc i1(c,clr,d,q); initial begin clr=0; c=0; end always #3 c=~c; initial begin d=4'b0000; #5 d=4'b0001; #5 d=4'b0010; #5 d=4'b0011; #10 clr=1; end initial $monitor($time,"c=%b\t,clr=%b\t,d=%b\t,q=%b\t",c,clr,d,q); initial #40 $finish; Endmodule TRANSCRIPTED VIEW:

# 0c=0 ,clr=0 ,d=0000 ,q=0000 # 3c=1 ,clr=0 ,d=0000 ,q=0000 # 5c=1 ,clr=0 ,d=0001 ,q=0000 # 6c=0 ,clr=0 ,d=0001 ,q=0000 # 9c=1 ,clr=0 ,d=0001 ,q=0001 # 10c=1 ,clr=0 ,d=0010 ,q=0001 # 12c=0 ,clr=0 ,d=0010 ,q=0001 # 15c=1 ,clr=0 ,d=0011 ,q=0100 # 18c=0 ,clr=0 ,d=0011 ,q=0100 # 21c=1 ,clr=0 ,d=0011 ,q=0111 # 24c=0 ,clr=0 ,d=0011 ,q=0111 # 25c=0 ,clr=1 ,d=0011 ,q=0000 # 27c=1 ,clr=1 ,d=0011 ,q=0000 # 30c=0 ,clr=1 ,d=0011 ,q=0000 # 33c=1 ,clr=1 ,d=0011 ,q=0000 # 36c=0 ,clr=1 ,d=0011 ,q=0000 # 39c=1 ,clr=1 ,d=0011 ,q=0000


59



WAVEFORM:

PROCEDURE:
















60





• Save the file.






RESULT

The simulation of Accumulator is performed using Xilinx 9.1i and Modelsim 5.7f.


61



Ex No.12 SIMILATION OF PSEUDO RANDOM BIT SEQUENCE (PRBS) GENERATOR

AIM:

To perform simulation of Pseudo random bit sequence (PRBS) generator using Xilinx 9.1i. APPARATUS REQUIRED:


SOFTWARE REQUIRED:


THEORY:

A Pseudo Random Bit Sequence (PRBS) Generator is used to generate a random sequence of 1’s and 0’s. PRBS Generator is implemented using maximal length LFSR (Linear Feedback Shift Register).Since it generates data that is almost random.

A linear feedback shift register (LFSR) is shift register whose input bit is a linear function of its previous state. The only linear functions of single bits are XOR and XNOR; thus it is a register whose input bit is driven by the exclusive-or (XOR) of some bits of the overall shift register value.

PROGRAM:

PRBS GENERATOR:

module prbs(clk, rst, rand); input clk; input rst; output rand; reg rand; reg [3:0] tmp; initial tmp=4'b1111; always@(posedge clk) begin if(rst==0) begin rand=tmp[0]; tmp={tmp[0]^tmp[1],tmp[3],tmp[2],tmp[1]}; end else tmp=4'b1111; end endmodule


62



LOGIC DIAGRAM


63



TESTBENCH FOR PRBS GENERATOR:

module tprbs(); reg clk,rst; wire rand; prbs i1(clk,rst,rand); always #3 clk=~clk; initial begin clk=1;rst=0; #200 rst=1; end initial $monitor($time,"clk=%b\t,rst=%b\t,rand=%b\t",clk,rst,rand); initial #300 $finish; endmodule

WAVEFORM:

PROCEDURE:




64

















• Save the file.






RESULT

The simulation of Pseudo random bit sequence (PRBS) generator is performed using Xilinx 9.1i

and Modelsim 5.7f.


65



Ex No.13 SIMULATION OF CMOS CIRCUITS

AIM:

To perform simulation of CMOS NOT,NAND, and NOR Xilinx 9.1i and Modelsim5.7f. APPARATUS REQUIRED:


SOFTWARE REQUIRED:


THEORY:

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–

semiconductor (or COS-MOS). The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.

Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Since one transistor of the pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which normally have some standing current even when not changing state. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in VLSI chips.

PROGRAM:

CMOS NOT:

module cnot(in, out); input in; output out; supply1 vdd; supply0 gnd; nmos n1(out,gnd,in); pmos p1(out,vdd,in); endmodule TESTBENCH FOR CMOS NOT:

module tcnot(); reg in; wire out;


66



cnot i1(in, out); initial begin in=1'b0; #10 in=1'b1; end always #3 in=~in; initial $monitor($time,"in=%b\t,out=%b\t",in,out); initial #20 $finish; endmodule TRANSCRIPTED VIEW:

# 0in=0 ,out=1 # 3in=1 ,out=0 # 6in=0 ,out=1 # 9in=1 ,out=0 # 12in=0 ,out=1 # 15in=1 ,out=0 # 18in=0 ,out=1

WAVEFORM:

PROGRAM:

CMOS NAND:

module cnand(a, b, y); input a; input b; output y; supply1 vdd; supply0 gnd; nmos n1(y,out,a); nmos n2(out,gnd,b); pmos p1(y,vdd,a); pmos p2(y,vdd,b);


67



endmodule TESTBENCH FOR CMOS NAND:

module tcnand(); reg a,b; wire y; cnand i1(a, b, y); initial begin a=1'b0;b=1'b0; #10 a=1'b0;b=1'b1; #10 a=1'b1;b=1'b0; #10 a=1'b1;b=1'b1; end initial $monitor($time,"a=%b\t,b=%b\t,y=%b\t",a,b,y); initial #40 $finish; Endmodule TRANSCRIPTED VIEW:

# 0a=0 ,b=0 ,y=1 # 10a=0 ,b=1 ,y=1 # 20a=1 ,b=0 ,y=1 # 30a=1 ,b=1 ,y=0 WAVEFORM:

PROGRAM:

CMOS NOR:

module cnor(a, b, y); input a;


68



input b; output y; supply1 vdd; supply0 gnd; nmos n1(y,gnd,a); nmos n2(y,gnd,b); pmos p1(out,vdd,a); pmos p2(y,out,b); endmodule

TESTBENCH FOR CMOS NOR:

module tcnor(); reg a,b; wire y; cnor i1(a, b, y); initial begin a=1'b0;b=1'b0; #10 a=1'b0;b=1'b1; #10 a=1'b1;b=1'b0; #10 a=1'b1;b=1'b1; end initial $monitor($time,"a=%b\t,b=%b\t,y=%b\t",a,b,y); initial #40 $finish; endmodule TRANSCRIPTED VIEW:

# 0a=0 ,b=0 ,y=1 # 10a=0 ,b=1 ,y=0 # 20a=1 ,b=0 ,y=0 # 30a=1 ,b=1 ,y=0


69



WAVEFORM:

PROCEDURE:

















• Save the file.


70








RESULT

The simulation of CMOS NOT, NAND ,and NOR is performed using Xilinx 9.1i and

Modelsim 5.7f.


71



Ex No.14 IMPLEMENTATION OF SERIAL ADDER AIM:

To perform the implementation of serial adder using Xilinx 9.1i.

APPARATUS REQUIRED:


SOFTWARE REQUIRED:


THEORY:

Addition of serial binary numbers is done using serial adders. It requires only one full adder. The

serial input data bit are applied after each clock pulse, say, first the least significant bits A0 and B0 appears,

then one clock pulse-next A1 and B1 –one clock pulse-next A2 and B2 and so on. If a carry bit is generated

in any one of the addition then it is saved and added to the next higher-order pair of input bits. The carry is

stored using flip-flop (storage device) for duration of one clock pulse and shift it as Cin with the next pair

of input bits. The time taken to perform addition is more when compared with parallel adders.

RTL SCHEMATIC:

PROGRAM:

SERIAL ADDER:

module ser(clk, clear, calc, load, addr, data, result); input clk; input clear; input calc;


72



LOGIC DIAGRAM


73



input load; input [1:0] addr; input [7:0] data; output reg [8:0] result; reg [7:0] ram[3:0]; always@(posedge clk) begin if(~clear) begin ram[0]=8'b0; ram[1]=8'b0; ram[2]=8'b0; ram[3]=8'b0; end else if(~load) ram[addr]=data; end always@(posedge clk) begin if(~load) result=data; else if(~calc) result=ser_add(ram[0],ram[1],ram[2],ram[3]); else result=ram[addr]; end function [8:0]ser_add; input [7:0] a,b,c,d; reg [8:0] a_mag,b_mag,c_mag,d_mag; reg [2:0] bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8; reg [8:0] y_mag; begin case(a[7]) 0:a_mag={2'b0,a[6:0]}; 1:a_mag=1024-{2'b0,a[6:0]}; endcase case(b[7]) 0:b_mag={2'b0,b[6:0]}; 1:b_mag=1024-{2'b0,b[6:0]}; endcase case(c[7]) 0:c_mag={2'b0,c[6:0]}; 1:c_mag=1024-{2'b0,c[6:0]}; endcase case(d[7]) 0:d_mag={2'b0,d[6:0]}; 1:d_mag=1024-{2'b0,d[6:0]};


74



endcase bit0=a_mag[0]+b_mag[0]+c_mag[0]+d_mag[0]; bit1=a_mag[1]+b_mag[1]+c_mag[1]+d_mag[1]+bit0[2:1]; bit2=a_mag[2]+b_mag[2]+c_mag[2]+d_mag[2]+bit1[2:1]; bit3=a_mag[3]+b_mag[3]+c_mag[3]+d_mag[3]+bit2[2:1]; bit4=a_mag[4]+b_mag[4]+c_mag[4]+d_mag[4]+bit3[2:1]; bit5=a_mag[5]+b_mag[5]+c_mag[5]+d_mag[5]+bit4[2:1]; bit6=a_mag[6]+b_mag[6]+c_mag[6]+d_mag[6]+bit5[2:1]; bit7=a_mag[7]+b_mag[7]+c_mag[7]+d_mag[7]+bit6[2:1]; bit8=a_mag[8]+b_mag[8]+c_mag[8]+d_mag[8]+bit7[2:1]; y_mag={bit8[0],bit7[0],bit6[0],bit5[0],bit4[0],bit3[0],bit2[0],bit1[0],bit0[0]}; ser_add=y_mag; end endfunction endmodule


NET "addr[0]" LOC = "p80" ; NET "addr[1]" LOC = "p82" ; NET "calc" LOC = "p130" ; NET "clear" LOC = "p137" ; NET "clk" LOC = "p52" ; NET "data[0]" LOC = "p92" ; NET "data[1]" LOC = "p96" ; NET "data[2]" LOC = "p74" ; NET "data[3]" LOC = "p76" ; NET "data[4]" LOC = "p77" ; NET "data[5]" LOC = "p79" ; NET "data[6]" LOC = "p84" ; NET "data[7]" LOC = "p85" ; NET "load" LOC = "p83" ; NET "result[0]" LOC = "p51" ; NET "result[1]" LOC = "p50" ; NET "result[2]" LOC = "p47" ; NET "result[3]" LOC = "p46" ; NET "result[4]" LOC = "p44" ; NET "result[5]" LOC = "p33" ; NET "result[6]" LOC = "p31" ; NET "result[7]" LOC = "p28" ; NET "result[8]" LOC = "p57" ;

PROCEDURE:


• File New Project � New project wizard appears. � Type project name and location. Enter next. � In the next window, set the device properties (or leave of with default). � Create new source window, press next.


75



� Add existing source, press next. � Click finish.

















RESULT:

The implementation of Serial Adder is performed by using Xilinx 9.1i.


76



Ex No.15 IMPLEMENTATION OF PARALLEL ADDER AIM:

To perform the implementation of parallel adder using Xilinx 9.1i.

APPARATUS REQUIRED:


SOFTWARE REQUIRED:


THEORY:

The basic parallel adder circuit can be used to perform both addition and subtraction. A n-bit

,parallel adder can be constructed using number of full adder circuit connected in parallel. To perform

subtraction ,negative numbers are given in 2’s complimented form. It should be noted that either a half

adder can be used for the least significant position or the carry input of a full-adder is made 0 because

there is no carry into the least significant bit position.

RTL SCHEMATIC:

PROGRAM:

PARALLEL ADDER:

module ser(clk, clear, calc, load, addr, data, result); input clk; input clear; input calc; input load;


77



LOGIC DIAGRAM


78



input [1:0] addr; input [7:0] data; output reg [8:0] result; reg [7:0] ram[3:0]; always@(posedge clk) begin if(~clear) begin ram[0]=8'b0; ram[1]=8'b0; ram[2]=8'b0; ram[3]=8'b0; end else if(~load) ram[addr]=data; end always@(posedge clk) begin if(~load) result=data; else if(~calc) result=ser_add(ram[0],ram[1],ram[2],ram[3]); else result=ram[addr]; end function [8:0]ser_add; input [7:0] a,b,c,d; reg [8:0] a_mag,b_mag,c_mag,d_mag; reg [2:0] bit0,bit1,bit2,bit3,bit4,bit5,bit6,bit7,bit8; reg [8:0] y_mag; begin case(a[7]) 0:a_mag={2'b0,a[6:0]}; 1:a_mag=1024-{2'b0,a[6:0]}; endcase case(b[7]) 0:b_mag={2'b0,b[6:0]}; 1:b_mag=1024-{2'b0,b[6:0]}; endcase case(c[7]) 0:c_mag={2'b0,c[6:0]}; 1:c_mag=1024-{2'b0,c[6:0]}; endcase case(d[7]) 0:d_mag={2'b0,d[6:0]}; 1:d_mag=1024-{2'b0,d[6:0]};


79



endcase y_mag=a_mag+b_mag+c_mag+d_mag; ser_add=y_mag; end endfunction endmodule USER CONSTRAINT FILE:

NET "addr[0]" LOC = "p80" ; NET "addr[1]" LOC = "p82" ; NET "calc" LOC = "p130" ; NET "clear" LOC = "p137" ; NET "clk" LOC = "p52" ; NET "data[0]" LOC = "p92" ; NET "data[1]" LOC = "p96" ; NET "data[2]" LOC = "p74" ; NET "data[3]" LOC = "p76" ; NET "data[4]" LOC = "p77" ; NET "data[5]" LOC = "p79" ; NET "data[6]" LOC = "p84" ; NET "data[7]" LOC = "p85" ; NET "load" LOC = "p83" ; NET "result[0]" LOC = "p51" ; NET "result[1]" LOC = "p50" ; NET "result[2]" LOC = "p47" ; NET "result[3]" LOC = "p46" ; NET "result[4]" LOC = "p44" ; NET "result[5]" LOC = "p33" ; NET "result[6]" LOC = "p31" ; NET "result[7]" LOC = "p28" ; NET "result[8]" LOC = "p57" ;

PROCEDURE:








80















RESULT:

The implementation of Parallel Adder is performed by using Xilinx 9.1i.


81



Ex No.16 IMPLEMENTATION OF SIGNED MULTIPLIER AIM:

To perform the implementation of signed multiplication using Xilinx 9.1i.

APPARATUS REQUIRED:


SOFTWARE REQUIRED:


THEORY:

Booth's multiplication algorithm is a multiplication algorithm that multiplies two signed binary

numbers in two's complement notation. The algorithm was invented by Andrew Donald Booth in 1950.

Booth used desk calculators that were faster at shifting than adding and created the algorithm to increase

their speed. Multipliers that uses booth’s algorithm recode the bits of the multiplier to reduce the number

of additions required to complete a cycle of multiplication. Only the multiplier is recoded; the multiplicand

is left unchanged.

In general, for Booth’s algorithm recoding scheme can be given as:

-1 times the shifted multiplicand is selected when moving from 0 to 1, +1 time the shifted multiplicand is

selected when moving from 1 to 0, and 0 times the shifted multiplicand is selected for none of the above

case, as multiplier is scanned from right to left.

RTL SCHEMATIC:


82



PROGRAM:

4-BIT SIGNED MULTIPLICATION:

module mul(clk, clear, calc, load, addr, data_in, result); input clk; input clear; input calc; input load; input addr; input [4:0] data_in; output reg [7:0] result; reg [4:0] ram[1:0]; always@(posedge clk) begin if(~clear) begin ram[0]=4'b0; ram[1]=4'b0; end else if(~load) ram[addr]=data_in; end always@(posedge clk) begin if(~load) result={3'b0,data_in}; else if(~calc) result=multiply(ram[0],ram[1]); else result={3'b0,ram[addr]}; end function [7:0]multiply; input [4:0]mr; input [4:0]md; integer i; reg [7:0] temp; reg [1:0] a; reg [5:0] y; reg [4:0] x; reg [7:0] z; reg [4:0] mr_mag,md_mag; begin case(mr[4]) 0:mr_mag={1'b0,mr[3:0]}; 1:mr_mag=32-{1'b0,mr[3:0]}; endcase case(md[4])


83



0:md_mag={1'b0,md[3:0]}; 1:md_mag=32-{1'b0,md[3:0]}; endcase y[5:0]=6'b00000; y[5:1]=md_mag[4:0]; x[4:0]=mr_mag[4:0]; z=8'b00000000; temp=8'b00000000; for(i=0;i<5;i=i+1) begin a[0]=y[i]; a[1]=y[i+1]; case(a) 2'b01:temp[4:0]=x[4:0]; 2'b10:temp[4:0]=(~x[4:0]+5'b00001); 2'b11:temp[4:0]=5'b00000; 2'b00:temp[4:0]=5'b00000; endcase if(temp[4]==0) begin temp[7:5]=3'b000; end else begin temp[7:5]=3'b111; end temp=temp<<i; z=z+temp; end multiply=z; end endfunction endmodule


NET "addr" LOC = "p80" ; NET "calc" LOC = "p130" ; NET "clear" LOC = "p137" ; NET "clk" LOC = "p52" ; NET " data_in [0]" LOC = "p92" ; NET " data_in [1]" LOC = "p96" ; NET " data_in [2]" LOC = "p74" ; NET " data_in [3]" LOC = "p76" ; NET " data_in [4]" LOC = "p77" ; NET "load" LOC = "p83" ; NET "result[0]" LOC = "p51" ; NET "result[1]" LOC = "p50" ; NET "result[2]" LOC = "p47" ;


84



NET "result[3]" LOC = "p46" ; NET "result[4]" LOC = "p44" ; NET "result[5]" LOC = "p33" ; NET "result[6]" LOC = "p31" ; NET "result[7]" LOC = "p28" ; PROCEDURE:



















RESULT:

The implementation of 4-bit signed multiplication is performed by using Xilinx 9.1i.


85



Ex No.17 VERIFICATION OF CMOS CIRCUITS USING TANNER SOFTWARE

AIM: To perform the functional verification of CMOS NOT, NAND, NOR and EX-OR using S-

Edit.

APPARATUS REQUIRED: System with P4 Processor & Tanner EDA Tool. THEORY: Tanner (Electronic design automation)EDA is a suite of tools for the design of integrated circuits. These tools allow you to enter schematics, perform SPICE simulations, do physical design (i.e., chip layout), and perform design rule checks (DRC) and layout versus schematic (LVS) checks. There are 3 tools that are used for this process: S-edit-a schematic capture tool. T-SPICE-the SPICE simulation engine integrated with S-edit. L-edit-the physical design tool.

S-Edit: S-edit is a schematic entry tool that is used to document circuits that can be driven forward into a layout of an integrated circuit. It also provides the ability to perform SPICE simulations of the circuits using a simulation engine called T-SPICE.

CMOS NOT

SCHEMATIC:


86



OUTPUT WAVEFORM:

CMOS NAND

SCHEMATICS:


87



OUTPUT WAVEFORM:

CMOS NOR

SCHEMATIC:


88



OUTPUT WAVEFORM:

EX-OR USING CMOS NAND:

SCHEMATIC:


89



OUTPUT WAVEFORM:

EX-OR USING CMOS NAND:

SCHEMATIC:


90



OUTPUT WAVEFORM:

EX-OR USING CMOS NOR:

SCHEMATIC:


91



OUTPUT WAVEFORM:

SYMBOL FOR NAND GATE


92



SYMBOL FOR NOR GATE

BOOLEAN EXPRESSION Y=A+BC(~D) USING NAND

SCHEMATIC:


93



OUTPUT WAVEFORM:

BOOLEAN EXPRESSION Y=A+BC(~D) USING NOR

SCHEMATIC:


94



OUTPUT WAVEFORM:

PROCEDURE:

Start a New Design & Setup Libraries a) Start S-Edit: - Start → All Programs → Tanner EDA → Tanner Tools v15.0 → S-Edit v15.0 b) Start a New Design:

Using the pull down menus, create a new design:

- File → New → New Design

A dialog will appear asking for a design name and location. When you give the name, S-edit will create a

folder of that name in the directory that you provide that will contain all of the design files.

c) Create a new Cell. A “cell” is a design element. A cell can contain multiple views such as

schematics and symbols. Cells can be instantiated in other cells.

Using the pull down menus, create a new cell view: - Cell – New View: and click OK. A blank schematic page will appear.

d) First, you need to include a library which contains the symbols for all basic circuit elements such

as resistors, NMOS, capacitors, etc…

e) e)On the left side of the S-edit screen you’ll see a Libraries window, click on the “Add” button. –

Browse to Tanner EDA\TannerToolsv15.0\Process\Standard_Libraries\SPICE_Elements\SPICE_Elements.tanner” and click “OK” Again click on the add button:


95



Browse to“C:\Documents and Settings\administrator\My Documents\Tanner EDA\Tanner Tools

v15.0\Process\Generic_250nm\Generic_250nm_Devices\Generic_250nm_Devices.tanner”

The libraries that you just added have symbols for NMOS and PMOS transistors. However, all non-linear

components such as MOS transistors require a model to describe their behavior. we will use a transistor

technology called “Generic_025”, which represents a standard, 0.25um CMOS process.

f) Enter the NMOS transistor - On the left, click on “Devices” in the upper window. This will

display all of the symbols available in this group. You should see all of the components that you

can implement on a CMOS integrated circuit.

- On the bottom left window, click once on “NMOS”. You should see the symbol of the NMOS transistor

show up in the symbol viewer window at the bottom. –

To place the NMOS, you will click on the “Instance” button. Two things happen when you click on this

button. First, a dialog will appear that will allow you to setup the parameters for the NMOS. Second, the

symbol will attach to your mouse. We will place the NMOS in the schematic first and then set its

properties later. This is an easier way to enter the device. Click in the schematic window to drop an

instance of the NMOS. Hit the “Esc” button to end the insert-mode. Repeat this same step for placing

PMOS transistor.

Enter a DC source/pulse source - Using the same process you used for the NMOS symbol, enter a

“SPICE_Elements: Voltage Source”. This is a generic voltage source symbol that is configured as a DC,

TRAN, PWL, etc.. in its properties dialog.

g) Enter Vdd and Gnd: Using the same process you used for the NMOS symbol, enter a “Misc:

Vdd” and “Misc: Gnd”.

h) Enter Wires - You can enter wires by clicking on the “wire” icon at the top

Enter wires by clicking on a symbol node and then dragging. Enter corners by clicking once where

you want to turn.

i) Entering the Ports: Ports are entered using the icons on the top of the S-edit window. Enter the

following: In Port: Name it “IN” Out Port: Name it “OUT”

j) Setup – SPICE Simulations

Using the pull down menus: - Setup → SPICE Simulations -

On the left, click on “Transient/Fourier Analysis”

On the right, enter the following

Stop time-600ns,maximum time step -10ns,print start time-1ns,print time step-10ns

Click on General-Library file and browse” Tanner EDA/Tanner Tools

v15.0/Process/Generic_250nm/Generic_250nm_Tech/Generic_250nm.lib tt”

k) Simulate the Design

- Click on the Green Arrow to start the simulator: The T-Spice window will appear. If everything is OK,

the waveform viewer will also appear.


96



l) Create the Inverter Symbol Symbols can either be created manually by creating a new symbol

view or automatically by S-edit. Remove DCsource and pulse source.

Click on cell- generate symbol- modify. Now we can draw our own symbol.

Result:

The schematic of CMOS NOT, NAND, NOR , EX-OR and Boolean expression was drawn using S-Edit and simulated.


97



Ex No.18 LAYOUT OF INVERTER AIM:

To draw the layout of CMOS inverter using L – Edit and verify the extracted netlist from L - Edit with the netlist extracted from S – Edit using LVS.

APPARATUS REQUIRED: System with P4 Processor & Tanner EDA Tool. THEORY: Tanner EDA is a suite of tools for the design of integrated circuits. These tools allow you to enter schematics, perform SPICE simulations, do physical design (i.e., chip layout), and perform design rule checks (DRC) and layout versus schematic (LVS) checks. There are 3 tools that are used for this process: S-edit-a schematic capture tool. T-SPICE-the SPICE simulation engine integrated with S-edit. L-edit-the physical design tool.

S-Edit: S-edit is a schematic entry tool that is used to document circuits that can be driven forward into a layout of an integrated circuit. It also provides the ability to perform SPICE simulations of the circuits using a simulation engine called T-SPICE.

L - Edit (IC Physical Design Tool): L - edit is an integrated circuit physical design tool from Tanner EDA. This tool allows you to draw the layout of an IC, look at cross - sections, perform DRC (design rule check) , and generate a Netlist of your layout so that you can perform LVS (layout versus schematic) using a different tool.

Layout Versus Schematic (LVS): The Layout Versus Schematic (LVS) is the class of electronic design automation (EDA) verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design. A successful Design rule check (DRC) ensures that the layout conforms to the rules designed/required for faultless fabrication. However, it does not guarantee if it really represents the circuit you desire to fabricate. This is where an LVS check is used.

LVS Checking involves following three steps: 1. Extraction: The software program takes a database file containing all the layers drawn to

represent the circuit during layout. It then runs the database through many area based logic operations to

determine the semiconductor components represented in the drawing by their layers of construction.

These operations are used to define the device recognition layers, the terminals of these devices, the

wiring.

2. Reduction: During reduction the software combines the extracted components into series and

parallel combinations if possible and generates a netlist representation of the layout database. A similar

reduction is performed on the "source" Schematic netlist.

3. Comparison: The extracted layout netlist is then compared to the netlist taken from the circuit

schematic. If the two netlists match, then the circuit passes the LVS check. At this point it is said to be

"LVS clean."


98



SCHEMATIC OF INVERTER

NETLIST GENERATED BY S-EDIT:

NETLIST FOR SCHEMATIC:

****************************************************************************** * SPICE netlist generated by HiPer Verify's NetList Extractor * * Extract Date/Time: Wed Apr 10 15:23:07 2013 * L-Edit Version: L-Edit Win32 15.02.20100805.07:58:22 * * Rule Set Name: * TDB File Name: D:\New Folder\CMOSINV-LSPICE.tdb * Command File: C:\Documents and Settings\placement\My Documents\Tanner EDA\Tanner Tools v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.ext * Cell Name: Cell0 * Write Flat: YES ****************************************************************************** M1 OUT 1 GND_ GND_ NMOS25 l=2.5e-007 w=2.5e-006 ad=2.5e-012 as=2.5e-012 pd=7e-006 ps=7e-006 $(31 21.5 31.25 24) M2 OUT 1 VDD VDD PMOS25 l=2.5e-007 w=4.8e-006 ad=4.8e-012 as=4.8e-012 pd=1.16e-005 ps=1.16e-005 $(31 27 31.25 31.8) * Device count * M(NMOS25) 1 * M(PMOS25) 1 * Number of devices: 2 * Number of nodes: 4 **********************************


99



LAYOUT OF INVERTER:

NETLIST FOR LAYOUT:

* SPICE export by: S-Edit 15.02 * Export time: Wed Apr 10 15:19:17 2013 * Design: not * Cell: not * View: view0 * Export as: top-level cell * Export mode: hierarchical * Exclude empty cells: no * Exclude .model: yes


100



* Exclude .end: no * Exclude simulator commands: no * Expand paths: yes * Wrap lines: 80 characters * Root path: D:\SRI\not * Exclude global pins: no * Exclude instance locations: no * Control property name: SPICE ********* Simulation Settings - General Section ********* *-------- Devices With SPICE.ORDER == 0.0 -------- ***** Top Level ***** MNMOS_2_5v_1 Out In Gnd Gnd NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f PD=4.3u +$ $x=3793 $y=3200 $w=414 $h=600 MPMOS_2_5v_1 Out In Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p PD=7.3u +$ $x=3793 $y=4100 $w=414 $h=600 ********* Simulation Settings - Analysis Section ********* .end

LVS OUTPUT:


101



PROCEDURE:

Export a SPICE Netlist

Exporting a SPICE Netlist is a good idea in order to verify that you have entered the schematic correctly.

Also, this Netlist will be used later when performing a “Layout versus Schematic (LVS)” check.

With the schematic open, use the pull down menus to perform: -

File → Export → Export SPICE. - Browse to your design directory and give the file name

“file name.spc”. - Click “OK”

Launch L-edit,

1. Start → All Programs → Tanner EDA → Tanner Tools v15.0 → L-Edit v15.0

2. Create a new layout design: - File – New - select “Layout” - under “Copy TDB…”, browse to:

\TannerEDA\TannerToolsv15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm_TechSet

up.tdb

- Click “OK”

When you copy in the Generic_025.tbd files, it loads all of the layer definitions for the 0.25um process and

the design rule information. On the left, you should see a set of layers for this technology that can be used

to create devices.

3. select the layers and contact from Layer palette,draw the devices and inter connection with proper

measurement.

4. Run DRC to make sure your dimensions are not violating any design rules - Click on the DRC button in the upper left corner of the screen (little green play arrow). If everything checks out, you should a pop up that says it passed DRC. Extract a SPICE Netlist of Layout

Using the pull down menus, perform: - Tools → Extract You will need to provide an extraction file for

this process (*.ext) - Browse to “..\Generic_025_Kit\Generic_025.ext” You will want to provide a SPICE

output file. Browse to your design directory .

Using LVS (Layout versus Schematic Checking Tool)

- Start → All Programs → Tanner EDA → Tanner Tools v15.0 → LVS v15.0 - Using the pull down menus in the LVS tool, perform: - File →New → Select “LVS Setup” - In the dialog that appears, browse to the Netlist you exported from S-edit

In the dialog that appears, browse to the Netlist you exported from L-edit Click the “Run Verification” icon (little Green arrow) to perform LVS. - If everything matches, you will see a report window that says “Circuits are equal” in red. If it does NOT match, you will be given a report showing what is wrong.


102



Result:

The layout of CMOS inverter using L – Edit was drawn and extracted netlist from L - Edit was verified with the netlist extracted from S – Edit using LVS.
