evikings ii meeting tallinn, march 17, 2003 design and test of digital systems raimund ubar tallinn...

eVIKINGS II MeetingTallinn, March 17, 2003

Design and Testof

Digital Systems

Raimund UbarTallinn Technical University

[email protected]

eVIKINGS II - Meeting, Tallinn, March 17, 2003

Roadmaps

• International Technology roadmap for semiconductors

• MEDEA+ Industry-driven pan-European programme for advanced co-operative R&D in microelectronics

• A dependability roadmap for the information society in Europe


System Design at a Crossroad

• Productivity Crisis– 21% Productivity Increase / Year vs.– 58% Complexity Incease / Year

Technology

ValidationTechniques

DesignMethods

ProductivityCrisis

1988 1992 1996 2000

Productivity

Time

Gates

RTL

IP-

Blocks

0,8

0,6

0,5

0,35

0,18

HW/ SW

Co-Design

(HLS)

Technology

ValidationTechniquesValidationTechniques

DesignMethodsDesignMethodsDesignMethods

ProductivityCrisis

ProductivityCrisis

1988 1992 1996 2000

Productivity

Time

Gates

RTL

IP-

Blocks

IP-

Blocks

0,8

0,6

0,5

0,35

0,18

HW/ SW

Co-Design

HW/ SW

Co-Design

(HLS)

Technology

ValidationTechniques

DesignMethods

ProductivityCrisis

1988 1992 1996 2000

Productivity

Time

Gates

RTL

IP-

Blocks

0,8

0,6

0,5

0,35

0,18

HW/ SW

Co-Design

(HLS)

Technology

ValidationTechniquesValidationTechniques

DesignMethodsDesignMethodsDesignMethods

ProductivityCrisis

ProductivityCrisis

1988 1992 1996 2000

Productivity

Time

Gates

RTL

IP-

Blocks

IP-

Blocks

0,8

0,6

0,5

0,35

0,18

HW/ SW

Co-Design

HW/ SW

Co-Design

(HLS)


Electronic Design Automation (EDA)

• System on a Chip development: Yesterday’s chip is today’s functional block!

New design methodologies are neededNew design methodologies are needed

3.0 1.0 0.5 0.2

20K gatesSchematics & simulation

50K gatesSchematics & Synthesis

500k gatesSimulation,Emulation,Synthesis,

Formal equivalence

2.5 million gates

New Design Paradigm

Source: ICE3.0 1.0 0.5 0.2

20K gatesSchematics & simulation

50K gatesSchematics & Synthesis

500k gatesSimulation,Emulation,Synthesis,

Formal equivalence

2.5 million gates

New Design Paradigm

Source: ICE


Technology trends


Impact of new design technologies on cost

Tall thin engineer

Large block reuse

Intelligent test bench


Landscape of design technology


EDA challenges

• Designers need to increase the level of abstraction, because the amount of information in the designs exceeds their ability to track the information increased use of synthesis technologies

• Necessity to reuse already designed, tested and synthesised functional blocks Intellectual Property (IP)

• Validation: High-Performance simulation tools for the entire design are needed (including early high-level timing validation)

• Improvement of the cooperation of different EDA-tools Standards have to be defined


FW 6 - EuroSoC Key Nodes

Network on chip (Hannu Tenhunen, Sweden) Multiphysics (Marta Rencz, Hungary) Mixed signals (JoseLuis Huertas, Spain) Low power (Christian Piguet, Switzerland) Integrated intelligence (Patrick Dewilde, The

Netherlands)

Test and debug (Ch. Landrault, France) Formal mehtods (Dominique Borrione, France)


FV 6 - EuroSoC Key Nodes

Modeling (Alain Vachoux, Switzerland) Reconfigurable SoC (W. Rosenstiel, Germany –

T. Arslan, UK) Design methods and IP reuse (J. Vounckx,

Belgium – J.C. Lopez, Spain) SoC programming model (E. Villar, Spain) SoC application (N. Wehn, U. Germany –

L.Lavagno, Italy) SoC education (J. Madsen, Denmark)


EuroSoC: Thematic Areas in Test

• Research topics• Digital, Analog, Mixed-Signal, and RF • Failure Analysis, Defect and Fault Modeling

• ATPG, BIST, DFT• Test Synthesis , Test Resource Partitioning and Embedded

Test • Defect/Fault Tolerance and Reliability • Debug and Diagnosis

• Research communities• European Group of the IEEE Test Technology Technical

Council• International Test Conference (ITC), VLSI Test Symposium

(VTS)• European Test Workshop (ETW), DATE C, Online Test

Symposium (IOLTS)


Paradigm Shift in Test

• Sky-rocketing complexities with decreasing pin/gate ratio, higher frequencies and decreasing product life cycles

• New defects due to technology evolution• Hardware/software designs, test of programmable

systems• IP(core)-based designs• Increasing use of analog, mixed-signal and RF IPs • Increase of temporary faults (transient and timing

faults)


Current Status and Barriers to Overcome• Current status

– Testing cost may represent up to 50% of the manufacturing cost of SoC

• Some of the barriers– Development of nanometer fault models

– ATPG, BIST for real defects

– Reduction of test execution time– Power consumption during test– Optimized Test Resource Partitioning strategies– Obsolescence of Iddq testing– Analog BIST – Tolerance of temporary faults – DfD methodology


Testing and Quality

“The problem of testing

can only be contained

not solved”

T.Williams

How much

to test?Cost oftesting

Quality

Cost of quality

Cost

Cost ofthe fault

100%0% Optimumtest / quality

Cost oftesting

Quality

Cost of quality

Cost

Cost ofthe fault

100%0% Optimumtest / quality


Complexity vs. Quality

Problems:

• Traditional low-level test generation and fault simulation methods have lost their importance because of the complexity reasons

• Traditional Stuck-at Fault (SAF) model does not quarantee the quality for deep-submicron technologies


Complexity vs. QualityNew solutions:

• The complexity is handled by raising the abstraction levels from gate to register-transfer, instruction set architecture (ISA) and behavioral levels

– But this moves us even more away from the real life of defects (!)

• To handle adequately defects in deep-submicron technologies, new fault models and defect-oriented test generation methods should be used

– But, this is increasing even more the complexity (!)

• To get out from the deadlock, the both trends should be merged into hierarchical approaches


Research in TTU (ATI)

• Modeling of Digital Systems at different levels – to cope with the complexity

• Test generation and fault simulation– Hierarchical approaches to test generation and fault simulation

Intensive international cooperation:– Joint design and test flow methods and tools (integr. research at ATI)

– BIST (cooper. with U Stuttgart, Uni Linköping, Artec Design)

– Defect-based approach (cooper. With TU Warsaw, Slovak Academy)

– Collaborative design via Internet (Fraunhofer Inst. In Germany)

– New teaching methods, tools, research scenarios (TU Ilmenau)

Subcontractors: in red


DECIDER: Hierarchical ATPG

Logic SynthesisScripts

Design Compiler(Synopsys Inc.)

Gate LevelDescriptions

SSBDD Synthesis

SSBDD Modelsof FUs

Hierarchical ATPG

RTL Model(VHDL)

FULibrary(VHDL)

FULibrary(DDs)

RTL DD Synthesis

Test patterns

RTL DDModel

Logic SynthesisScripts

Design Compiler(Synopsys Inc.)

Gate LevelDescriptions

SSBDD Synthesis

SSBDD Modelsof FUs

Hierarchical ATPG

RTL Model(VHDL)

FULibrary(VHDL)

FULibrary(DDs)

RTL DD Synthesis

Test patterns

RTL DDModel

Modules or subcircuits are represented as word-level Decision Diagrams


Joint VHDL Design and Test Flow

• High-level synthesis– CAMAD developed at

Linköping University

• Test pattern generation– DECIDER developed at

Tallinn Technical University

• Interfaces to – behavioral and RT-level

VHDL and

– EDIF netlist formats

Cooperation with LIU (subcontractor) and in TTU

Behavioral description(VHDL)

RT-Level description(VHDL)

High-levelsynthesis

Logic-levelSynthesis

Gate-level netlist(EDIF)

Hierarchical TestGeneration

Behavioral description(VHDL)

RT-Level description(VHDL)

High-levelsynthesis

Logic-levelSynthesis

Gate-level netlist(EDIF)

Hierarchical TestGeneration


.

ROM. . .

SoC

Core

Co

ntro

ller

• Combining – on-line generated pseudo-

random patterns – with pre-generated and stored

test patterns

• Problems :– To find the best characteristics

for test generator (PRPG)

– To find the best level of mixing pseudo-random test and stored test as the tradeoff between memory cost and testing time

CORE UNDER TEST

Response Analyzer

Test Generator

BIST (Optimization and Hybrid Solutions)

Cooperation with LIU (subcontractor)


International Virtual Lab: Tool integration

Behavioral levelVHDL description

(EAS/IIS)

High-level

RTL VHDLdescription

High-level DDmodel

HierarchicalATPG(TTU)

Test patterns exchange interfaceFunctional test

(EAS/IIS)

Logicsynthesis

Gate-levelEDIF

EDIF-SSBDDconverter (TTU)

SSBDD model

High-levelVHDL description

(EAS/IIS)

Turbo Tester

1 2

3 4

5 6

VHDL-DDconverter(TTU)

EDIF-ISCASconverter (TTU)

8

synthesis

ISCAS-SSBDDconverter (TTU)

9

ISCAS netlist

ISCASbenchmarks

DefGen(IIN)

10 Universitysoftware

11(TTU)

Schematicentry

7

CommercialCAD software

MOSCITOUSER

(EAS/IIS)

Behavioral levelVHDL description

(EAS/IIS)

High-level

RTL VHDLdescription

High-level DDmodel

HierarchicalATPG(TTU)

Test patterns exchange interfaceFunctional test

(EAS/IIS)

Logicsynthesis

Gate-levelEDIF

EDIF-SSBDDconverter (TTU)

SSBDD model

High-levelVHDL description

(EAS/IIS)

Turbo Tester

1 2

3 4

5 6

VHDL-DDconverter(TTU)

EDIF-ISCASconverter (TTU)

8

synthesis

ISCAS-SSBDDconverter (TTU)

9

ISCAS netlist

ISCASbenchmarks

DefGen(IIN)

10 Universitysoftware

11(TTU)

Schematicentry

7

CommercialCAD software

MOSCITOUSER

(EAS/IIS)

Cooperation with EAS/IIS, DresdenEV-subcontractor


Test Generation

BIST Simulation

Methods:DeterministicRandomGenetic

Methods:BILBOCSTPStore/Generate

Design Test

Levels:GateMacro

Fault Simulation

Methods:Single faultParallelDeductive

Fault Table

Fault models:Stuck-at-faultsStuck-opensDelay faults

Test Optimization

Fault Diagnosis

Fault Location

Tools for test generation and fault simulation


Applets for Learning RT Level Test

ForFor learninglearning problems problems ofof RT-level design RT-level design andand test test::

- - DesignDesign - S- Simulationimulation - - FaultFault simulationsimulation - - Test generationTest generation - DFT- DFT - - BISTBIST

Cooperation with TU Ilmenau, Germany – EV subcontractor


Conclusions

• Long term goal of the NoE EuroSoC in Framework 6 :

2003 2005 2007 2010

Get fundingfrom secondFP6 Call and other public

funding

Start Convinceindustry to

partiallyfund thenetwork

Network Fullyfunded byIndustry

evikings ii meeting tallinn, march 17, 2003 design and test of digital systems raimund ubar tallinn...

Documents