ese front end - cecs

ESE Front End

D. Gajski, R. Doemer

(With contribution from A. Gerstlauer, J. Peng, D. Shin)

Center for Embedded Computer SystemsUniversity of California, Irvine

Copyright ©2006, CECSESE Front-End 2

• No basic change in design methodology required• ESE methodology follows present manual design process

• Productivity gain of more then 1000X demonstrated• Designers do not write models

• Simple change management: 1-day change• No rework for new design decisions

• High error-reduction: Automation + verification• Error-prone tasks are automated

• Simplified globally-distributed design• Fast exchange of design decisions and easy impact estimates

• Benefit through derivatives designs• No need for complete redesign

• Better market penetration through customization• Shorter Time-to-Market through automation

Technology Advantages


DecisionUser

Interface (DUI)

ValidationUser

Interface (VUI)

TIMED

Create

Map

Compile

Replace

Select

Partition

Compiler

Debugger

Stimulate

Verify

ES Environment

Application Tools : Compilers/Debuggers Commercial Tools : FPGA, ASIC

CYCLE ACCURATE

Verify

Simulate

Check

Compile

ESE Front – End

System Capture + Platform Development

SW Development + HW Development

ESE Back – End


Platform Architecture

Brid

ge

CPU Mem

HW IP

Components:• Processors• Memories• IPs• Custom HW• Buses• Bridges

Arb

iter


System Definition

Brid

ge

B1 B2

CPU Mem

HW

B3

IP

B4

Arb

iter

Computation • Behaviors (in C)(processes/functions)


System Definition

Brid

ge

v1C

1B1 B2

CPU Mem

HW

B3

IP

B4

C2

System Definition = (Partial) Platform + (Partial) Spec

Arb

iter

Communication• Channels (in C)• Variables (in C)


Output: Application Model

v1C

1B1 B2

B3 B4

C2


Output: Transaction-Level Model (TLM)

CPU Bus

B1 B2

OS

B4

CPU Mem

IP

B3

HW

HALDrivers

IP Bus


Output: Pin-Accurate Model (PAM)

B1 B2

OS

B4

CPU Mem

IP

Arb

iter

Bridge

B3

HW

HAL


System Modifications

Brid

ge

v1C

1B2

CPU Mem

HW IP

B4

C2

Arb

iter

B1

B3B6

B5

C3

TLM is generated/upgraded automatically with changes in Spec or Platform, including:

• Software changes

• Hardware changes

• Communication changes

TLM is generated/upgraded automatically with changes in Spec or Platform, including:

• Software changes

• Hardware changes

• Communication changes


Output: Modified TLM

CPU Bus

B1 B2

OS

B4

CPU Mem

IP

B3

HW

HAL

IP Bus

B6

B5


Output: Modified PAM

B2

OS

B4

CPU Mem

IP

Arb

iter

Bridge

HW

HAL

B1

B3B6

B5


Example: MP3 Decoder

• Functional block diagram (major blocks only)

• Timing constraints• 38 frames per second• Frame delay < 26.12ms

HuffDec

FilterCoreIMDCT

PCM

FilterCoreIMDCT

mp3 pcm

Left channel

Right channel

AliasRed

AliasRed

2 granules


ESE: System Definition

• Allocate and connect system components• Edit processes (C code) inside components• Insert communication channels and variables• Run transaction-level model generator

ARM

Mem

Brid

ge

.

mainBus

HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

FilterCore

FilterCore

Arb

iter

PCMPCM

ch1

ch0

real gainpow2[378];...

pcmBus

ARM

Mem

Brid

ge

.

mainBus

HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

FilterCore

FilterCore

Arb

iter

PCMPCM

ch1

ch0


pcmBus


ESE: TLM SimulationESE – MP3Decoder.ese*ESE – MP3Decoder.ese*

Output

PEs

File Edit

Project

p1.sc

p2.sc

Platform1

Platform2

Ready

PCM MemARM

right

Main

aliasred

imdct

p2_2.sc

Architecture

Sources

ARMARMv7

uCosII

MemSRAM64

PCM

Bridge

mainBusAMBA_AHB Bus2

DoubleHdshk

View Project Simulation Help

Database

CEs Busses

ARMv7

SRAM64

CPUs

Memories

SRAM128

PEs

Platforms

Channels

c1

c2

c3

c_double_handshake

c_handshake

c_semaphore

i_sendi_receive

Synthesis

filtercore

left

aliasred

imdct

filtercore

HardwaresHW_StandardNISC

Simulation logSimulation log

MP3Decoder Input MP3 file : spot1.mp3 Output PCM file: spot1.pcmBitrate = 96000 bits/s, Sampling frequency = 44100 samples/sFrame 1 ... 4.73 ms, meets deadline 26.12 msFrame 2 ... 35.98 ms, missed deadline 26.12 msFrame 3 ... 35.98 ms, missed deadline 26.12 ms

****** Compare spot1.pcm to reference output for correctness…***Diff -s ./testStream/spot1_ref.pcm spot1.pcmFiles ./testStream/spot1_ref.pcm and spot1.pcm are identical

Running simulation …% xterm -e ./mp3decoder funky.mp3 funky.pcm

InstrumentCompile

Simulate...Kill simulation

View log...

• Run simulation on automatically-generated TLMmainBus

OSDrivers

pcmBus

PCM

. HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

FilterCore

FilterCore

ARM

Mem

Bridge PCM

HAL

mainBus

OSDrivers

pcmBus

PCM

. HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

FilterCore

FilterCore

ARM

Mem

Bridge PCM

HAL


Computation Analysis

• View computation time of processes • filtercore is the most computation-intensive

• Look for parallelism in process hierarchy• Left and right filtercore processes can run in parallel

→Use two identical custom HWs

DecodeMP3 time distribution

huffdecprogranule

Comm.

Progranule time distribution

Comm.right

channel

left channel

Channel time distribution

imdct

Comm.

aliasred

filtercore


ESE: System Modification (1)ESE – MP3Decoder.ese*ESE – MP3Decoder.ese*

Output

File Edit

Project

p1.sc

p2.sc

Platform1

Platform2

Ready

p2_2.sc

Architecture

Sources

ARMARMv7

uCosII

MemSRAM64

mainBusAMBA_AHB


Database

CEs Busses

ARMv7

SRAM64

CPUs

Memories

SRAM128

PEs

Platforms

Channels

c1

c2

c3

c_double_handshake

c_handshake

c_semaphore

i_sendi_receivePCM

Bridge

pcmBusDoubleHdshk

HW1 HW2

PEs

HW1 HW2ARM

right

Main

aliasred

imdct

filtercore

left

aliasred

imdct

filtercore

PCM


Synthesis

DisconnectConnect

Add port...

Remove

mainBuspcmBus masterCPU

slaveDisconnectConnect

Add port...

Remove

• Allocate new components from database• Create bus ports for PEs• Connect PE ports to busses

ARM

Mem

Brid

ge

.

mainBus

HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

FilterCore

FilterCore

Arb

iter

PCMPCM

ch1

ch0


pcmBus

HW1 HW2

ARM

Mem

Brid

ge

.

mainBus

HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

FilterCore

FilterCore

Arb

iter

PCMPCM

ch1

ch0


pcmBus

HW1 HW2



Output

File Edit

Project

p1.sc

p2.sc

Platform1

Platform2

Ready

p2_2.sc

Architecture

Sources

ARMARMv7

uCosII

MemSRAM64

mainBusAMBA_AHB


Database

CEs Busses

ARMv7

SRAM64

CPUs

Memories

SRAM128

PEs

Platforms

Channels

c1

c2

c3

c_double_handshake

c_handshake

c_semaphore

i_sendi_receivePCM

Bridge

pcmBusDoubleHdshk

HW1 HW2

PEs

HW1 HW2ARM

right

Main

aliasred

imdct

filtercore

left

aliasred

imdct

filtercore

PCM


Synthesis

Generate Network

Generate TLM

m1 c_double_handshakem2 c_double_handshake

m3 c_double_handshake


m4 c_double_hamdshake

• Move processes to newly allocated PEs• Inter-PE channels are inserted automatically• Run transaction-level model generator

ARM

Mem

Brid

ge

.

mainBus

HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

Arb

iter

PCMPCM

ch1

ch0


pcmBus

HW1 HW2FilterCoreFilterCore

ch3

ch2

ARM

Mem

Brid

ge

.

mainBus

HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

Arb

iter

PCMPCM

ch1

ch0


pcmBus


ch3

ch2



Output

File Edit

Project

p1.sc

p2.sc

Platform1

Platform2

Ready

p2_2.sc

Architecture

Sources

ARMARMv7

uCosII

MemSRAM64

mainBusAMBA_AHB


Database

CEs Busses

ARMv7

SRAM64

CPUs

Memories

SRAM128

PEs

Platforms

Channels

c1

c2

c3

c_double_handshake

c_handshake

c_semaphore

i_sendi_receivePCM

Bridge

pcmBusDoubleHdshk

HW1 HW2

PEs

HW1 HW2ARM

right

Main

aliasred

imdct

left

aliasred

imdct

PCM


Synthesis






MP3Decoder Input MP3 file : spot1.mp3 Output PCM file: spot1.pcmBitrate = 96000 bits/s, Sampling frequency = 44100 samples/sFrame 1 ... 9.39 ms, meets deadline 26.12 msFrame 2 ... 28.45 ms, missed deadline 26.12 msFrame 3 ... 28.45 ms, missed deadline 26.12 ms

****** Compare spot1.pcm to reference output for correctness…***Diff -s ./testStream/spot1_ref.pcm spot1.pcmFiles ./testStream/spot1_ref.pcm and spot1.pcm are identical

InstrumentCompile


View log...

Running simulation …% xterm -e ./mp3decoder spot1.mp3 spot1.pcm

Bus UtilizationBus UtilizationBus ContentionBus Contention

mainBus

OSDrivers

pcmBus

PCM

. HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

ARM

Mem

Bridge PCM

FilterCore

HW1

FilterCore

HW2

HAL

mainBus

OSDrivers

pcmBus

PCM

. HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

ARM

Mem

Bridge PCM

FilterCore

HW1

FilterCore

HW2

HAL

• Run simulation on automatically-generated TLM• Display over-the-time bus activity


Bus Contention Analysis

ARM

IDLE

HW2

HW1

HW1

HW2

None

• Bus priority: ARM > HW1 > HW2

HW2

None

Waiting time when ARM uses bus Waiting time when HW2 uses bus

Usage Distribution for mainBus



Output

File Edit

Project

p1.sc

p2.sc

Platform1

Platform2

Ready

p2_2.sc

Architecture

Sources

ARMARMv7

uCosII

MemSRAM64

mainBusAMBA_AHB


Database

CEs Busses

ARMv7

SRAM64

CPUs

Memories

SRAM128

PEs

Platforms

Channels

c1

c2

c3

c_double_handshake

c_handshake

c_semaphore

i_sendi_receivePCM

pcmBusDoubleHdshk

HW1 HW2

PEs

HW1 HW2ARM

right

Main

aliasred

imdct

left

aliasred

imdct

PCM


Synthesis





DisconnectConnect

Add port...

Remove

mainBuspcmBus masterCPU

slave

Generate Network

Generate TLM

Bridge

DisconnectConnect

Add port...

Remove

• Remove components and connections• Change connectivity• Run transaction-level model generator

ARM

Mem

Brid

ge

.

mainBus

HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

Arb

iter

PCMPCM



ch3

ch2

pcmBusch1

ch0

ARM

Mem

Brid

ge

.

mainBus

HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

Arb

iter

PCMPCM



ch3

ch2

pcmBusch1

ch0



Output

File Edit

Project

p1.sc

p2.sc

Platform1

Platform2

Ready

p2_2.sc

Architecture

Sources

ARMARMv7

uCosII

MemSRAM64

mainBusAMBA_AHB


Database

CEs Busses

ARMv7

SRAM64

CPUs

Memories

SRAM128

PEs

Platforms

Channels

c1

c2

c3

c_double_handshake

c_handshake

c_semaphore

i_sendi_receivePCM

pcmBusDoubleHdshk

HW1 HW2

PEs

HW1 HW2ARM

right

Main

aliasred

imdct

left

aliasred

imdct

PCM


Synthesis






MP3Decoder Input MP3 file : spot1.mp3 Output PCM file: spot1.pcmBitrate = 96000 bits/s, Sampling frequency = 44100 samples/sFrame 1 ... 9.31 ms, meets deadline 26.12 msFrame 2 ... 25.33 ms, meets deadline 26.12 msFrame 3 ... 25.33 ms, meets deadline 26.12 ms

****** Compare spot1.pcm to reference output for correctness…***Diff -s ./testStream/spot1.pcm spot1.pcmFiles ./testStream/spot1.pcm and spot1.pcm are identical

InstrumentCompile


View log...

Running simulation …% xterm -e ./mp3decoder spot1.mp3 spot1.pcm

Bus ContentionBus Contention Bus UtilizationBus Utilization

mainBus

OSDrivers

PCM

. HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

ARM

Mem

PCM

FilterCore

HW1

FilterCore

HW2

pcmBus

HAL

mainBus

OSDrivers

PCM

. HuffEnc

AliasRed

AliasRed

IMDCT

IMDCT

ARM

Mem

PCM

FilterCore

HW1

FilterCore

HW2

pcmBus

HAL

• Run simulation on automatically-generated TLM• Display over-the-time bus activity


Design Summary

Frame Delay (ms)

0

10

20

30

40

TLM1 TLM2 TLM3

mainBus Utilization

0

0.1

0.2

0.3

0.4

0.5

TLM1 TLM2 TLM3

mainBus Contention

0

0.002

0.004

0.006

0.008

TLM1 TLM2 TLM3

Deadline: 26.12


ESE Advantages

• Platform and application can be easily captured using GUI

• TL models are automatically generated• ESE allows concurrent development of platform SW,

HW and application code• ESE allows easy upgrade of platform• ESE simplifies reuse of legacy application SW and

RTL HW code

ese front end - cecs

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