ert/sert algorithm (1/16)practical problems in vlsi physical design elmore routing tree (ert)...
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![Page 1: ERT/SERT Algorithm (1/16)Practical Problems in VLSI Physical Design Elmore Routing Tree (ERT) Algorithm Perform ERT algorithm under 65nm technology Unit-length](https://reader036.vdocuments.site/reader036/viewer/2022082709/56649f585503460f94c7d773/html5/thumbnails/1.jpg)
Practical Problems in VLSI Physical Design ERT/SERT Algorithm (1/16)
Elmore Routing Tree (ERT) Algorithm Perform ERT algorithm under 65nm technology
Unit-length resistance r = 0.4 Ω/μm Unit-length capacitance c = 0.2 f F/μm
Driver output resistance rd = 250 Ω
Sink input capacitance r = 50 f F
![Page 2: ERT/SERT Algorithm (1/16)Practical Problems in VLSI Physical Design Elmore Routing Tree (ERT) Algorithm Perform ERT algorithm under 65nm technology Unit-length](https://reader036.vdocuments.site/reader036/viewer/2022082709/56649f585503460f94c7d773/html5/thumbnails/2.jpg)
Practical Problems in VLSI Physical Design ERT/SERT Algorithm (2/16)
Adding First Edge Simply add the nearest neighbor to the source
Add (s,a)
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Practical Problems in VLSI Physical Design ERT/SERT Algorithm (3/16)
Adding Second Edge Rule: each node in T can connect to its nearest neighbor
Two edges to consider: (a,b), (s,c) Elmore delay calculations shown on next slides
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Practical Problems in VLSI Physical Design ERT/SERT Algorithm (4/16)
Elmore Delay Calculation Case 1: edge (a,b)
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Practical Problems in VLSI Physical Design ERT/SERT Algorithm (5/16)
Elmore Delay Calculation (cont) Case 2: edge (s,c)
It is easy to see that t(c) > t(a) Elmore delay is t(c) = 2035ps Thus, we add (s,c) to minimize maximum Elmore delay
![Page 6: ERT/SERT Algorithm (1/16)Practical Problems in VLSI Physical Design Elmore Routing Tree (ERT) Algorithm Perform ERT algorithm under 65nm technology Unit-length](https://reader036.vdocuments.site/reader036/viewer/2022082709/56649f585503460f94c7d773/html5/thumbnails/6.jpg)
Practical Problems in VLSI Physical Design ERT/SERT Algorithm (6/16)
Adding Third Edge Three edges to consider: (a,b), (s,d), (c,d)
Elmore delay: t(b) = 4267.5ps, t(d) = 2937.5ps, t(d) = 5917.5ps Add (s,d)
t(c) = 2937.5ps
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Practical Problems in VLSI Physical Design ERT/SERT Algorithm (7/16)
Adding Fourth Edge Four edges to consider: (a,b), (s,b), (c,b), (d,b)
In all these cases, delay to b is the maximum t(b) = 4630ps, 4720ps, 10720ps, 8310ps, respectively Add (a,b)
t(b) = 4630ps
![Page 8: ERT/SERT Algorithm (1/16)Practical Problems in VLSI Physical Design Elmore Routing Tree (ERT) Algorithm Perform ERT algorithm under 65nm technology Unit-length](https://reader036.vdocuments.site/reader036/viewer/2022082709/56649f585503460f94c7d773/html5/thumbnails/8.jpg)
Practical Problems in VLSI Physical Design ERT/SERT Algorithm (8/16)
Final ERT Result Maximum Elmore delay is t(b) = 4630ps
No Steiner node used Star-shaped topology
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Practical Problems in VLSI Physical Design ERT/SERT Algorithm (9/16)
Steiner Elmore Routing Tree (SERT) Perform SERT algorithm under 1.2μm technology
Unit-length resistance r = 0.073 Ω/μm Unit-length capacitance c = 0.083 f F/μm
Driver output resistance rd = 212 Ω
Sink input capacitance r = 7.1 f F
![Page 10: ERT/SERT Algorithm (1/16)Practical Problems in VLSI Physical Design Elmore Routing Tree (ERT) Algorithm Perform ERT algorithm under 65nm technology Unit-length](https://reader036.vdocuments.site/reader036/viewer/2022082709/56649f585503460f94c7d773/html5/thumbnails/10.jpg)
Practical Problems in VLSI Physical Design ERT/SERT Algorithm (10/16)
First Iteration Simply add the nearest neighbor to the source
Add (s,a)
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Practical Problems in VLSI Physical Design ERT/SERT Algorithm (11/16)
Second Iteration Rule: each node not in T can connect to each edge in T
using a Steiner point or directly to source 6 edges to consider: (a,b), (s,b), (p,d), (s,d), (p,c), (s,c) Node p is a Steiner node
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Practical Problems in VLSI Physical Design ERT/SERT Algorithm (12/16)
Second Iteration (cont) Case (e) results in minimum delay: t(c) = 268.6ps
Add (p,c)
t(c) = 268.6ps
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Practical Problems in VLSI Physical Design ERT/SERT Algorithm (13/16)
Third Iteration 7 edges to consider
t(d) = 413.3ps
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Practical Problems in VLSI Physical Design ERT/SERT Algorithm (14/16)
Fourth Iteration 6 edges to consider
t(b) = 606.3ps
t(d) = 557.3ps
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Practical Problems in VLSI Physical Design ERT/SERT Algorithm (15/16)
Final SERT Result Maximum Elmore delay is t(b) = 606.3ps
Two Steiner nodes used
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Practical Problems in VLSI Physical Design ERT/SERT Algorithm (16/16)
ERT vs SERT Not a fair comparison
Technology parameters are different (65nm vs 1.8μm)
t(b) = 4630ps t(b) = 606.3ps