compact model challenges of 65nm rf65nm rf- ---cmos
TRANSCRIPT
Copyright 2008, Toshiba Corporation.
Compact Model Challenges of Compact Model Challenges of Compact Model Challenges of Compact Model Challenges of
65nm RF65nm RF65nm RF65nm RF----CMOS technologyCMOS technologyCMOS technologyCMOS technology
TOSHIBACorp. Semiconductor CompanySadayuki Yoshitomi ([email protected])Tadamasa Katoh ([email protected])Toshifumi Nakanose ([email protected])Fumie Fujii ([email protected])
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 2
CMOS Technology Innovation
CMOS1BSIM3
0.13um
90nm
0.18um
0.25um
0.35um
65nm
40nm
32nm
CMOS2BSIM3・・・・EKV
CMOS3BSIM3・・・・EKV*
CMOS4BSIM4・・・・EKV*
CMOS5BSIM4・・・・PSP・・・・EKV*
CMOS6????
CMOS7????
1995
STIDual Gate / Ti Salicide
Logic Based eDRAM
Cu Interconnect
Low k
Stress controlLow-k II
Strained-Si, High-kLow-k III
Metal Gate High-k
Toshiba’s been a leaderfor many process generations
Release RF-CMOS Technology from 0.13um
CMOS306/Q2
CMOS407/Q2
CMOS508/Q2
EKV available for internal use only
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 3
10
100
1000
10 100 1000
Toshiba
TSMC
NXP
ITRS
Cut-off Frequency [GHz]
Lg [nm]
fT Trend and Benchmarking
TOSHIBA’’’’ssss
CMOS5
(65nm)
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 4
Agenda
• Challenges of RF scalable model creation of 65nm RF -CMOS technology– Methodology of creation of RF-CMOS scalable model
– Observation of “RF-scaling law”
– Extensional validation issues.
• RF Switch
• High-linear circuits
D iode
C JDB
D iode
C JDS
R
R S UB2
P ort
D R A IN
N um = 2
L
LD
R
R D
R
R S UB1
R
R S UB4
R
R S UB3
C
CFGS
C
CFGD
R
R S
L
LG
R
RG
L
LS
P ort
S O U R C E
N um = 3
P ort
G A TE
N um = 1 M O S F E T_N M O S
c 3_fas t_n
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 5
What is needed for RF-CMOS compact model ?• Scalable and compact
– For portability, parasitic elements should be scalable function of • Lg (Gate Length)• Wf (Finger Length)• NF (Finger Numbers)• (SA,SB,SD)
• Accurate for all design purpose– LNA (NQS effect, Thermal noise)
• Linear: S-parameters > 100GHz– De-embedding: SOLT ? TRL ?
– VCO and Mixer (Harmonic distortion, Flicker noise)• Flicker noise close to the carrier.• ACPR, EVM
– Power amplifier• Self Heating• Load-pull
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 6
MOSFET : Extrinsic Parasitic elements
Yuhua Cheng et al.(2000b) MOSFET modeling for RF circuit design, Proceeding of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems, D23/1-D23/8
Gm*vgs+Gds*Vds
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 7
Simplified Equivalent Circuit when MOSFET= OFF
Port
SB
Num=2
R
RDB
R
RDSB
Port
G
Num=2
Port
D
Num=2
R
RD
Diode
CBDR
RG
C
CGBpulsCGS
I_DC
Gm+Gds
C
CFGD1
Source and Back-gate groundedVG=VD=VS=VB=0
∞
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 8
Equivalent Circuit when MOSFET= SI & Linear
Port
SB
Num=2
R
RDB
R
RDSB
Port
G
Num=2
Port
D
Num=2
R
RD
Diode
CBDR
RG
C
CGBpulsCGS
I_DC
Gm+Gds
C
CFGD1
Source and Back-gate groundedVG=VDD, VD=low, VS=VB=0
R
gdsRDSB
RDB
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 9
Measure of components from y-parameters
( ) ( )( ) ( )
CBCDCSG
GDBDmGDGDGBDGGDS
mGDmGDGGm
GGDG
GG
GGGC
CCjωCCCCCCRωGY
CCjωCCCRωGY
jωCCRωY
jωRCωY
++=+++++≈
+−+−≈
−−≈
+≈
222
221
212
2211
GD
G
C
C
( )( )( )( )12
1211
1222
12
Re
Im
Im
Im
ZR
YYCC
YYC
YC
DB
GSGB
DB
GD
→+→++=
=
Starting point the formula (12.7a~12.7d) : Christian C.Enz, Eric A. Vittoz , “Charge-based MOS Transistor Modeling” Wiley 2006.
( )( )
( ) ( )
=
=
=
22
211
11
1Re
Im
Re
YR
RR
Y
YR
DSB
SD
G
22ZRe
SI and linear region OFF region
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 10
Q1
• Does RG scaling follows classical ohmic-law ?
NfLg
WfkR rgG ⋅
⋅= ρ
K : constant depending on the configuration of gate contact
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 11
NO : Gate resistance behaves complex behavior
0
1
2
3
4
5
0.01 0.1 1 10
Lg [um]
No
rma
lize
d g
ate
re
sist
an
ce
Scaling dependence of Rg on gate-length (Lg)
LV NMOSFET
Wf=1um, NF=40
Lg -1
Lgmodel
Meas.
0
1
2
3
4
5
0.01 0.1 1
Lg [um]
No
rma
lize
d R
g
+
g
RGLg
f
RGL
L
KL
N
K 21
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 12
Scaling dependence of Rg on Wf/Nf
0
1
2
3
4
5
0 0 .0 5 0 .1 0.1 5
W f/ N f
No
rma
lize
d R
G
LV NMOSFET
Lg=50nm
Wf*NF=40um
model
Meas.NF*Wf-1
NF*Wf
2um*20
0.5um*80
1.0um*40
+
f
RGLf W
KW 3
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 13
Q2 Does capacitance scaling has unique behaviour ?
• NO : It is typical behavior
( )( )( )1211
1222
12
Im
Im
Im
YYCC
YYC
YC
GSGB
DB
GD
+→++→
→
0
1
2
3
4
5
0.01 0.1 1 10Lg [um]
No
rmal
ize
d C
ap
aci
tan
ce
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
0.001 0.01 0.1 1
Wf/Nf
No
rma
lize
d C
aa
cita
nce
CGB+CGS
CGD
CDB
CGB+CGS
CGD
CDBShorter Wf
More # of NF
CGB
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 14
Observation of the RB scaling
0
2
4
6
8
10
12
0.01 0.1 1 10
Lg [um]
No
rma
lize
d R
B
0
0.5
1
1.5
2
2.5
3
0 5 0 100 150 200
Wf*NF
No
rma
lize
d R
B
NF-1*Wf-1
NFWfRsh
NF
WfLgRsh
⋅⋅+⋅⋅ 1
21
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 15
RF-CMOS modeling summary
ffRCL NWK
CGBG-B capacitance
RSUB1
RSUB2
RSUB3
RSUB4
Substrate resistance
CFGD CFGS
G-D,G-S overlap capacitance
RG
NQS
Gate resistance
Geometric
dependencyItem nameComponent name
+
+
f
RGLf
g
RGLg
f
RGL
W
KW
L
KL
N
K 321
KCGB,KRGL1, KRGL2, KRGL3,KRCL,KRsh1, KRsh2 : Constants
NfLgKCGB CGB ⋅⋅=
NFWfRsh
NF
WfLgRsh
⋅⋅+⋅⋅ 1
21
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 16
Verification of 65nm RF-CMOS via peak-fT
1.00E+09
1.00E+10
1.00E+11
1.00E+12
1.00E-08 1.00E-07 1.00E-06 1.00E-05
Lg [m]
Pe
ak
fT
[H
z]
NMOS
PMOS
model
Meas.
LV MOSFETsWf=1um Nf=40
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 17
Model VerificationImprove
NMOSFET Lg=0.3um Wf=20um NF=100
S D
GDeepNwell Pwell
LINE1
LINE2LINE3
449.6145.93Pwell-RPOLY-PADLINE3192.4844.39GATE-RPOLY-PADLINE2
35525.04DeepNwell-RPOLY-
PADLINE1
Lngth of M6S [um]
Length of M1 [um]
PATH
Line width all 0.3um
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 18
MOSFETMOSFETMOSFETMOSFET----SwitchSwitchSwitchSwitch
RF1
Gate(Vg)
RF2
BackGate(Vbg) D-Nwell(Vdn)
FET
R=10kΩ(All)
PSUB
D-Nwell B-GateSource
GateDrain
Psub
Deep-Nwell
n
p
n+ n+
STI
寄生ダイオードの導入が必要
P-N Diode
Define
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 19
5 Term MOS
BSIM4_NMOS
CORE
Port
G
Num=2
Port
DNW
Num=2
Port
PW
Num=4
Port
PSUB
Num=5
Diode
Dpsubwb
Diode
Dwpwb
C
CGB1
Port
S
Num=3
R
RS
Port
D
Num=1
R
RD
R
RG
R
RSUB2
R
RSUB1
R
RSUB3
R
RSUB4
Diode
Djds
L
LD
L
LS
L
LG
C
CFGS
C
CFGD
Diode
Djdb
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 20
Simulation does not match
– NMOSFET Lg=0.3um Wf=20um NF=100• 50MHz~20.05GHz (201 PTS))))
• VG, V_DNW::::0V,2.5V
• VD=VS=0V
Blue:Meas
Red::::Model
Define
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 21
Hard Implemantation
Cov_hkRGBCGB
DIO_CJO
Rline1
Rline2
Rline3
Cov_CJW
Analyze
Cpad
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 22
Transmission Line
– Lind:Self inductaoce– Rind:Series Resistance– Cox:Cap between Metal and Si– Rs:Loss of Si substrate– Cs:Loss of Si substrate
2.482.031.072.031.972.93Cs [fF]
6094361422436771.5697Rs [Ohm]
7.893.223.373.226.221.86Cox [fF]
21.66.899.266.8917.13.82Rind [Ohm]
0.390.040.170.050.310.02Lind [nH]
M6SM1M6SM1M6SM1
LINE3LINE2LINE1
Improve
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 23
Completed schematicImprove
5term MOS
LINE1
transLine
LINE1
TransLine
LINE2
TransLine
LINE2
TransLine
LINE3
TransLine
LINE3
Transline
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 24
Comparison before and afterImprove
1E9 1E101E8 3E10
-30
-25
-20
-15
-10
-5
-35
0
freq, Hz
S2
1 [
dB
]
SWEEP.freq, Hz
Eqn Dev=100.9+130.8+207.1+132.0
Dev
570.800
1E
9
1E
10
1E
8
3E
10
5.0E3
1.0E4
0.0
1.5E4
SWEEP.freq, Hz
ma
g(S
21
_e
rr)
VDNW
0.000E02.500E0
Sum_S21_ErrVgsh=0.000E0 Vgsh=2.500E0
1.009E2 1.308E22.071E2 1.320E2
1E9 1E101E8 3E10
-30
-25
-20
-15
-10
-5
-35
0
freq, HzS
21
[d
B]
SWEEP.freq, Hz
Eqn Dev1=5.862+5.202+1.234+0.726 Dev1
13.024
1E
9
1E
10
1E
8
3E
10
20
40
60
0
80
SWEEP.freq, Hz
ma
g(S
21
_e
rr)
VDNW
0.000E02.500E0
Sum_S21_ErrVgsh=0.000E0 Vgsh=2.500E0
-1.234E0 -5.862E0-7.260E-1 -5.202E0
Before after
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 25
freq (50.00M Hz to 20.05G Hz)
(S(2
,1))
SW EEP.freq (50.00M Hz to 20.05G Hz)
(zY
68
_I_
fet0
1_
m..
sp
ar_
vg
0.I
CC
AP
_S
WE
PT
_D
AT
A.X
FO
RM
.sd
(2,1
))(z
y6
8_
I_fe
t01
_m
..s
pa
r_v
g2
p5
.IC
CA
P_
SW
EP
T_
DA
TA
.XF
OR
M.s
d(2
,1))
freq (50.00M Hz to 20.05G Hz)
(S(1
,1))
SW EEP.freq (50.00M Hz to 20.05G Hz)
(zy
68
_I_
fet0
1_
m..
sp
ar_
vg
0.I
CC
AP
_S
WE
PT
_D
AT
A.X
FO
RM
.sd
(1,1
))(z
y6
8_
I_fe
t01
_m
..s
pa
r_v
g2
p5
.IC
CA
P_
SW
EP
T_
DA
TA
.XF
OR
M.s
d(1
,1))
freq (50.00M Hz to 20.05G Hz)
(S(2
,1))
SW EEP.freq (50.00M Hz to 20.05G Hz)
(zY
68
_I_
fet0
1_
m..
sp
ar_
vg
0.I
CC
AP
_S
WE
PT
_D
AT
A.X
FO
RM
.sd
(2,1
))(z
y6
8_
I_fe
t01
_m
..s
pa
r_v
g2
p5
.IC
CA
P_
SW
EP
T_
DA
TA
.XF
OR
M.s
d(2
,1))
freq (50.00M Hz to 20.05G Hz)
(S(1
,1))
SW EEP.freq (50.00M Hz to 20.05G Hz)
(zy
68
_I_
fet0
1_
m..
sp
ar_
vg
0.I
CC
AP
_S
WE
PT
_D
AT
A.X
FO
RM
.sd
(1,1
))(z
y6
8_
I_fe
t01
_m
..s
pa
r_v
g2
p5
.IC
CA
P_
SW
EP
T_
DA
TA
.XF
OR
M.s
d(1
,1))
S-Parameter before and afterImprove
Before After
S21
S11
S21
S11
Copyright 2008 TOSHIBA Corporation MOS-AK Meeting 2008 Edinburgh 26
Summary
• 65nm-RFCMOS compact models’ development– Scaling approach based on COLD-measurement and SI & Linear
measurement still works.
– It is possible to get a simple guess by taking look at Y and Z parameters.
– Substrate modeling is needed in case of RF switch which controls back-gate bias.
– All possible modeling efforts by the aid of EM simulation is sure needed.
Thank you !